TWI334256B - Power factor correction circuit and method of varying switching frequency - Google Patents

Description

1334256 IX. Description of the invention: [Technical field to which the invention pertains] In general, the present invention relates to an integrated circuit, and more specifically _ + ^ relates to an integrated power factor correction circuit. [Prior Art]

, J " Thousands of people, (2) _H draw current from the alternating current (AC) mains only when it is close to its peak voltage level (rather than during the entire cycle). Also "丨cq々 is always matched.. The peak voltage of all users in Zhouluzhong is in between, and the total of six female fruits is to make the network generator negative at the peak of the voltage /...·" W current, and in | At his time there is little or no current. The load, distortion, + line current in the three-phase distribution network is high, and the second is the possible failure of the device. In order to avoid line distortion, the land == division is forced to expand its distribution network, which requires a large capital investment. Some governments are trying to incorporate the power factor correction (pFc) by requiring the system manufacturer to Mitigating the T'· IEC1000-3-2^iA^. 砀 For example, the European Regulation 2 requires that in the lighting system and some other electrical wear: the source has a coffee, usually implemented by a PFC circuit, etc., =遂 is greater than the frequency of the mains frequency via the coil and then the electric current is then passed through a _1 _1 deep current 'sub-establishment of a coil current is released into a capacitor, v adjusted DC (direci current; DC) for 瘅泰Power supply system. The current exchange is controlled so that the turbulent value of the turbulent value of the fish-scale coil is proportional to the electric current and the mains voltage, that is, the power obtained by the in-phase and the substantial chord method is 0 995 ge larger / the upper watt is a positive wattage Larger, with 1.0 as the ideal 9l803.doc 1334256 value. A major portion of the previous PFC circuit operates in a continuous conduction mode in which a new switching cycle is initiated before the coil current of the previous month's cycle is released to zero. The continuous conduction mode P F C system requires a high performance coil and a blocking diode with fast recovery time to maintain efficient power conversion. However, the high cost of the high performance coil and the blocking diode increases the manufacturing cost of the continuous mode PFC system. Moreover, such systems typically operate at a fixed switching frequency, thereby producing a high peak energy that requires an expensive filter to suppress the resulting electromagnetic interference (EMI). Other PFC systems operate in a critical or boundary conduction mode where the coil current just reaches zero. The new switching cycle provides a high power factor f' but operates over a wide range of switching frequencies. It is complicated and expensive to suppress EM. In addition, under the force rate condition, the parent switching frequency is so high that the propagation delay in the pFC circuit reduces the achievable power factor. ,: His PFC circuit operates in a discontinuous mode, in which the coil current can decay to zero during each exchange: time period in the garment. This can be first exchanged with -m (four) to reduce the bribe spectrum and allow the use of 乍^EMim 1, similar to the continuous conduction mode circuit, these systems are owed by a single _ bottle. Xuan Li + ancient 丨The frequency of the ray is the peak energy level, which may be difficult to suppress even with a narrow band. Therefore, Xue Yi, Shi Yi, PFC circuit and party exchanged within the scope of party control to reduce the EMI filtering cost of the electrical system. 9l803.doc 1334256 SUMMARY OF THE INVENTION Elements having the same code in the figure have similar functions. 1 is a schematic diagram of a power factor correction (PFC) circuit for correcting the power factor of an alternating current (AC) mains that operates under a sinusoidal Ac voltage VAC and provides a load current to a load 28. Il〇ad. The pFc circuit 1 is controlled by a PFC control circuit 10 operating in a discontinuous mode and having a supply voltage Vcc = i2 〇 volts, and includes an electromagnetic interference (emi) filter state 15, a capacitor 19, a diode Bridge 2, resistor "to and", an inductor or coil 25, a blocking diode 26 and an output capacitor 27. The PFC private circuit generates a direct current (dc) output voltage V〇ut 0 at an output node 3〇. [Embodiment] 5. The PFC circuit 1 is modified by the power factor at the input node 32. Providing a high power factor to the AC mains, the node operates at a input voltage Vin obtained by rectifying the VAC. In effect, the pFc circuit 1 〇 0 uses feedback to create a resistive load between the node 32 and the negative terminal of the bridge, which operates at ground potential in the particular embodiment of FIG. Thus, the average value of the current flowing through node 32 and thus through the AC mains is in phase with v.... In particular, the PFC circuit 1 is used as a boost switching regulator, in which resistors 16 to 17 are used as a slave to establish a boost to a level above the VAC peak. . In a specific embodiment, when the value of VAC is —-100 volt root mean square (RMS) and the frequency is about 50 Hz, the output power of the PFC circuit (10) is approximately Four hundred volts DC. In some geographical areas where the value of VAC is approximately -100-ten volts root mean square (RMS) 9t803.doc Ϊ 334256 and the frequency of V〇ut is approximately sixty hertz, the VOUT value of the pFC circuit 1 约为 can be approximately Two hundred and thirty volts volts (: The size of the pFc circuit component can be selected, the breakdown voltage, etc., so that the system that sets ν〇υτ to about 400 volts dc can operate on almost any trunk line in the world. These systems are called universal Trunk system. In most areas, the general range of VAC is approximately plus or minus twenty percent. In an alternative embodiment, the PFC circuit is configured to combine a power factor correction function with a voltage regulator. In a single stage, the VOUTW voltage generated is lower than the peak VAC voltage. For example, resistors 16 through 17 may be selected such that the PFC circuit 100 provides an EMI filter 15 having a level of, for example, 5 volts as a low pass filter, It suppresses the high frequency switching signals generated by the PFC circuit 100 by the low frequency components of the VAC. In a specific embodiment, the EMI filter 15 is configured to reject signal components above one kilohertz. a standard full wave A bridge rectifier rectifies the line voltage vac and produces a rectified sinusoidal input voltage να at node 32 at a frequency of twice the VAC frequency or about one hundred hertz and a peak value of about three hundred to ten volts. The VAC noise is further reduced at both ends of the diode bridge 20. The inductance Lm of the coil 25 is generally loo.o micro-henry and has a low equivalent series resistance for efficient operation. The PFC control circuit 10 includes A transistor 29, a pulse width modulated (PWM) control circuit 31 and an oscillator 35. The PWM control circuit 10 receives a clock signal CLK from the oscillator 35 and triggers 9l803.doc 1334256

It is called a drive series V D R [ v E and switches the pulse series of transistors 29. Resistors 16 and 17 are used as a voltage divider to divide the output voltage ν 〇υ τ & and generate a feedback signal Vfb at an input 36. In a specific embodiment, pwM

The reference voltage generated internally in Winter 1 is compared to modulate the width of the vDR1VE pulse. Thus, when the load 28 draws the increased load current ILOAD to discharge the capacitor 27 and reduces the output voltage ν〇υτ, the level of the feedback voltage vFB is correspondingly lower. In response, the pWM control circuit 3 1 increases the width of the VDRIVE pulse, thereby increasing the charge transferred from the coil 25 to the capacitor 27 to adjust the V〇UT to its designated level. Therefore, if the load current IL 〇 AD is kept constant with respect to the frequency of VIN or about one hundred and twenty Hz, the PWM control circuit 3 is configured such that the width of the Vdrive pulse remains constant in one cycle. In one embodiment, the pFC control circuit 1 is adapted to be integrated on a semiconductor die to form an integrated circuit. The transistor 29 is a high-core channel MOSFET that exchanges the coil current w via the coil 25. In one embodiment, the transistor 29 is a power transistor capable of exchanging Ic〇1 having a peak greater than two amps. The transistor 29 typically has a larger gate capacitance - greater than five hundred picofarads. The transistor 29 is shown integrated with a further component of the PFC control circuit 1A on a die, but can also be formed as an external discrete device. Where the electric raft, the claw component ICHG and a discharge current component Idschg.眭 狡 & * >&______

To be constant. When the transistor 29 is turned off, the coil current I c Ο IL has a charge of 充 、, y V τ 〜 入 入 入 入 〜 〜 〜 〜 〜 〜 〜 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' t t t t t t t t t t Magnetic energy as discharge current 9I803.doc -10- 1334256

Whg flows from line 25 through blocking diode 26 to capacitor 27 to establish an output (4) V coffee at node π. The time during which the discharge current Whg flows is referred to as a discharge period TDSCHG', which varies according to the peak value of the discharge current τ(10) and the voltage level of v[N. The oscillator 35 is configured as a voltage controlled oscillator having an input 39 for sensing - the input current I from the input voltage V1N is input 39 operating near the ground potential 'so the IlN is almost equal to % 8, where r Think of the resistance of resistor W. Since the shape of VIN is a rectified sine wave, & also has a rectified sinusoidal shape, which thus represents V[N. An output provides a clock signal clk whose frequency changes according to IIN. In a specific embodiment, the amplitude of Iin is selected such that the clock signal CLK changes within a range of less than two to one, which is significantly less than the switching frequency range of the critical conduction mode PFC circuit, the spectrum of which often covers twenty to - or more Large range. In a particular embodiment, the oscillator suppresses a nominal frequency of - about forty kilohertz and - CLK ranging from about thirty kilohertz to about fifty kilohertz. The controlled CLK switching frequency range is reduced in the singular-single peak-to-peak and produces a finite EMI radiance energy spectrum to allow the emi filter 配置 to be configured in a simpler and less expensive way, thereby reducing the pFc circuit. The total cost. The nominal operating frequency of CLK is selected such that the period of CLK is still low enough in response to its highest level of operation of input current I1N, capable of operating PFC circuit 100' in a non-continuous mode, ie, a non-zero portion of the switching cycle , Ic〇IL is one of the modes. The switching cycle of the PFC control circuit 1 () is initiated by the clock signal CLK whose operating period is much less than ~ cycle. Thus, the coil 25 has a substantially constant voltage vIN in any particular switching ring. Thus, the charging current iCHG is linearly increased by a slope approximately equal to v, N / L to reach a peak value I P E A K = T C H G * V 丨 N / L. Similarly, the slope of the 'discharge current I D s c H G is substantially equal to (V0UT-V[N)/L and its duration

Tdschg=L*Ipeak/(V〇ut-V〖n). Therefore, the total time when ICCML is not zero is as follows: 1) Tcoil=Tchg+Tdschg~L*Ipk·-- 0 ^IN OUT ~^In)

Therefore, the coil current Icoil flows as a triangular wave whose average value Ic 〇 IL CLK during a CLK period TcLK is as follows: 2) Ic 〇 [L_clk = ^. (Z^

lCLK ^(tchg*Dcycle) where Dcycle-(Tchg+Tdschg)/Tclk represents the duty cycle of the non-zero coil current in TcLK per CLK cycle "When the average coil current j COIL_CLK. follows the rectified sinusoidal shape of vIN (occurs in When Tchg*Dcycle is constant) 'Achieve a high power factor.

Since the load current IloM1 timing charge time Tchg is constant, in order to keep the product TCHG*DCYCLE constant and achieve a high power factor, the oscillator 35 changes the exchange frequency Fsw of CLK to maintain Dcycle substantially constant. The average input power during the period of the input electric house vIN is <1%> is given by the equation, 3) <p1N>=i^*(TcHG*DcYCLE), where VACRMS is the line voltage VAC Root mean square value. When the load power I: strange timing 'PFCf road (10) operation, the average input power (four) to protect! · 亘疋 * MVagrms & l for the strange ^, Μ load conditions caused by 9l803.doc -12- 1334256 4) (Tchg * DCycle)=^1^>

The intersection required for ^lACRMS to achieve the High Power # factor is also constant. From these relationships, the change frequency F s w is given by: 5) F^w=Jlh*<p^ ^〇υτ-Κ, 〇

V~acrms *T2chg V Therefore, when the switching frequency Fsw is proportional to the difference between the output voltage νουτ and the instantaneous rectified input voltage ν, the PFC circuit 1〇〇

Zen near one PFC operates. In fact, under the steady-state conditions, % is adjusted and thus remains constant, so Equation 5) can be simplified as: 6) Fsw = Ki * (K2-VIN) > T (: HG for the time. Among them, 2^%> constant, Κ2=ν〇υι^ adjust configuration adjustment= At a given <P!n>&VAC operating point, there is a power factor, and the CLK frequency Fsw is effectively modulated by Vin. Thus, Fsw has a lower value near the peak of VIN' and a higher value near zero volts. To achieve this, oscillator 35 has an input that operates near ground potential, one of which is used to The sensor 18 establishes a sense current Ιιν to sense the input voltage VlN, and the other is used to sense the output voltage v〇UT by establishing a current IOUT by a resistor. The oscillator 35 is subtracted from 1〇(10). I, N to obtain a difference current for establishing an instantaneous value of the CLK period TcLK, and thereby obtaining the switching frequency Fsw. The detailed operation of the PFC circuit 100 can be explained by referring to the timing chart of FIG. 2, which shows Input voltage vIN, coil current Ic()1L, drive during selected switching cycles (Τ4·τ〇) and (Τ9 Τ5) No. ν_Ε The waveform of the pulse signal clk, the duration of each item is in the range of about fifty microseconds and 9l803.doc -13 - 1334256 (Ding 9-Τ5)>(Τ4_Τ0). Figure 2 illustrates the two coffee cycle Or period τ, interval TO lasts to time Τ4 - period, eL*K 0' „3 from time Τ5 lasts until

Β The first car parent cycle. Although the input voltage V is taken as ^ 4 1N as the rectified sinusoidal curve, the ICLK period is still much shorter than V [N cycles. Since ^ Βα , . and ί are better than the month of the month, when VlN is displayed, it is valued in each week, but the value vIN1 of the basin in the first cycle is lower than the value ViN2 in the second cycle. /, Assume that the initial time 'just before time το' CLK~[VE is a logic low level and the transistor 29 and the blocking diode 26 are both off, thus Icoil = 0.0 amps. At the TO between τ, the s a pulse CLK is converted from a logic low level to a logic high level, and a first switching cycle is started to initiate a pulse of the drive signal VDrivE. The transistor 29 is turned on, and the coil 25 is charged with a charging current at a linearly increasing rate VIN/L25. Since the voltage across the transistor 29 is close to the command, the entire voltage vIN is effectively applied across the coil 25. Thus, the charging current ICHG increases at a rate proportional to the instantaneous value of V[N. During the interval of time το to τι, the input signal Vin has a substantially constant voltage value V [NI], so the charging current 1 (: is called linear increase until time TI, at which time it reaches a peak iPKI = VlN 丨 * Tchg /L25 0 At time T1 'vDRIVE transitions from a high logic level to a low logic level' turns off transistor 29 to allow energy stored in coil 25 to be transferred via blocking diode 26 to capacitor 27 ^ The voltage drop across the body 26 is small compared to a voltage (V〇ut-V丨N), so it can be considered that (v0UT-V1NI) is applied across the coil 25, and the iDSCHG# rate (V) 〇UT_v_)/L25 linearly decreases' until it is discharged to zero at time T3=Tl+IPK1*L25/(VOUT-ViN1). 9l803.doc 14 1334256 At time T2, the clock signal CLK is from ~ ancient The same level is reset to the low level, which does not cause the change of the drive signal Vdrive voltage level from time T3 to time T4, and Ic〇lL remains in a non-non-conducting period for this purpose is a non-continuous operation mode of the PFC circuit 100. Characteristics: At time T4, the first-switch cycle ends, and another _ may have several CLKs Change cycle. & sweat start. At time T5, the specified second cycle has a low to high CLK and vDRIVE conversion, but its input voltage VtN operates at a higher effective voltage value of V, N2 > V1N1. The high VlN2 value causes the charging current Ichg to increase linearly at a faster rate via the coil 25 and the transistor 29, and reaches a peak above the peak Ιρκι at time T6. IpK2 = ViN2*

[LOAD

When a J Ί field 丄 I is constant, Tchg = (T1 - T 〇 HT6 - T5) has a constant value. At time T6, Vdrive performs another high to low transition to deactivate transistor 29' and allow the magnetic energy stored in coil 25 to be transferred as discharge current Whg via blocking diode 26 and stored on capacitor 27. . During the interval from time T6 to time T8, the _substantially weighed voltage (V〇ut-VIN2) is applied to the coil_end, so that the τ Id Id Idschg is linearly reduced by the slope (V〇UT_ViN2)/L25 until It discharges to zero at time T8 = T (four) PK2 * L25 / (WVIN2). Since Vw~, the coil current] (4) reaches a higher peak current Ιρκ2, but at a lower rate (w~ crystal 5 puts the field Ic〇IL discharge to zero day _, the second non-conductive period starts at time, and holds , ', to the end of the _ exchange cycle, and the other - exchange cycle starts at time π 0 9I803.doc !334256 At time T7, the clock signal CLK performs a high-to-low transition, which does not drive the drive signal VDR Figure 3 is a circuit diagram showing a portion of the PFC circuit 100, including further details of the oscillator 35 and resistors 18 and 45. The oscillator 35 includes current mirrors 57 through 60, switches 62 through 65, and a timing sequence. Capacitor 68 and a comparator 69 oscillator 35 are configured as a voltage controlled oscillator that generates a clock signal CLK as a series of pulses at a nominal or center frequency, the frequency and difference (VOUT-ViN) Proportional is modulated.

The timing capacitor 68 is connected between a timing node 7 〇 and a ground potential. The container 68 is typically integrated into the same die as the other components of the PFC control circuit 1 ,, but can also be formed as an external capacitor. In one embodiment, capacitor 68 has a value of approximately - hundred picofarads. Capacitor (10) is charged and discharged in sequence by currents iIM2, iIM3, IqM2 & Iqm3 to form a triangular or ramp voltage at node 70. Cleavage = 2 to 65 is implemented using a transistor that is activated or turned on by the clock signal clk or the complementary clock signal CX, respectively. Because &, switch and 65 are actuated or closed when CLK is logic high, switch (4)_ is logic high and CLK is logic low. Comparator 69 is configured as a hysteresis comparator that compares a voltage established at the timing node with a reference dust to produce a clock signal comparison at its output (4) having a complementary clock signal clk and a pole output , or ^ can be obtained by inverting CLK by a single inverse c 1 . When comparator 69 is generated with, for example, _

The logic is still in the CLK temple, an internal hysteresis circuit reduces the reference value by π. After printing, the value is REF HYST. Therefore, CLK remains at a logic high level until ^ is discharged to - low. At the level of (Vref_Vhyst), clk is converted to a logic low level. The effect of hysteresis is that v- is generated as a two-dimensional wave between ν_(ν_ ν_τ), as shown in Figure 2. In-supply voltage

In a particular embodiment where Vcc = 12.0 volts, the value of VREF is approximately three volts, and the value of vHYST is approximately - volts due to & voltage difference (v__m is approximately two volts. Current mirrors 57 through 58 include scaling A transistor that produces a mirror reflection current IiMi, ", and [10) proportional to or in multiples of the wheel sensing current I: N. Similarly, the current mirrors 59 to 60 include a scaled transistor, which produces and outputs The sense current Ι〇υτ is proportional or multiplied by the mirror reflection currents 1〇(4), ι〇... and Ι〇Μ3. The oscillating state 3 5 operates as follows. Assume initially that the clock signal clk is at a logic low level. Thus switches 63 and 64 are closed, switches 62 and 65 are open, and VRAMP is increased and its value is less than, as shown in Figure 2. At time Dc, CLK transitions to a logic high level, which closes switches 62 and 65. The switches 63 to 64 are opened to discharge the capacitor 68 with the current I 〇 M3 while being charged by the current. The current mirrors 57 to 60 are ratiometric, so I 〇 M3 is higher than I [M2, and thus the current 〇 4 (4) 〃, the algebra of Iim 2 And causing - the net difference current (ΙΟΜ: 3-Ι1Μ2), which causes the capacitor to write 68 to discharge The small Vramp2 level. At the 7th interval, the 'vRAMp reaches the level of (vREF-VHYST), at which point clk switches to a logic low level, which closes the switches 63 to 64 and turns off the switch "with 65. Then the capacitor 68 is charged with current I 〇 M2, and is discharged with current I [M3. Electric "_L I! M: 3 and I0M2 have been reduced so that hM: j <]; 〇 M2, resulting in a valid difference of electricity 9l803. Doc 17 1334256 Stream (i(10)chuan(10)) charges capacitor 68. When capacitor 68 is charged to VrAMP VREFa^, CLK performs a low-to-high transition to begin another cycle. V, or current mirror 57 to 60 scaling or mirror The reflection ratio is such that the capacitance 1 ^ (I〇M2'Ii^)=K3*(Vout-Vin) ^ (I〇M3-IIM2), K:4 (V0UT-VIN) are respectively charged and discharged, where && Both are constants. It can be seen that the switching frequency Fsw has the form shown in Equation 6) above, resulting in a power factor close to one. Figure # illustrates a circuit diagram of a portion of the PFC circuit 100, which includes an alternative "body" step-by-step details of the oscillator 35 and the resistor 18. The oscillator 35 includes a current source δ() to 81, current Mirrors 57 to 58' switch 62 to 65, a timing capacitor 68 and a comparator 69. When CZX is high and switch 64 is closed, current source 8 is supplied from supply voltage ye. Supply node 70 is supplied with charging reference current u. The current source 81 supplies a scaling or mirror reflection discharge reference current law2 to the node 70 when the coffee is high and the switch is "closed." The scaling or mirror reflection ratio of the current mirrors 57 to 58 and the current sources 8 〇 to 81 is selected such that the capacitor 68 has a difference current when Μ is high (1 yang fi-i 丨 M3) = k5 * (vref - v 丨Ν) Charging, where κ5 is a constant and is discharged with a j difference current (IREF2_I1M2)=K7*(VREF-VIN), where 7 is a constant. Obviously, the false SVREF is representative of a desired value of V〇UT, which determines the switching frequency Fsw according to the above equation 6), thereby achieving - close to a factor. *, Figure 5 is a schematic diagram illustrating further details of the oscillator in another alternative embodiment. This embodiment has an operation and structure similar to that of the embodiment shown in FIG. 4, but the comparator 69 is non-hysteresis and has a limit of 9l803.doc *18· when there is a limit power, 甘1, The error is generated by a circuit comprising resistors 83 to 84 and 88 main (10), a capacitor 85, a square ray, a 100,000 circuit or multiplier 86, a dividing circuit 87 and a switch 90. As above, for Il 〇 I I 及 及 TCH TCH TCH TCH TCH TCH TCH TCH TCH TCH TCH TCH TCH TCH TCH TCH CLK CLK CLK CLK CLK TCH TCH TCH CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK However, as the equation), the magnitude of V [N is higher, the change of F, | Fsw is larger especially at the peak value of the peak current 1 - C 〇 [L current flowing. This embodiment provides a circuit that does not reduce the overall frequency change or jitter as follows. Resistor 83 to 84 is used as a voltage divider for splitting the turn-in voltage Vin, and the combiner 85 cooperates with the resistors 83 to 84 to generate a low-pass filter which produces, the physics is zero. Or at least less than the average voltage of the rectified sinusoidal waveform of VIN <ViNl>. In one embodiment, resistors 83 through 84 and capacitor 85 are selected to set the low pass angle to about ten hertz such that Vr is substantially the DC voltage. Since s Xuan low pass chopping ' < V 丨 N1 > represents the average value of VIN. Multiplier 86 is a standard analog multiplier circuit that calculates the average voltage

The square of VlN, to produce a square voltage Vsq = K8 * < Vin1 > 2, where κ8 is a constant. The dividing circuit 87 divides a reference voltage VREF by VSQ to generate a voltage vum = VDiV = Vref / (K8 * < Vini > 2) which is coupled via a resistor 88 to be used in the comparator when the clock signal CLK is low. 69 One input setting - Vramp upper limit. When CLK is high, switch 90 is closed and VDIv is the voltage divided by resistors 88 through 89 ' to establish a lower limit of vRAMp at VUivi = Vref / (k8 * < v (4) > '-) * r89 / (R88 + R89), where r88 and 89 are the resistors of resistors 88 and 89, respectively. 9i803.doc -19- 1334256 a Therefore, the switching frequency Fsw=k9*<Vin>NVref_Vin), where κ9 is a #number option allows 4:1 ft 3 5 to limit the switching frequency change for EMI filtering. Figure 6 is a schematic illustration of a pFc circuit 1 in an alternative embodiment. This embodiment does not require the resistor i8 and its ?; the power consumption Pri8 = Ii^Ri8, which is 'resistance of the resistor 18. Thus, this particular embodiment is suitable for applications requiring low standby power and power factors less than ideal. The embodiment of Figure 6 modulates the switching frequency Fsw with the instantaneous value of the coil current Ic 〇 il instead of the input voltage vIN. On average, ICCHL^ has a sinusoidal waveform in phase with ~ due to the correction of the factor of the pFc circuit. Sensing is sensed in its return path through resistor 72 to diode bridge 2, which establishes a current sense voltage Vcs across resistor 72 at a node 39 to modulate Fsw. In a particular embodiment, the resistance of resistor 72 is approximately 〇 ohms. a. When the amplitude of iC0IL is one ampere, the value of Vcs is approximately _ 〇 1 volt. Alternatively, other techniques such as a current transformer instead of current sense resistor 72 can be used to measure IC0IL. Use coil current Ic〇il instead of input voltage ~ to change the switching frequency Fsw is suitable for continuous mode or discontinuous mode pFc circuit, or suitable - combine power factor correction with a downstream voltage regulator or converter in a single stage The method of the specific embodiment. The power factor of this particular embodiment can be considered to be lower than the specific embodiment previously described because the instantaneous value of iC0IL is only approximate to the rectified sinusoidal waveform of Vin. In this case, the power consumption and manufacturing cost of this form are low, so it is suitable for applications that do not require the highest power factor. In a specific embodiment, the power factor can be improved by connecting a capacitor across resistor 72. Selecting the power to dissipate high frequency components, such as components above the VIN frequency, to produce at node 39 - more ideally approximates the waveform of a rectified sine wave. Figure 7 illustrates further details of the current (four) of the PFC circuit (10) in a particular embodiment of Figure 6 including a resistor 82, a current source 78, and a surge (four). The illustrated transistors 76 through 77 are formed as a matched or scaled pair of NPN bipolar transistors whose emitter regions are scaled by a predetermined ratio. Current source 78 supplies a current Ir via % anode 77 to establish a base-emitter voltage biasing the base electrode of transistor 76 to a fixed potential. The resistor 82 is typically formed as an external resistor to avoid the detrimental effects caused by the negative potential of the current sense voltage Vcs when flowing. If transistors 76 and 77 have the same ratio of emitter regions, their respective emitters will operate at substantially equal potentials, so the current Im 々 w is proportional, since vcs = -r72 *icoil ; isense is substantially equal to Imi (ignoring 57 base current) and vcs+(R82*Isense) is zero, where the resistor is the resistor and is remotely selected to provide the desired sampling current r(10) to the via transistor 76. Then Im-I^^Icoa/R82 4S£nse is mirror-reflected by the current mirror "to" to provide differential charging and discharging currents (Iref|.w and (Iref2_Imi) to the timing node 70 as described above. In summary, this The invention provides a PFC circuit that operates in a discontinuous mode with a fixed switching pulse. This discontinuous mode of operation allows the pFC circuit to block diode fabrication at a low cost, thereby reducing system cost. A pulse width modulator The transition edge of a clock signal is synchronized, thereby generating a pulse to establish a coil current-charge period. The coil current is then discharged in a discharge 9l803.doc -21 - 丄川4256' to create a pFc output from an input signal ::Generate the clock signal' so that its clock period is longer than the charge and discharge cycles: thus ensuring discontinuous mode operation. The oscillator has - for sensing: the input of one of the input signals of the PFC circuit for modification in a controlled manner Time q, (9) keeps the product of the charge cycle and the coil current duty cycle maintained. Thus the 'PFC circuit exchanges the coil current in the predetermined frequency range, so as to use a low cost EMI. The filter reduces electromagnetic interference. [Simplified illustration] & Figure 1 is a schematic diagram of a power factor correction (PFC) circuit; 0 Figure 2 is a timing diagram illustrating the waveform of the pFC circuit; Figure 3 is a PFC circuit including an oscillator Figure 4 is a schematic diagram of an oscillator in a first alternative embodiment; Figure 5 is a schematic diagram of an oscillator in a second alternative embodiment; Figure 6 is an alternative embodiment of a pFC circuit Circuit diagram; and Figure 7 is a circuit diagram of a PFC circuit in another alternative embodiment. [Main component symbol description] 10 '100 power factor correction circuit 15 filter 16, 17, 45 18 19 20 25 26 resistor resistor Capacitor diode bridge inductor blocking diode 9l803.doc -22- 1334256 CLK clock signal CLK complementary clock signal Dcycle load cycle FSw switching frequency IcHG charging current Ic-HG charging current component Ic〇IL coil current Ic〇IL_CLK Average coil current Idschg Discharge current IlMI IlM2, IlM3, I[M4 Mirror reflection current IlN Input current Iload Load current I〇Ml I〇M2, I 〇M3 Mirror reflection current IpEAK Peak current TO, ΊΠ, T2, T3, T4 Time T5, T6, T7, T8, T9 Time TcHG Charging period TcLK Clock period Tdschg Discharge period VAC Sinusoidal AC voltage Vcc Supply voltage 9I803.doc -24 - 1334256

Vcs current sense voltage V〇RI VE drive signal Vfb feedback signal Vhyst hysteresis voltage vIN input voltage Vlim limit voltage V〇UT output voltage V ramp ramp voltage Vref reference voltage 9l803.doc

Claims (1)

133425b Patent Application No. 093110996 ^- One Chinese Patent Application Scope (99 years 6^) Years and Months Amendment 10, Patent Application Range: ^ ^— 丄. A power factor correction circuit, including: a pulse width modulation The transformer, the response - the clock signal is used during a charging cycle - the power is due to the sin = loop current, to correct the - node power to establish the loop current to discharge during a discharge cycle to establish a round a voltage; and a charge it' has a round of pulse signal for generating a clock period longer than the sum of the discharge periods, and - the first input is used to sense the power factor to repair the clock cycle, 1... (4) "Transfer 4 to modify the electrical cycle and ... a load current is constant, the charge current - load (four) B :: always define the line 2. Make the load ^ modify the clock cycle to clothing /, The product of the charging cycle is kept constant. For example, the Kn Μ positive circuit of the power factor correction circuit of the application scope of the item [the operation of the power] operates as a rectified sine wave voltage. The power factor of the item is modified by the #哭忐&" circuit', wherein the oscillation is formed as a voltage controlled oscillator to include: a ramp generator that operates in response to the clock signal and the second node is used to Capacitor #广', during a charging cycle, from a first soil to the mouth ^ seated in the slope electricity; > _ 曰 to - second reference level:: comparator, which is used to compare the slope The electric house has an output that is combined with the output of the vibrator; 91803-990615.doc 1334256, ___1 [Jvta and an electric retractor having a -first input for receiving - an input current representing the input signal of the key , a # @ & represents the input from (4) provides - the first mirror reflection electric '丨L δ χ electric current minus to modify the clock cycle. 4. As claimed in the third paragraph of the patent a packet road, wherein the current brother k provides a first mirror reflection current for the first shovel ramp generator to include: ^ first-point charging and the first electrical current 该 coupled to the second node "for supplying the charge 2: two current sources, which are used to make the second node - Discharge = Electricity, the second mirror reflected current is subtracted from the discharge current. 5. For example, the power factor correction circuit of the first item of the patent of the month of the month, wherein the pulse width modulator has a light feedback to the input voltage = the voltage to respond to the power due to the m measurement of the output φ ... η load The current period of the %•pulse is adjusted by the current. For example, apply for a patent! The power factor correction circuit of the item has a voltage higher than a peak voltage of the input signal. The power factor correction circuit signal of item 1 of the patent application range is representative of the coil current. 8. The power factor correction circuit of claim 7 of the patent scope includes: a sense resistor 2 that is coupled to the first input of the oscillator:: The coil current is sent to establish a sense voltage. 9. : Power factor correction circuit operating in - discontinuous mode, package 6. 7. 91803-990615.doc where the output is the input of the further package 1334256 months, the correction replacement page "^ • degree adjustment a transformer having an input for receiving a pulse width = a pulse of a load current of the power factor correction circuit for charging a coil current that has been discharged to establish an output cladding; and an oscillator having a An output for generating a pulse having the selected frequency to discharge the coil current to zero and having an input for sensing an input signal of the power factor correction circuit to modify the frequency, wherein the vibrator is formed The voltage-controlled vibrator includes: a-ramp generator that operates in response to the clock signal and has a second node for supplying a charging current to a capacitor to generate two in the charging - the first reference level is increased to - the second reference level of the ramp voltage; - the comparator ' is used to compare the ramp with the first and the second / test voltage and has a An output coupled to the output of the oscillator and a current mirror having a first-input-receiving-representing a wheel-in current representing the input signal to provide a -first-mirror reflected current to the second node This charging current is subtracted to modify the clock cycle. 1. The power factor correction circuit of claim 9, wherein the output voltage is established at a node, and the pulses have a trailing edge to discharge the buffer current to a capacitance of the node to establish the The output voltage. η. The power factor correction circuit of claim 4, wherein the pulse widths are substantially equal when the read load current is constant. 12.------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ One of the signals has a clock period longer than one of the charge period and a discharge period of the coil current; discharging the coil current to zero during the discharge period to establish an output voltage; and sensing the input of the power factor correction circuit Signaling to modify the clock cycle, wherein one of the output voltages is constant, the charge cycle and the discharge cycle are summed during the clock cycle to define a duty cycle of the coil current 'and the input signal modifies the The clock cycle is such that the product of the load cycle and the charge cycle remains constant. 13. The method of claim 12, further comprising: charging a capacitor with a charging current to generate a ramp voltage; comparing the ramp voltage to a first reference voltage to generate the clock signal; and mirror reflection An input current representative of the input signal to provide a first mirror reflected current to the capacitor to modify the clock period. 14. The method of claim 13, wherein the mirror reflection comprises subtracting the first mirror reflection current from the charging current to modify the clock period. 15. The method of claim 14, wherein the mirror reflection comprises actuating the first mirror reflection current in response to the first transition of the clock k. The method of claim 13, wherein the charging comprises increasing the ramp voltage with the charging current, and the comparing comprises generating a first transition of the clock signal. 17. The method of claim 13, further comprising: discharging the capacitor with a discharge current to reduce the ramp voltage; and 91803-9906l5.doc -4- The second reference voltage is used to generate a second conversion of one of the clock signals. The method of claim 16, further comprising mirroring the wheeling current to provide - a second mirror reflecting current for subtracting from the discharging current to modify the clock period. 19. A power factor correction circuit comprising: a pulse width modulator operative in response to a clock signal for synchronizing a self-destruction voltage-coil current of a coil current, wherein the coil current is discharged to establish An output voltage; the oscillator having an output for generating a frequency of the clock signal and an input for sensing the coil current to modify the frequency; and a light port to the input of the oscillator current path# It is used to transmit the coil current to establish a sensing signal. The power factor correction circuit of claim 19, wherein the clock signal is subjected to a first-to-conversion from a -th logic level to a -: logic level, and from the second logic level The second transition of the first logic level, and the pulse width modulator should wait for the first transition to generate the pulses. 4 The power factor correction circuit of claim 19, wherein the pulses have a constant pulse width. A power factor correction circuit as disclosed in claim 19, wherein the current path in the basin includes a resistor that establishes the sensing signal at both ends thereof. 91803-9906I5.doc -5- 1334256 Patent Application No. 093110996 Chinese Manual Replacement Page (June 99) VII. Designation of Representative Representatives: (1) The representative representative of the case is: (1). (2) A brief description of the component symbols of this representative diagram: 10, 100 power factor correction circuit 15 waver 16, 17, 45 resistor 19 capacitor 20 diode bridge 25 inductor/coil 26 blocking diode 27 capacitor 28 load 29 transistor 30 node 31 pulse width modulator 32 node 35 oscillator 39 > 36 input CLK clock signal IcHG charging current IcOIL coil current Idschg discharge current IlN input current 91803-990615.