CN1663101A - Power factor calibrating circuit having variable switching frequency - Google Patents
Power factor calibrating circuit having variable switching frequency Download PDFInfo
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- CN1663101A CN1663101A CN038142376A CN03814237A CN1663101A CN 1663101 A CN1663101 A CN 1663101A CN 038142376 A CN038142376 A CN 038142376A CN 03814237 A CN03814237 A CN 03814237A CN 1663101 A CN1663101 A CN 1663101A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
A power factor correction (PFC) circuit includes a pulse width modulator operating in response to a clock signal (CLK) for switching a coil current (ICOIL) over a charging period (TCHG) to correct a power factor at a node. The coil current discharges over a discharging period (TDSCHG) to develop an output voltage (VOUT) at an output. An oscillator generates the clock signal to have a clock period (TCLK) longer than the sum of the charging and discharging periods, thereby operating in a discontinuous mode, and has an input for sensing the input signal to modify the clock period.
Description
Technical field
The present invention relates generally to integrated circuit, and relates in particular to integrated power factor correction circuits.
Background technology
Illuminating equipment and other electrical systems have low power factor, because they only extract electric current near the crest voltage of alternating current (AC) power supply, rather than carry out in whole alternating cycles.Specify for all users in distribution network for being in certain, voltage peak occurs simultaneously, thereby causes a kind of assembly effect, makes grid generator will carry high electric current near voltage peak, and other the time electric current very little even do not have an electric current.This load can cause the harmonic distortion of supply voltage, the high neutral line current in the three phase power distribution networks, and the equipment work that also may cause utilizing this power supply to carry out work is unusual.For fear of this line distortion, local cause company just has to strengthen their distribution network, and this just needs fund input of writing.
Some governments attempt to alleviate this problem by requiring system manufacturer to add power factor calibration (PFC) in some electrical system.For example, Ou Zhou IEC 1000-3-2 code requirement adds PFC in other electric equipment of illuminator and some.PFC is realized by pfc circuit usually, this circuit is with the source current of the coil of flowing through far above the frequency switching of supply frequency, then coil current is discharged on the electric capacity by a blocking diode, thereby form a direct current (DC) supply power voltage, this direct voltage is carried out to be equipment or system's power supply with it after the rectification.The switch of electric current is controlled, and this control makes the mean value of coil current be directly proportional with AC power supplies voltage, that is, and and homophase and be sinusoidal wave basically.This method can realize .995 or more power factor, or even desirable 1.0.
In the existing pfc circuit quite a few worked under the pattern of conducting continuously, and in this pattern, new switch periods had just begun before the coil current in previous cycle discharges into zero.The PFC system of continuous conduction mode needs high performance coil and has the blocking diode of instantaneous recovery time, so that keep power delivery efficiently.Yet high-performance coil and blocking diode cost are very high, and this has just improved the manufacturing cost of continuous conduction mode PFC system.In addition, these systems are the switching frequency work to fix usually, thereby produce high peak energy, and the filter of a costliness of needs is restrained the electromagnetic interference (EMI) of generation like this.
Other PFC systems are with critical or boundary conduction mode work, and in this pattern, new switch periods begins when coil current arrives zero just.The critical conduction mode circuit can provide High Power Factor, but they within a very wide switching frequency scope, work, thereby need complicated and expensive filter restrain EMI.Simultaneously, under low power condition,, switching frequency reduced attainable power factor to such an extent as to being so high propagation delay by pfc circuit.
Other pfc circuits are worked under discontinuous pattern, in this pattern, all allow coil current to reduce to zero and continue for some time in each switch periods.These systems can be provided to by the fixed frequency switch, thereby dwindle the electromagnetic interface filter of EMI frequency spectrum and permission use arrowband.Yet similar with the continuous conduction mode pfc circuit, these systems can produce the peak value emittance of single-frequency, promptly use narrow band filter also to be difficult to restrain this energy.
Therefore need a kind of pfc circuit and method, it can be in controlled scope switch, thereby reduce the cost of filtering EMI in the electrical system.
Description of drawings
Fig. 1 shows a kind of principle schematic of power factor calibration (PFC) circuit;
Fig. 2 shows a width of cloth sequential chart, and it has showed the work wave of pfc circuit;
Fig. 3 shows the principle schematic of a pfc circuit part that contains oscillator;
Fig. 4 shows the principle schematic of the oscillator in first alternative;
Fig. 5 shows the principle schematic of the oscillator in second alternative;
Fig. 6 shows the circuit diagram of the pfc circuit in the alternative; And
Fig. 7 shows the circuit diagram of the pfc circuit in the another kind of alternative.
Embodiment
In the accompanying drawings, the element that has a same reference number has similar function.
Fig. 1 shows a kind of principle schematic of power factor calibration (PFC) circuit 100, and this circuit is used to calibrate the power factor of an alternating current (AC) power supply, and described power supply is worked with sinusoidal AC voltage VAC, provides a load current I to a load 28 simultaneously
LOAD Pfc circuit 100 is subjected to the control of PFC control circuit 10, and this circuit is with V
CC=12.0 volts supply power voltage is operated under the discontinuous pattern, contains an electromagnetic interference (EMI) filter 15, capacitor 19, diode bridge 20, resistance 16-18 and 45, inductance or coil 25, a blocking diode 26 and an output capacitance 27 in the pfc circuit 100.Pfc circuit 100 produces a direct current (DC) output voltage V on output node 30
OUT
Put it briefly, pfc circuit 100 comes for AC power supplies provides a High Power Factor by the power factor on the calibration input node 32, and described input node is operated in input voltage V
INOn, this voltage obtains by rectification VAC.In fact, pfc circuit 100 utilizes feedback to produce a resistive load in the negative terminal of node 32 and electric bridge 20, and in the embodiment shown in fig. 1, the negative terminal of electric bridge 20 is operated on the ground potential.Therefore, the mean value and the AC power supplies of the electric current of the node 32 of flowing through are all with V
INHomophase.
Specifically, pfc circuit 100 has played the effect of a step switch adjuster, and wherein resistance 16-17 sets up V as voltage divider
OUTValue, this magnitude of voltage is lifted on the level that is higher than the VAC crest voltage.In one embodiment, the root mean square of VAC (RMS) value is about 220 volts, and frequency is about 50 hertz, the output voltage V that pfc circuit 100 produces
OUTValue be about 400 volt DC voltages.In some region, the RMS value of VAC is about 110 volts, and frequency is about 60 hertz, and then pfc circuit 100 produces and is about 230 volts direct voltage V
OUTPfc circuit 100 size of component, puncture voltage or the like can suitably be selected, and make V
OUTThe system that is arranged on about 400 volts of dc voltages can work under any in the world AC power.This type systematic is called as universal mains systems.In most of areas, the typical range of VAC is all between positive and negative 20 percent.
In an alternative, pfc circuit 100 is configured to power factor calibration function and voltage regulator are combined in the single-level circuit, and this single-level circuit produces a V who is lower than peak value VAC voltage
OUTFor example, resistance 16-17 can so select, and makes pfc circuit 100 that a V such as 5 volts of voltages is provided
OUT
Coil current I
COILComprise a charging current component I
CHGWith a discharging current component I
DSCHGThe time of transistor 29 conductings is called as charge cycle T
CHG, charging current I during this period
CHGFlowing through coil 25 and transistor 29, thus in coil 25, store magnetic energy.If load current I
LOADBe steady state value, so T
CHGAt whole V
INAlso steady state value in cycle.When transistor 29 turn-offed, the magnetic energy of storage was with discharging current I
DSCHGForm flows into electric capacity 27 from coil 25 through blocking diode 26, and forms output voltage V on node 30
OUTDischarging current I
DSCHGThe time of circulation is called as discharge cycle T
DSCHG, this time cycle can be along with charging current I
CHGPeak value and V
INVoltage and change.
The CLK switching frequency scope that is controlled has reduced the peak E MI radiation on any single frequency, produced the limited frequency spectrum of EMI emittance simultaneously, thereby make electromagnetic interface filter 15 can be set to complexity and all lower form of cost, so just reduced the whole cost of pfc circuit 100.The nominal operation frequency of CLK may be selected such a case, when its corresponding to input current I
INWhen being operated in highest frequency value, the cycle of CLK is still low as to be enough to allow pfc circuit 100 be worked under discontinuous mode, that is to say, and under this pattern, I
COILA non-zero a switch periods is zero in the period.
The switch periods of PFC control circuit 10 is started by clock signal clk, and the work period of this clock signal is much smaller than V
INCycle, therefore in the switch periods of any specific, a substantially invariable voltage V appears at coil 25 two ends
INThereby, charging current I
CHGTo be approximately equal to V
INThe slope linear increment of/L, and reach a peak I
PEAK=T
CHG* V
IN/ L.Similarly, discharging current I
DSCHGSlope be substantially equal to (V
OUT-V
IN)/L, and its duration T
DSCHG=L*I
PEAK/ (V
OUT-V
IN).Like this, I
COILBe providing total time of nonzero value by following formula:
Coil current I
COILForm with triangular wave flows through, and it is at a clk cycle T
CLKInterior mean value I
COIL_CLKProvide by following formula:
D wherein
CYCLE=(T
CHG+ T
DSCHG)/T
CLK, it represents each clk cycle T
CLKThe duty factor of interior non-zero coil current.As average line loop current I
COIL_CLKFollow V
INRectified sinusoidal the time, just can realize high power factor, this situation can be at T
CHG* D
CYCLEOccur when being set as steady state value.
Because load current I
LOADCharging interval T during for steady state value
CHGAlso be steady state value, in order to keep T
CHG* D
CYCLEProduct constant and realize a High Power Factor, oscillator 35 can change the switching frequency F of CLK
SW, to keep D
CYCLESubstantially constant.Input voltage V
INMean Input Power<P in one-period
INBy equation 3) provide:
V wherein
ACRMSIt is the root-mean-square value of line voltage distribution VAC.As load current I
LOADWhen constant, pfc circuit 100 is operated in Mean Input Power<P
INUnder the constant condition.Because V
ACRMSAll constant with L, so constant load conditions causes product:
Also constant.According to these relational expressions, can release the switching frequency F that will realize that High Power Factor is required
SWProvide by following formula:
As a result, if switching frequency F
SWBe changed to and output voltage V
OUTWith instantaneous rectification input voltage V
INBetween difference be directly proportional, then pfc circuit 100 can be operated in PFC near under 1 the situation.In fact, under described limit, V
OUTRegulated, thereby be constant, so equation 5) can be reduced to:
6)F
SW=K
1*(K
2-V
IN)
K wherein
1Be a constant, K
2=V
OUT, and adjusting device is adjusted T
CHG, make at given<P
INAnd the VAC working point on,
In order to realize High Power Factor, CLK frequency F
SWBy V
INModulation effectively, thus F made
SWAt V
INHave lower value near the peak value, and at V
INHas higher value in the time of near zero volt.In order to realize this point, oscillator 35 has several and is operated near the input of ground potential, and one according to the induced current I that forms through resistance 18
INDetect input voltage V
IN, another is then according to the electric current I that forms through resistance 45
OUTDetect output voltage V
OUTOscillator 35 is from I
OUTIn deduct I
IN, obtaining a difference current, this electric current is used to set up clk cycle T
CLKInstantaneous value, and switching frequency F
SW
The detailed operation process of pfc circuit 100 can be referring to the sequential schematic diagram among Fig. 2, and this figure has showed input voltage V
IN, coil current I
COIL, drive signal V
DRIVEAnd clock signal clk is in selected switch periods (T4-T0) and the waveform (T9-T5), and the duration of each waveform is in about 50 microsecond scopes, and (T9-T5)>(T4-T0).Fig. 2 shows two CLK circulations or period T
CLK, first cycle from moment T0 moves to T4 constantly, and second period (also being long one-period) moves to T9 constantly from moment T5.Although input voltage V
INMeeting is with the variation of rectified sine wave, but clk cycle far is shorter than V
INCycle.Therefore, in order to describe the present invention, V better
INIn each cycle, be shown as steady state value, but its value V in first cycle
IN1Be lower than the value V in the second period
IN2
Suppose, initial-just before moment T0-CLK and V
DRIVEAll be logic low, and transistor 29 and blocking diode 26 all turn-off, thereby I is arranged
COIL=0.0 ampere.
At moment T0, along with clock signal clk is logic high and sends a drive signal V from the logic low saltus step
DRIVEPulse, first switch periods has just begun.Transistor 29 conductings are to charge charging current I to coil 25
CHGWith V
IN/ L
25Linear the increasing of speed because the voltage at transistor 29 two ends is near zero, therefore whole voltage V
INIn fact all be applied in coil 25 two ends.Thereby, charging current I
CHGTo be proportional to V
INThe speed of instantaneous value increases progressively.
During from moment T0 to T1, input signal V
INMagnitude of voltage V with constant
IN1Thereby, charging current I
CHGLinear increment, it reaches peak I up to moment T1
PK1=V
IN1* T
CHG/ L
25
At moment T1, V
DRIVEFrom the logic high saltus step is logic low, thereby has turn-offed transistor 29, so that allow the energy that is stored in the coil 25 be transferred to electric capacity 27 by blocking diode 26.Voltage comparison with voltage (the V that descends at blocking diode 26 two ends
OUT-V
IN) very little, therefore can think (V
OUT-V
IN) be applied in coil 25 two ends, and I
DSCHGWith speed (V
OUT-V
IN1)/L
25Linear decline of speed, up to it at moment T3=T1+I
PK1* L
25/ (V
OUT-V
IN1) be discharged to zero.
At moment T2, clock signal clk is reset from high level and is low level, and this can not cause drive signal V
DRIVEChange in voltage.
From moment T3 to moment T4, I
COILRemain 01 non-conduction periods, the non-conduction period of this section is the characteristic of the discontinuous conduction mode of pfc circuit 100.
At moment T4, first switch periods finishes, and another switch periods begins.Also may follow some CLK switch periods subsequently.
At moment T5, the second round of appointment, CLK and V simultaneously
DRIVEUprise from low, but input voltage V
INBe operated in higher effective magnitude of voltage V
IN2>V
IN1Higher VIN2 value causes charging current ICHG with the faster rate linear increment, and flowing through coil 25 and transistor 29, reaches peak I up to it at moment T6
PK2=V
IN2* T
CHG/ L
25, this peak value is higher than peak I
PK1Note T
CHG=(T1-T0)=(T6-T5), work as I
LOADWhen constant, this charging interval also has fixed value.
At moment T6, V
DRIVECarry out again saltus step from high to low, thereby turn-off transistor 29, and allow and be stored in magnetic energy in the coil 25 with discharging current I
DSCHGForm flow through blocking diode 26 so that be stored on the electric capacity 27.During from moment T6 to moment T8, the voltage (V of a constant
OUT-V
IN2) be applied in coil 25 two ends, thus I
DSCHWith slope (V
OUT-V
IN2)/L
25Linear decline, up to it at moment T8=T6+I
PK2* L
25/ (V
OUT-V
IN2) be discharged to zero.Because V
IN2>V
IN1, so coil current I
COILCan reach a higher peak current I
PK2, but with lower speed (V
OUT-V
IN2)/L
25Discharge.Second not turn-on cycle at moment T8-I just
COILWhen being discharged to zero-beginning, and last till that always second switch end cycle, another switch periods are till the moment, T9 began.
At moment T7, clock signal clk carries out saltus step from high to low, and this can not influence drive signal V
DRIVELevel.
Circuit theory diagrams shown in Figure 3 have been showed the part of pfc circuit 100, comprising the more details of oscillator 35, and resistance 18 and 45.Oscillator 35 comprises current mirror 57-60, switch 62-65, a timing capacitor 68 and a comparator 69.Oscillator 35 is set to a voltage controlled oscillator, and it produces the clock signal clk of a series of impulse forms, and these pulses produce by a nominal or centre frequency, and this frequency is modulated to and difference (V
OUT-V
IN) be directly proportional.
Switch 62-65 realizes that with transistor they are enabled or conducting by clock signal clk or complementary clock signal CLK respectively, as shown in the figure.Therefore, switch 62 and 65 is enabled during for logic high or closed at CLK, and switch 63 and 64 are logic high and CLK closure when being logic low at CLK.
Current mirror 57-58 comprises proportional transistor, and they produce image current I
IM1, I
IM2, I
IM3And I
IM4, these electric currents and input induced current I
INBe directly proportional or its integral multiple.Similarly, current mirror 59-60 also comprises proportional transistor, and they produce image current I
OM1, I
OM2And I
OM3, these electric currents and output induced current I
OUTBe directly proportional or its integral multiple.
The course of work of oscillator 35 is as follows.Suppose that initial clock signal clk is a logic low, so switch 63 and 64 closures, switch 62 and 65 is opened V
RAMPValue less than V
REFAnd increase, as shown in Figure 2.At moment T0, CLK jumps to logic high, so closed switch 62 and 65 and open switch 63-64, thereby with electric current I
OM3To electric capacity 68 discharges, simultaneously with electric current I
IM2Charging.The ratio of current mirror 57-60 makes I
OM3Greater than I
IM2Thereby, electric current I
OM3And I
IM2Algebraical sum cause a net difference current (I
OM3-I
IM2), this electric current difference is to electric capacity 68 discharges, thus reduction V
RAMPLevel.
At moment T2, V
RAMPReach level (V
REF-V
HYST), this moment, the CLK saltus step was a logic low, this meeting Closing Switch 63-64 also opens switch 62 and 65.Electric capacity 68 is then by electric current I
OM2Charging is simultaneously by electric current I
IM3Discharge.Electric current I
IM3And I
OM2Be conditioned and make I
IM3<I
OM2, like this will be with an effective difference electric current (I
OM2-I
IM3) to electric capacity 68 chargings.When electric capacity 68 is charged to V
RAMP>V
REFThe time, CLK is saltus step from low to high, thereby begins another cycle.
The mirror image scaling of current mirror 57-60 further is chosen for, and makes electric capacity 68 be recharged and the electric current that discharges is respectively (I
OM2-I
IM3)=K
3* (V
OUT-V
IN) and (I
OM3-I
IM2)=K
4* (V
OUT-V
IN), K wherein
3And K
4Be constant.Be not difficult to find switching frequency F
SWHave above equation 6) shown in form, so can realize approaching 1 power factor.
Circuit theory diagrams shown in Figure 4 have been showed the part of pfc circuit 100, comprising the more details and the resistance 18 of the oscillator 35 in the alternative.Oscillator 35 comprises current source 80-81, current mirror 57-58, switch 62-65, timing capacitor 68 and comparator 69.
When CLK was high level and switch 64 closures, current source 80 provided one from supply voltage V
CCCharging reference current I to node 70
REF1, and when CLK was high level and switch 65 closures, current source 81 provided the discharge reference current I of a proportional convergent-divergent or mirror image to node 70
REF2The convergent-divergent of current mirror 57-58 and current source 80-81 or mirror image ratio are chosen for, and make when CLK is high level, and electric capacity 68 is by a difference current (I
REF1-I
IM3)=K
5* (V
REF-V
IN) charging, and by a difference current (I
REF2-I
IM2)=K
7* (V
REF-V
IN) discharge, wherein K
5And K
7Be constant.Clearly, these equations have been set up corresponding to equation 6 above) switching frequency F
SWThereby, can realize approaching 1 power factor, suppose V herein
REFRepresented V
OUTIdeal value.
Principle schematic shown in Figure 5 has been showed the more details of the oscillator 35 in the another kind of alternative.This embodiment has the similar course of work and structure to the embodiment shown in Fig. 4, but comparator 69 wherein is non-retarded type, and V
RAMPSwitch restriction by a deboost V
LIMSet up, the circuit that produces this voltage comprises resistance 83-84 and 88-89, electric capacity 85, squaring circuit or multiplier 86, a division circuit 87 and a switch 90.
As implied above, for constant I
LOADAnd T
CHGIf, CLK frequency F
SWWith (V
OUT-V
IN) be directly proportional, just can realize High Power Factor.Yet, as equation 6) as shown in, if V
INHas high amplitude, then F
SWHave bigger variation, particularly at peak current I
COILThe voltage peak place of flowing through.This embodiment provides a kind of circuit, and it can reduce whole frequency change or shake, and its course of work is as follows.
Resistance 83-84 is as a voltage divider job that distributes input voltage VIN, and electric capacity 85 cooperates resistance 83-84 to form a low pass filter, and this filter produces an average voltage<V
IN1, the ripple of this average voltage is zero substantially, perhaps at least than V
INRectified sinusoidal very little.In one embodiment, resistance 83-84 and the electric capacity 85 selected low pass corner frequencies of fetching are set to about 10 hertz, thus V
RBe roughly a dc voltage.As the result of this low-pass filtering,<V
IN1Just can represent V
INMean value.
Multiplier 86 is analog multiplier circuits of a standard, its power average voltage V
IN1To produce a squared voltage V
SQ=K
8*<V
IN1 2, K wherein
8It is a constant.
Division circuit 87 is with reference voltage V
REFDivided by V
SQTo produce a voltage V
LIM=V
DIV=V
REF/ (K
8*<V
IN1 2), this voltage is coupled to resistance 88 two ends, thus an input at comparator 69 is provided with V when clock signal clk is low level
RAMPThe upper limit.When CLK is high level, switch 90 closures, V
DIVBy resistance 88-89 dividing potential drop, thereby set up V
RAMLower limit, this lower level is V
LIM=V
REF/ (K
8*<V
IN1 2) * R
89/ (R
88+ R
89), R wherein
88And R
89It is respectively the resistance of resistance 88 and 89.
Thereby, obtain switching frequency F
SW=K
9*<V
IN 2* (V
REF-V
IN), K wherein
9It is a constant.This option makes that oscillator 35 can the limit switch frequency change, with auxiliary EMI filtering.
Fig. 6 shows the principle schematic of a pfc circuit 100 in the alternative.Do not need resistance 18 among this embodiment, thereby eliminated the power P of its consumption yet
R18=I
IN 2* R
18, R wherein
18It is the resistance of resistance 18.Therefore, this embodiment is suitable for the application scenario of the power factor that needs low standby power loss and be lower than ideal value.
Embodiment shown in Figure 6 coil current I
COILInstantaneous value but not input voltage
VINModulation switch frequency F
SWOn an average, since the power factor calibration operation of pfc circuit 100, I
COILHave and V
INThe sinusoidal waveform of homophase.I
COILTo the return path of diode bridge 20, be detected through resistance 72 at it, and on node 39, form a current sense voltage V who strides resistance 72 two ends
CS, in order to modulation F
SWIn one embodiment, the resistance of resistance 72 is about 0.1 ohm, at I
COILAmplitude is 1 ampere-hour, V
CSValue be approximately-0.1 volt.In addition, I
COILAlso can measure, replace induction by current resistance 72 such as Current Transformer with other technologies.Use coil current I
COILBut not input voltage V
INChange switching frequency F
SW, this is a kind of method that continuous mode also is fit to the discontinuous mode PFC circuit that both had been fit to, and also is suitable for the power factor calibration and is combined in an embodiment in the single-level circuit with downstream electrical voltage regulator or transducer.
The power factor of this embodiment can be lower than previous described embodiment according to believing, because I
COILInstantaneous value just approach V
INSinusoidal waveform through over commutation.But this version has lower power consumption, and can be with the low cost manufacturing, and this makes it be applicable to many application scenarios that do not need highest power factor.In one embodiment, power factor can be by improving at electric capacity of resistance 72 two ends cross-over connections.The selected filtering radio-frequency component that is used for of this electric capacity, for example those are higher than V
INThe composition of frequency, thus a waveform on node 39, produced, and this waveform more desirably has been similar to rectified sine wave.
Fig. 7 shows the part of the pfc circuit 100 in embodiment illustrated in fig. 6, comprising a resistance 82, a current source 78, and the more details of the current mirror 57 of oscillator 35.
That transistor 76-77 is illustrated as constituting a coupling or proportional NPN bipolar transistor is right, these transistorized emitter regions are in predetermined ratio setting.Current source 78 provides an electric current I by transistor 77
RTo set up a base-emitter voltage, this voltage is biased to the base electrode of transistor 76 on the fixing electromotive force.
Resistance 82 is made into a non-essential resistance usually, to avoid I
COILCurrent sense voltage V when flowing
CSThe ill effect that causes of negative potential.If transistor 76 and 77 has identical emitter area ratio, their emitters separately will be operated on the essentially identical electromotive force so, because V
CS=-R
72* I
COIL, thereby electric current I
M1With I
COILBe directly proportional I
SENSESubstantially equal I
M1(ignoring 57 base currents) and V
CS+ (R
82* I
SENSE) be zero, wherein the resistance of resistance 82 is R
82, the selected desirable sample rate current I that the transistor 76 of flowing through is provided that fetches of this resistance
SENSEI so
M1=R
72* I
COIL/ R
82I
SENSEBy current mirror 58-59 mirror image so that provide difference charging and discharging current (I to timing node 70 respectively
REF1-I
M3) and (I
REF2-I
M1), as indicated above.
Put it briefly, the invention provides a kind of pfc circuit, this circuit can be operated under the discontinuous mode of floatless switch pulsewidth.This discontinuous mode of operation makes pfc circuit can use blocking diode manufacturing cheaply, has so just reduced system cost.To produce pulse, this pulse is that coil current is set up charge cycle synchronously at the saltus step edge of pulse width modulator and clock signal.Described coil current is then discharged in discharge cycle, thereby forms a PFC output voltage by an input signal.An oscillator clocking makes its clock cycle be longer than charging and adds the summation in discharge cycle, thereby guaranteed the work of discontinuous mode.Oscillator has an input, is used to detect the input signal of pfc circuit, so that change the clock cycle in a controlled manner, thereby keeps the product of charge cycle and coil current duty factor to fix.Like this, pfc circuit just can be in a predetermined frequency range switching line loop current, to help to reduce electromagnetic interference with a low-cost electromagnetic interface filter.
Claims (25)
1. a power factor is calibrated (PFC) circuit, comprising:
The pulse width modulator of a response clock signal job is used at switching line loop current on the charge cycle so that the power factor on the calibration first node, and wherein said coil current discharges on a discharge cycle to form an output voltage; And
An oscillator, it has an output and brings in the described clock signal of generation, the clock cycle that this clock signal has is longer than the summation of described charging and discharge cycle, and a first input end, is used to detect the input signal of pfc circuit to regulate the described clock cycle.
2. pfc circuit according to claim 1, the load current of wherein said output voltage is a steady state value, described charging and discharge cycle are summed on the described clock cycle, defining the duty factor of described coil current, and described input signal changes the described clock cycle and keeps the product constant of duty factor and charge cycle.
3. pfc circuit according to claim 1, the input signal of wherein said pfc circuit are basically with the form work of rectified sine wave voltage.
4. pfc circuit according to claim 1, wherein said oscillator are formed a voltage controlled oscillator, comprising:
The ramp generator of the described clock signal work of response, it has a Section Point provides charging current to form a ramp voltage to an electric capacity, and this ramp voltage rises to second reference level from first reference level in charge cycle;
A comparator is used for more described ramp voltage and first and second reference voltage, and this comparator also has an output that is connected to described oscillator output end; And
A current mirror, it has a first input end, is used for receiving the input current of the described input signal of representative, so that one first image current to be provided to Section Point, to be used for deducting this image current from charging current and to change the described clock cycle.
5. pfc circuit according to claim 4, wherein said current mirror provide one second image current in order to the charging Section Point, and described ramp generator comprises:
First current source that is connected to described Section Point is used to provide described charging current; And
One second current source, it is coupled with a discharging current discharges to Section Point, wherein deducts second image current from described discharging current.
6. pfc circuit according to claim 1, wherein said pulse width modulator have a feedback input end, and this input is connected and detects described output voltage, so that come the charge cycle of regulating impulse according to the load current of pfc circuit.
7. pfc circuit according to claim 1, the output voltage shown in it has the value that is higher than described input signal crest voltage.
8. pfc circuit according to claim 1, wherein said input signal has been represented described coil current.
9. pfc circuit according to claim 8 wherein also comprises an inductive reactance that is connected to the oscillator first input end, is used for the described coil current of conducting and forms an induced voltage.
10. the power factor with discontinuous mode work is calibrated (PFC) circuit, comprising:
A pulse width modulator, it has an input that is used for receiving a plurality of pulses, and pulse duration has been represented the load current of pfc circuit, and to be used for the charge coil electric current, described coil current is discharged forms an output voltage; And
An oscillator, it has an output and is used for producing described a plurality of pulse with a selected frequency, coil current being discharged to zero, and an input, be used to detect the input signal of pfc circuit to regulate described frequency.
11. pfc circuit according to claim 10, wherein said output voltage are formed on the node, and described pulse has back edge and is used for coil current is discharged on the electric capacity of described node to form described output voltage.
12. pfc circuit according to claim 11, when described load current was constant, described pulsewidth was basic identical.
13. the method for the power factor of an input signal of a calibration comprises:
Utilize clock signal to produce a plurality of pulses, so that set up a charge cycle for coil current, the clock cycle of wherein said clock signal will be longer than the summation of the charge cycle and the discharge cycle of coil current;
On discharge cycle, coil current is discharged to zero to form an output voltage; And
The input signal that detects pfc circuit is to change the described clock cycle.
14. method according to claim 13, the load current of wherein said output voltage is constant, described charging and discharge cycle are added a duty factor with definite described coil current on a clock cycle, and described input signal changes the described clock cycle to keep the product constant of described duty factor and charge cycle.
15. method according to claim 14 also comprises:
With a charging current electric capacity is charged to produce a ramp voltage;
More described ramp voltage and one first reference voltage are to produce described clock signal;
And
The input current of the described input signal of one of mirror image expression, and provide one first image current to change the clock cycle to described electric capacity.
16. comprising, method according to claim 15, wherein said mirror image from described charging current, deduct first image current to change the described clock cycle.
17. method according to claim 16, wherein said mirror image comprise that first saltus step according to described clock signal enables first image current.
Improve described ramp voltage 18. method according to claim 15, wherein said charging comprise with described charging current, and describedly relatively comprise first saltus step that produces described clock signal.
19. method according to claim 15 also comprises:
With a discharging current to described capacitor discharge, to reduce described ramp voltage; And
More described ramp voltage and one second reference voltage are with second saltus step of clocking.
20. method according to claim 18 comprises that also the described input current of mirror image is to provide one second image current, to deduct this image current from described discharging current, to change the described clock cycle.
21. power factor calibration (PFC) circuit comprises:
A basis is used for the pulse width modulator of the clock signal work of synchronous a plurality of pulses, and described a plurality of pulses are set up a coil current from an input voltage, and described coil current is discharged forms an output voltage; And
An oscillator, it has an output and is used for producing described clock signal with certain frequency, and an input is used to detect described coil current to change described frequency.
22. pfc circuit according to claim 21, wherein said clock signal through first saltus step from first logic level to second logic level, through second saltus step from second logic level to first logic level, and described pulse width modulator responds described first saltus step and produces described a plurality of pulse.
23. pfc circuit according to claim 21, wherein said a plurality of pulses have fixing pulsewidth.
24. pfc circuit according to claim 21 also comprises a current path that links to each other with the input of oscillator, is used for the described coil current of conducting to form an induced signal.
25. pfc circuit according to claim 24, wherein said current path comprise a resistance, described induced signal just is formed on this resistance.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2003/013859 WO2004107546A1 (en) | 2003-05-06 | 2003-05-06 | Power factor correction circuit and method of varying switching frequency |
Publications (2)
Publication Number | Publication Date |
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CN1663101A true CN1663101A (en) | 2005-08-31 |
CN100423417C CN100423417C (en) | 2008-10-01 |
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Application Number | Title | Priority Date | Filing Date |
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CNB038142376A Expired - Fee Related CN100423417C (en) | 2003-05-06 | 2003-05-06 | Power factor calibrating circuit having variable switching frequency |
Country Status (5)
Country | Link |
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CN (1) | CN100423417C (en) |
AU (1) | AU2003228831A1 (en) |
HK (1) | HK1081334A1 (en) |
TW (1) | TWI334256B (en) |
WO (1) | WO2004107546A1 (en) |
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CN101546954A (en) * | 2008-03-27 | 2009-09-30 | 半导体元件工业有限责任公司 | Method of forming a power supply controller and structure therefor |
US7777474B2 (en) | 2006-06-09 | 2010-08-17 | Fujitsu Semiconductor Limited | DC-DC converter with oscillator and monitoring function |
CN102624215A (en) * | 2012-01-16 | 2012-08-01 | 崇贸科技股份有限公司 | Circuit and method for reducing electromagnetic interference of power converter |
CN101226764B (en) * | 2006-08-29 | 2012-08-29 | 尔必达存储器株式会社 | Calibration circuit, semiconductor device with the same, and output characteristic adjusting method of semiconductor device |
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US9618955B2 (en) | 2008-11-07 | 2017-04-11 | Power Integrations, Inc. | Method and apparatus to increase efficiency in a power factor correction circuit |
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US7400127B2 (en) * | 2005-05-23 | 2008-07-15 | Semiconductor Components Industries, L.L.C. | Method for regulating an output signal and circuit therefor |
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US8716999B2 (en) * | 2011-02-10 | 2014-05-06 | Draker, Inc. | Dynamic frequency and pulse-width modulation of dual-mode switching power controllers in photovoltaic arrays |
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US5146398A (en) * | 1991-08-20 | 1992-09-08 | Led Corporation N.V. | Power factor correction device provided with a frequency and amplitude modulated boost converter |
US5367247A (en) * | 1992-08-10 | 1994-11-22 | International Business Machines Corporation | Critically continuous boost converter |
US5408403A (en) * | 1992-08-25 | 1995-04-18 | General Electric Company | Power supply circuit with power factor correction |
KR0134914B1 (en) * | 1995-06-29 | 1998-04-25 | 김광호 | Analog oscillation circuit |
-
2003
- 2003-05-06 AU AU2003228831A patent/AU2003228831A1/en not_active Abandoned
- 2003-05-06 CN CNB038142376A patent/CN100423417C/en not_active Expired - Fee Related
- 2003-05-06 WO PCT/US2003/013859 patent/WO2004107546A1/en active Application Filing
-
2004
- 2004-04-20 TW TW093110996A patent/TWI334256B/en not_active IP Right Cessation
-
2006
- 2006-01-26 HK HK06101178.6A patent/HK1081334A1/en not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
WO2004107546A1 (en) | 2004-12-09 |
TWI334256B (en) | 2010-12-01 |
TW200505137A (en) | 2005-02-01 |
HK1081334A1 (en) | 2006-05-12 |
CN100423417C (en) | 2008-10-01 |
AU2003228831A1 (en) | 2005-01-21 |
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