1334180 _ 99年6月29曰修正替換頁 九、發明說明： - 【發明所屬之技^1#領域】 - 本發明係有關一種半導體結構及其製造方法，特別是一 . 種晶粒封裝結構及其封裝方法。 【先前技術】 隨著半導體製程之進步，以及使用者對電子產品輕薄短小特色 之要求與日俱增，使得降低晶粒封裝體之尺寸變成各家廠商競爭之要 點’由既往之單片晶粒封裝轉向多片晶粒封裝，如堆疊式晶粒封裝或 晶粒並排式（Side by Side)封裝，以縮小晶粒封裝體在應用印刷電路 板上之面積並提升電性功能。 一般傳統晶圓切割係利用切割刀沿著晶圓表面上之切 割道，將每一晶粒分開，以形成複數個獨立之晶粒；爾後， 再將單一的晶粒放置到基板上，以進行封裝。請參閱第1圖， 所示為根據習知之晶圓切割方法所形成之封裝體示意圖，晶 粒2、4係並排於基板6上，並利用複數個電接元件7(例如： 引線或銲球）電性連接晶粒2、4及基板6，最後以一封裝膠 體（圖中未示）包覆晶粒2、4、基板6、以及電接元件7以 形成一封裝體1。 【發明内容】 為了解決上述問題，本發明之一目的係在提供一種晶粒封 裝、、。構及其封裝方法，利用以兩晶粒或複數顆晶粒為—切割單位進行 晶粒封裝，可減少晶粒黏著次數'簡化製程、縮小晶粒封裝體之尺寸、 - 降低成本、及提升產品競爭力。 5 1334180 99年6月29日修正替換頁 本發明之-目的係在提供—種日日日粒封裝結構及其封裝方法， 二#兩1$切割單位進行晶粒封裝，可增加單位時間内晶粒封 、衣°的產量’具有驗整體製程之獅賴的優點。 ㈣错為了達到上述目的，本發明之一實施例提供一種晶粒封 ^構’包含：—基板；至少-晶粒模組，係設置於基板上，其 = 模組係包含至少兩晶粒彼此相連，且該些晶粒係為二 早位，及一電接元件’係電性連接晶粒模組與基板。 ，了達到上述目的，本發明之—實施例提供—種晶粒封 ίΐί ’包含下列步驟：提供—基板；提供—晶圓，其中晶圓包含 割道·，沿著切割道以至少兩相連之晶粒為單位切割晶圓，以 形成複數個晶粒模組；至少一晶粒模組於基板上；以及設置一電接 元件電性連接晶粒模組與基板。 以下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解 本發明之目的、技術内容、繼及其所達成之功效。 【實施方式】 請參閱第2圖，為依據本發明所實施—實施例之晶粒封裝方 法流程圖。於此實施例中，晶粒封裝方法包含··提供一基板（步驟 =〇)，提供至少-晶粒模組設置於基板上，其中晶粒模組係包 3至少兩晶粒彼此相連’且該些晶粒係為—切割單位（步驟 S20)，·以及設置-電接元件電性連接晶粒模組與基板（步驟㈣）。 請繼續參閱第4圖’前述晶粒雖方法中，提供晶粒模组之 =驟（步驟S則更包含下列步驟··提供一包含複數條切割道之晶 SK步驟S40)’·利用-切割刀沿著切割道切割晶圓，以兩相連 ，晶粒為單位進行晶圓切割（步驟S5G);最後，形成複數個 s曰粒模組，其中每—晶粒模組具有至少二相連之晶粒（步驟 6 99年6月29日修正替換頁 S60)。最後再設置一封裝材料（圖中未示）包覆晶粒模組與電接 元件，以形成一晶粒封裝結構。 請參閱第3圖，為依據本發明所實施_實施例之晶粒封裝結構 示意圖。於此實施例中’晶粒封裝結構10包含一基板6 ·至,|、曰 少 日日 粒模組8，係設置於基板6上，其中晶粒模組8係包含至少 兩晶粒82、84彼此相連，且兩晶粒82、84係為一切割單位； 及一電接元件7 (例如：複數條引線或複數個銲球），係電性連接曰’ 8 粒模組8與基板6，最後以-封裝材料（圖中未示）包覆晶粒模： ^'電接元件7、以及基板6。 、 综合上述，本發明所提供之晶粒封裝結構及其封裝方法係以兩 相連之晶粒（晶粒模組）或複數顆晶粒為—切割單位進行封裝，透過 應用晶粒模組，可增加單位時_晶粒封裝製簡產量、縮短 =週期_、減少晶粒封·之尺寸、降低成本、以及提升產品^ 點，Γ目H述之實施難料說日林發明之技術思想及特 並據能夠瞭 本發明所搞-夕：：： 專利範圍，即大凡依 發明之神所作之均等變化或修飾，仍應涵蓋在本 【圖式簡單說明】 =圖所示為根制知晶_割方法所形成之晶粒封裝結構示意 I彳Τ騎據本發騎實施_實_之晶姉裝方法流程圖。 β 4轉本發明所實施—實施例之晶粒封裝結構示意圖。 1334180 99年6月29日修正替換頁 第4圖所示為依據本發明所實施一實施例之晶圓切割方法流程圖。【主要元件符號說明】 1 晶粒封裝體 7 電接元件 2 第一晶粒 8 晶粒核組 4 第二晶粒 10 晶粒封裝結構 6 基板 82、84 晶粒 S10、 S20、S30、S40、 S50 、 S60 步驟1334180 _June 29, 1999 Correction replacement page IX, invention description: - [Technology of the invention] - The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a die package structure and Its packaging method. [Prior Art] With the advancement of semiconductor manufacturing process and the increasing demand for thin and light electronic products, the reduction of the size of die package has become the main point of competition among manufacturers. Chip die packages, such as stacked die packages or side by side packages, reduce the area of the die package on the printed circuit board and enhance electrical functionality. In general, conventional wafer cutting uses a dicing blade to separate each die along a dicing street on the surface of the wafer to form a plurality of independent dies; then, a single dies are placed on the substrate for processing. Package. Please refer to FIG. 1 , which is a schematic diagram of a package formed according to a conventional wafer dicing method. The dies 2 and 4 are arranged side by side on the substrate 6 and utilize a plurality of electrical components 7 (eg, leads or solder balls). The die 2, 4 and the substrate 6 are electrically connected, and finally the die 2, 4, the substrate 6, and the electrical component 7 are coated with an encapsulant (not shown) to form a package 1. SUMMARY OF THE INVENTION In order to solve the above problems, it is an object of the present invention to provide a die package. Structure and its packaging method, using two or more grains as the cutting unit for die encapsulation, can reduce the number of die adhesions. 'Simplify the process, reduce the size of the die package, reduce costs, and enhance the product. Competitiveness. 5 1334180 Revision of the page on June 29, 1999. The present invention is directed to providing a day-to-day solar package structure and a package method thereof, and two #1$$ cutting units for die encapsulation, which can increase the crystal per unit time. The production of grain seals and garments has the advantages of the overall process. (4) In order to achieve the above object, an embodiment of the present invention provides a die seal comprising: a substrate; at least a die module disposed on the substrate, wherein the module comprises at least two die Connected, and the die is in the early position, and an electrical component is electrically connected to the die module and the substrate. In order to achieve the above object, the present invention provides an embodiment of the present invention. The method includes the steps of: providing a substrate; providing a wafer, wherein the wafer comprises a kerf, and at least two are connected along the scribe line. The die is diced to form a plurality of die modules; at least one die is mounted on the substrate; and an electrical component is electrically connected to the die module and the substrate. The details of the present invention, the technical contents, and the effects achieved by the present invention will be more readily understood by the following detailed description in conjunction with the accompanying drawings. [Embodiment] Please refer to Fig. 2, which is a flow chart of a die package method according to an embodiment of the present invention. In this embodiment, the die package method includes: providing a substrate (step = 〇), providing at least a die module disposed on the substrate, wherein the die module package 3 at least two dies are connected to each other' The die is a cutting unit (step S20), and the setting-electrical component is electrically connected to the die module and the substrate (step (4)). Please refer to FIG. 4 for the above-mentioned die. In the method of providing the die, the die module is provided. (Step S includes the following steps: providing a crystal SK step S40 including a plurality of dicing streets.) · Utilization-cutting The knives cut the wafer along the scribe line, and perform wafer dicing in two connected, die units (step S5G); finally, a plurality of s granule modules are formed, wherein each of the die modules has at least two connected crystals Granules (Step 6 June 29, 1999 revised replacement page S60). Finally, a package material (not shown) is disposed to cover the die module and the electrical component to form a die package structure. Please refer to FIG. 3, which is a schematic diagram of a die package structure according to an embodiment of the present invention. In this embodiment, the die package structure 10 includes a substrate 6 . . . , and a solar cell module 8 is disposed on the substrate 6 , wherein the die module 8 includes at least two crystal grains 82 . 84 are connected to each other, and the two crystal grains 82, 84 are a cutting unit; and an electrical connection component 7 (for example, a plurality of leads or a plurality of solder balls), electrically connected to the 8 module 8 and the substrate 6 Finally, the die mold is coated with a package material (not shown): ^' electrical connection component 7, and substrate 6. In summary, the die package structure and the package method thereof provided by the present invention are packaged by two connected die (die modules) or a plurality of die-cut units, and the die module can be applied through the application. When adding units, _ die package, simple output, shortening = cycle _, reduce the size of the die seal, reduce the cost, and improve the product point, the implementation of the project H is difficult to say, the technical ideas and special features of the invention And according to the invention can be carried out - eve::: The scope of patents, that is, the equivalent changes or modifications made by the god of invention, should still be covered in this [simplified description of the schema] = the diagram shows the root system _ The die package structure formed by the cutting method is shown in the flow chart of the crystal mounting method according to the present invention. 4 is a schematic diagram of a die package structure implemented by the present invention. 1334180 Modified Replacement Page, June 29, 1999 Figure 4 is a flow chart of a wafer cutting method in accordance with an embodiment of the present invention. [Main component symbol description] 1 die package 7 electrical component 2 first die 8 die core group 4 second die 10 die package structure 6 substrate 82, 84 die S10, S20, S30, S40, S50, S60 steps