TWI334132B - Error correction system and related method thereof - Google Patents

Error correction system and related method thereof Download PDF

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TWI334132B
TWI334132B TW96114095A TW96114095A TWI334132B TW I334132 B TWI334132 B TW I334132B TW 96114095 A TW96114095 A TW 96114095A TW 96114095 A TW96114095 A TW 96114095A TW I334132 B TWI334132 B TW I334132B
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ecc
value
edc
symptom
error correction
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TW200805297A (en
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Kuo Lung Chien
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Mediatek Inc
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  • Detection And Correction Of Errors (AREA)
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1334132 九、發明說明: 【發明所屬之技術領域】 特別有關於光碟機的錯誤更正 本發明有關於錯誤更正系統 系統及其方法。 【先前技術】 隨著科技的進步,光碟__及儲存於其上的資料 ^之增加,因此光韻需要錯誤勤以及更正機綱定讀取到正 確的資料。 第1圖緣示了相關技術之錯誤更正系統1〇〇。如第i圖所示, 錯誤更正系統100包含-資料緩衝器1〇1,一解調器1〇3,一徵狀 值產生器1〇5、-徵狀值記憶體1〇7、一 ECC (_r c槪cti〇n c〇㈣ 解碼器應…線性卽咖贿細細㈣啊確認元件出、^^ 。己憶體113以及-EDC更正器ι15。在此例中,當儲存在資料緩 衝器ιοί中的資料量足夠解碼時,儲存在資料缓衝器1〇1中的ecc 區塊(ECC block)被讀出以執行PI/p〇徵狀值計算以及線性 E〇c。同時,若發現錯誤,則施行PIECC動作以修正儲存在資料 緩衝器101中的錯誤資料,而儲存在徵狀值記憶體107十的徵狀 值亦被更新。而且’下一方向的ECC動作(此例中為P0)係直接 頌取儲存在徵狀值記憶體'107中的徵狀值,而不是根據資料緩衝 器ιοί中的資料計算徵狀值。然而,此類結構缺乏η方向的Ecc, W4132 較差之效能。而且,這樣的結構缺乏能克服_定同 / 堝移(frame sync shift)的問題。 曰除了前述的相關技術,還有其他的相關技術亦被發展出來, 但亦因為其侧素而具有其他缺點,這些缺點可簡述如下。若 ^僅具有預先(on the fly) P0徵狀值計算,其無法克服巾貞鎖定=步 =。而且,若系統具有預先EDC機制,其亦無法克服難定同 步偏移。絲祕有最後咖_,其祕雜絲表現。 2有預先徵狀值計算,其具有較高的成本^統在解調器和 〜,IIECC凡件之間不具有記憶體元件,系統無法克服因為同步 貝4遺失而引起的_1同步偏移問題,且會因為資料緩衝器上 的更正週_具有較差賴寬。預先(Gnthefly)係表· 入資料緩衝器之前便做處理。 貝科在進 【發明内容】 因此’本發明的目的之一為提供—種錯誤更正系統,其可避 免上述之缺點並維持上述之優點。 本發明之—實施_露了—種錯誤更m包含:一解調 器’用以接收和解調原始資料以產生一 ECC區塊;一預先pi ecc 解碼益’祕至該解調$,用以對來自該解調器的該ecc區塊施 '亍H ECC動作以產生更正後Ecc區境;一資料緩衝器,用以 儲存該ECC區塊和該更正後咖區塊;一非線性edc確認裝置, 7 1334132 用以根據儲存在該資料緩衝器内的該ECC區塊施行一非線性EDC 動作以產生一 EDC結果;一徵狀值產生器,用以根據儲存在該資 料緩衝器内的該ECC區塊之一碼字以產生至少一徵狀值;一 ecc 解碼器’用以根據該徵狀值施行一 ECC動作;以及一 EDC更正 器,用以根據該ECC動作之一結果更正該EDC結果;其中該徵 狀值包含一 PI徵狀值以及一 P0徵狀值其中至少其一,碼字包含 PI碼字以及一 P0碼字其中至少之一。 本發明的實施例亦揭露了對應此系統的錯誤更正方法,包 3 (a)接收和解調原始資料以產生一 ECC區塊;(b)對來自該步 驟⑷的該ECC區塊施行一 PIECC動作以產生一更正後ECc區 塊,(c)儲存該Ecc區塊和該更正後ECC區塊;⑹根據該步驟⑷ 儲存的該ECC區塊施行一非線性EDC動作以產生一 ED(:結果; ()根據該步驟⑹儲存的該ECC區塊之__ρι碼字以及一⑺碼字 產生至少一徵狀值;(f)根據該徵狀值施行一 Ecc動作;以及(幻 _該ECC動作之一結果更正該EDC結果;其中該徵狀值包含 PI徵狀值以及一 P0徵狀值其中至少其一。 本發明之另-實施例揭露了—種錯誤更正系統,包含:一解 調裔’用以接收和解調原始資料以產生-ECC區塊;-種資料緩 ^"用^儲存該ECC區塊以及更正後ECC區塊;一預先pi ECC ,馬器#接至該解調器,用以對來自該解調器的該 ECC區塊施 订PI ECC動作以產生該更正後Ε(χ區塊;一記憶體元件,用1334132 IX. Description of the invention: [Technical field to which the invention pertains] In particular, the error correction of the optical disk drive The present invention relates to an error correction system system and a method thereof. [Prior Art] With the advancement of technology, the number of optical discs __ and the data stored on them has increased, so the rhyme needs to be erroneously and the correct machine can read the correct data. The first figure shows the error correction system of the related art. As shown in the figure i, the error correction system 100 includes a data buffer 1〇1, a demodulator 1〇3, a syndrome generator 1〇5, a symptom value memory 1〇7, an ECC. (_r c槪cti〇nc〇 (4) The decoder should be... linear 卽 贿 贿 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( When the amount of data in ιοί is sufficient for decoding, the ecc block (ECC block) stored in the data buffer 〇1 is read out to perform PI/p 状 值 value calculation and linear E 〇 c. In the case of an error, the PIECC action is performed to correct the error data stored in the data buffer 101, and the syndrome value stored in the symptom value memory 107 is also updated. And the 'ECC action in the next direction (in this case, P0) directly extracts the symptom value stored in the symptom value memory '107, instead of calculating the symptom value according to the data in the data buffer ιοί. However, such a structure lacks the Ecc in the η direction, and the W4132 is poor. Performance. Moreover, such a structure lacks the problem of overcoming the frame sync shift. The related art mentioned above, and other related technologies have also been developed, but also have other disadvantages because of its side effects. These disadvantages can be briefly described as follows. If only the P0 symptom value calculation is performed on the fly It can't overcome the frame lock = step =. Moreover, if the system has the pre-EDC mechanism, it can not overcome the difficult synchronization offset. The silk secret has the last coffee _, its secret silk performance. 2 has the pre-symptom value calculation , it has a higher cost ^ system in the demodulator and ~, IIECC between the pieces do not have memory components, the system can not overcome the _1 synchronization offset caused by the loss of synchronous shell 4, and because of data buffering The correction week on the device has a poorer width. The Gnthefly table is processed before entering the data buffer. Beko is in the field of invention. Therefore, one of the objects of the present invention is to provide an error correction system. , which avoids the above disadvantages and maintains the above advantages. The present invention - the implementation of the error - more m includes: a demodulator 'to receive and demodulate the original data to generate an ECC block; a pre-pi Ecc solution The deciphering $ is used to perform a '亍H ECC action on the ecc block from the demodulator to generate a corrected Ecc area; a data buffer for storing the ECC block and the Correcting the post-block; a non-linear edc confirming device, 7 1334132 for performing a non-linear EDC operation based on the ECC block stored in the data buffer to generate an EDC result; a symptom generator Generating at least one syndrome value according to one of the ECC blocks stored in the data buffer; an ecc decoder 'for performing an ECC action according to the syndrome value; and an EDC corrector for Correcting the EDC result according to one of the ECC actions; wherein the syndrome value comprises a PI symptom value and a P0 symptom value, wherein at least one of the code words comprises at least one of a PI code word and a P0 code word. . Embodiments of the present invention also disclose a method of error correction corresponding to the system. Packet 3 (a) receives and demodulates the original data to generate an ECC block; (b) performs a PIECC action on the ECC block from the step (4). To generate a corrected ECc block, (c) storing the Ecc block and the corrected ECC block; (6) performing a non-linear EDC action according to the ECC block stored in the step (4) to generate an ED (: result; () generating at least one symptom value according to the __ρ code word and one (7) code word of the ECC block stored in the step (6); (f) performing an Ecc action according to the symptom value; and (the illusion_the ECC action A result corrects the EDC result; wherein the syndrome value comprises at least one of a PI symptom value and a P0 symptom value. Another embodiment of the present invention discloses a error correction system comprising: a demodulation class For receiving and demodulating the original data to generate an -ECC block; - storing the ECC block and correcting the ECC block; and pre-pi ECC, the horse is connected to the demodulator, Used to apply a PI ECC action to the ECC block from the demodulator to generate the correction ([Chi] block; a memory device, with

I 1334132 以儲存來自該資料緩衝器的一部份該EC6區塊;一非線性EDC . 確認裝置,用以對該資料緩衝器中的該ECC區塊施行一非線性 ‘ EDC動作以產生一 EDC結果;一 p〇徵狀值產生器,用以根據該 • 記憶體元件内的該一部份ECC區塊之P0碼字產生一 p〇徵狀值; 一 PI徵狀值產生器,用以根據該記憶體元件内儲存的該部份ECC 區塊產生一 PI徵狀值;—Ecc解碼器,用以根據該徵狀值以 及該p〇徵狀值其中至少其一施行ECC動作;以及一 EDC更正 器,用以根據該ECC動作之結果更正該EDC結果。 本發明的實施例亦揭露了對應此系統的錯誤更正方法,包 含.(a)接收和解調原始資料以產生一 ECC區塊;(b)對來自該步 驟(a)的該ECC區塊施行一 PI ECC動作以產生一部份EC(:區 塊,⑹儲存該ECC區塊以及該部分ECC區塊;(d)對該步驟作) 中儲存的該ECC區塊施行一非線性EDC動作以產生一 ED(:結 果’(e)根據該步驟(b)中儲存的該一部份ECC區塊之p〇碼字 產生一p〇徵狀值;(f)根據該步驟(c)中儲存的該部份ecc區塊 產生—Π徵狀值;(g)根據該PI徵狀值以及該P0徵狀值其中至 夕其—對該步驟⑹中儲存的該ECC區塊施行ECC動作;(h)根 , 據該步驟⑹中儲存的該一部份ECC區塊產生該PI徵狀值;① 根據該ECC動作之結果更正該 EDC結果。 【實施方式】 在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱 寺定的7L件所屬領域中具有通常知識者應可理解,硬體製造商 ^月b曰用不同的名雜稱呼同—航件。本說明書及後續的申請 專利範圍並不以名稱的差異來作為區分雜的方式,而是以元件 在功此上的ϋ異來作祕分的翔。在通篇說明書及後續的請求 =田中所提及的「包含」係為—開放式的用語,故應解釋成「包 3 <不限定於」。财卜,「域」—詞在絲包含任何直接及間接 的電氣連接手段。@此,若文中描述-第-裝置祕於-第二敦 置’則代表該第U可直接電氣連接於該第U,或透過其 他裝置或連接手段間接地電氣連接至該第二裝置。 第2圖繪示了根據本發明之第-實施例的錯誤更正系統的方 境圖。如帛2圖所示,錯誤更正系統11〇〇包含一資料緩衝器11〇1、 解調器1103、一預先(on the fly) EDC確認元件11〇5 (如上所 述,預先係表示資料在進入資料緩衝器之前被處理)、一徵狀值產 生器1107、一徵狀值記憶體u〇9、一 gee解碼器ιιη、一 EDC 圮憶體1113以及一 EDC更正器1115。解調器11〇3係用以接收 並解調來自光碟1102的原始資料以產生包含資料、ρι碼字(ρι codeword)和PO碼字(p〇 codeword)的ECC區塊。預先EDC確認 元件1105用以根據來自解調器11〇5的資料施行操作以產生 一 EDC結果。資料緩衝器1101被用以儲存Ecc區塊以及EDC 結果。徵狀值產生器1107根據儲存在資料緩衝器iioi内的?1碼 字和PO碼字產生PI和PO徵狀值。徵狀值記憶體11〇9係用以儲 存PI徵狀值和PO徵狀值。ECC解碼器111係用以根據徵狀值記 1334132 憶體1109中的PI徵狀值和P0徵狀值對資料緩衝器iioi中的gee 區塊之資料施行錯誤更正’並根據勘誤結果(errata result)修正徵 狀值記憶體1109中的PI徵狀值和p〇徵狀值。EDc記憶體1113 係用以緩衝EDC結果。EDC更正器1115根據來自ECC解碼器mi 的勘誤結果修正EDC結果。I 1334132 to store a portion of the EC6 block from the data buffer; a non-linear EDC. acknowledgment means for performing a non-linear 'EDC action on the ECC block in the data buffer to generate an EDC a p〇 syndrome generator for generating a p〇 syndrome value according to the P0 codeword of the portion of the ECC block in the memory component; a PI syndrome generator for Generating a PI symptom value according to the part of the ECC block stored in the memory component; an Ecc decoder for performing an ECC action according to the symptom value and the p〇 symptom value; and An EDC corrector for correcting the EDC result based on the result of the ECC action. Embodiments of the present invention also disclose error correction methods corresponding to the system, including: (a) receiving and demodulating original data to generate an ECC block; (b) performing an ECC block from the step (a) PI ECC action to generate a portion of the EC (: block, (6) store the ECC block and the portion of the ECC block; (d) the ECC block stored in the step to perform a non-linear EDC action to generate An ED (the result '(e) generates a p〇 symptom value according to the p〇 codeword of the part of the ECC block stored in the step (b); (f) according to the storage stored in the step (c) The portion of the ecc block generates a Π symptom value; (g) according to the PI symptom value and the P0 symptom value, wherein the ECC action is performed on the ECC block stored in the step (6); Root, generating the PI symptom value according to the part of the ECC block stored in the step (6); 1 correcting the EDC result according to the result of the ECC action. [Embodiment] Used in the specification and the subsequent patent application scope Some vocabulary to refer to the general knowledge of the 7L parts of the temple should be understandable, the hardware manufacturer ^ b 曰 不同 曰 曰 曰 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Xiang. In the entire manual and subsequent requests = "include" mentioned in Tanaka is an open-ended term, so it should be interpreted as "package 3 < not limited to". Finance, "domain" - word in The wire contains any direct and indirect electrical connection means. @本, if described in the text - the first device - the second device, means that the U can be directly electrically connected to the U, or through other means or means of connection The grounding is electrically connected to the second device. Fig. 2 is a diagram showing the environment of the error correction system according to the first embodiment of the present invention. As shown in Fig. 2, the error correction system 11 includes a data buffer 11 〇1, demodulator 1103, on the fly EDC confirmation component 11〇5 (as described above, the data is pre-processed before being entered into the data buffer), a syndrome generator 1107, a sign Shape memory u〇9, a gee decoder ιιη An EDC memory 1113 and an EDC correction unit 1115. The demodulator 11〇3 is configured to receive and demodulate the original data from the optical disc 1102 to generate an included data, a ρι codeword, and a PO codeword (p The ECC block of 〇codeword. The pre-EDC acknowledgment element 1105 is operative to generate an EDC result based on the data from the demodulator 11 。 5. The data buffer 1101 is used to store the Ecc block and the EDC result. The value generator 1107 generates PI and PO syndrome values based on the ?1 codeword and the PO codeword stored in the data buffer iioi. The symptom value memory 11〇9 is used to store the PI symptom value and the PO symptom value. The ECC decoder 111 is configured to perform error correction on the data of the gee block in the data buffer iioi according to the PI symptom value and the P0 symptom value in the syndrome 1109132 and according to the errata result. The PI symptom value and the p〇 symptom value in the symptom value memory 1109 are corrected. The EDC memory 1113 is used to buffer EDC results. The EDC Corrector 1115 corrects the EDC result based on the errata result from the ECC decoder mi.

在此例中,下一方向的ECC動作(即錯誤更正動作)係直接 讀取來自徵狀值記憶體1109。此外,徵狀值記憶體11〇9和EDC 兄憶體1113可整合至資料緩衝n 11Q1 ’此賴變化亦應在本發明 的範圍之内。 錯誤更正系統11〇〇的動作可簡述如下:解調器11〇3所解調 的資料被傳送至預先EDC確認元件1105以及資料緩衝器11〇1, 且EDC結果被儲存至資料緩蘭。接著纽夠解碼的資料被 儲存至資料緩衝器麗後,開始執行底下的動作:f料緩衝器!⑼ 儲存之EDC絲被讀取並儲存至EDC記憶體ni3。資料緩衝器 随内具有資料、PI、p〇碼字的ECC區塊被讀取,PI、p〇徵狀 值根據PI、PQ碼字被產生織儲存錢狀值記紐聰,且第 方向的ECC動作被施行。若在資料緩衝器11〇1内發現錯誤資 料’便更正錯誤,同時ECC解碼器llu内的徵狀值更正電路 '(未 繪示)更新相對應的徵狀值,同時EDC記憶體1113内的咖沾 果亦透過咖更正器1115被更新。接著,下-方向的ECC_ 係直接讀取雛值記顏聰的徵狀值,而不會讀取資料緩衝哭 11 ⑸ 4132 101—中的ECC區塊㈣新計算。兩個額的Ecc動作持續的交 仃直到達到預定動作次數或不再有錯誤資料存在為止。 第3圖繪示了根據本發明之第二實施例的錯誤更正系統 1200 ,塊圖。與錯誤更正系統酬比較起來,錯誤更正系統蘭 更包含-預先PIECC冑碼^㈣(如前所述,預先係指資料在進 二資料緩衝11之前便被麵,_贿接對來自解織副的資 ;斗行PI ECC動作並根據勘誤結果修正資料緩衝器u⑴内的 ECC結果。因此,錯誤更正系統議_作和錯誤更正系統謂 有。P伤不同。對錯誤更正系統丨篇而言,來自解調器謂的資 料除了上述的π件之外更被送到預先PI Ecc解碼器1201,且 EDC結果補存在資騎衝器mi巾。預先piEcc解碼器随 對儲存在資料緩衝n 11G1巾的資料騎預先PI Ecc動作,且預 先EDC確認元件聰直接對來自解調器11〇3的資料施行EDC 動作。當足夠解碼的資料被儲存至資料緩衝器11〇1後之詳細動作 與第2圖類似,且可由上述說明中輕易推得,故在此不再贅述。 第4圖繪示了根據本發明之第三實施例的錯誤更正系統13⑽ 的方塊圖。與錯誤更正系統1200比較起來,錯誤更正系統13〇〇 更包含位於預先EDC確認元件1105以及預先Pi ECC解碼器 丄2〇1之間的記憶體元件13〇1。因此,來自解調器11〇3之解調資 料的一部份列(row)被暫存於記憶體元件1301中。預先piECC解 碼器1201對記憶體元件1301中的ECc區塊施行一 PIECC動作。 12 而且,預S EDC確認元件更輕接至記憶體元件ΐ3〇ι以對 ECC區塊中的主資料施行EDC動作以產生edc結果。錯誤更正 系統130G之其他動作和錯誤更正系統12⑻相同,故在此不再費 述0 第5圖繪示了根據本發明之第四實施例的錯誤更正系統刚 的方塊圖。類似於錯誤更正系統12〇〇,錯誤更正系統·包含一 資料緩衝n liGi、-崎n _、―預先EDC確認元件11〇5以 及一預先PIECC解碼器12(U。然而,錯誤更正系統14〇〇更包含 一記憶體元件剛、- p〇徵狀值產生器剛、一 ECC解碼器 1405、一 π徵狀值產生器14〇7、一 pi徵狀值記憶體14〇9、一 EDc 圮憶體1411以及一 EDC更正器1413。解調器11〇3用以接收並解 調原始資料(Γawdata)以產生ECC區塊。預先EDC確認元件1105 用以對ECC區塊的主資料施行EDC動作以產生EDC結果。資料 緩衝器1101用以儲存ECC區塊和EDC結果。預先I>I ECC解碼 器1201用以直接對來自解調器11〇3的Ecc區塊之資料施行一預 先PI ECC動作,並根據預先pi ECC動作所產生之勘誤結果修正 貧料緩衝器1101中的EDC結果。記憶體元件1401用以暫時儲存 來自資料緩衝裔1101之ECC區塊的部份行(column)。PO徵狀值 產生器1403用以根據記憶體元件1401中的p〇碼字產生p〇徵狀 值。Π徵狀值記憶體1409用以儲存來自Π徵狀值產生器14〇7的 部份PI徵狀值。ECC解碼器1405根據PI徵狀值或PO徵狀值施 行錯誤更正。PI徵狀值產生器1407用以根據記憶體元件1401中 13 1334132 的ECC區塊產生PI徵狀值。EDC記憶體1411用以暫存肪c結 果。EDC更正器1413用以根據來自ECC解碼器剛的勘誤結果 更正EDC結果。 錯誤更正祕觸之動作可簡述如τ:來自解調器蘭的 解調資料被傳送至聽EDC確認元件_、預先piEcc解碼器 1201以及資料緩衝器11〇1。預先piECC解碼器12〇1直接對來自 解調器1103的ECC㈣之資料施行一預先n ECC動作,預先 EDC確認元件聰計算EDC結果,其中EDC結果被儲存至資 料緩衝器1UU ’且預先EDC確認元件11〇5根據預先ρι咖勘 誤結果更新EDC結果接著當足贿碼㈣料觀敍資料緩衝 器uoi後,開始執行底下的動作:EDC結果從資料緩衝器11〇1 中被讀出並儲存在EDC記憶體1411内。ECC區塊的一部份行被 暫存在記㈣元件剛巾,且POEO:動倾施行於記憶體元件 1401的行資料上以產生勘誤結果。接著,資料緩衝器u〇i中的錯 誤資料被更正且EDC更正器1413根據勘誤資料更新EDC記憶體 1411中的EDC結果。然後,PI徵狀值產生器14〇7自記憶體元件 1401讀取已經更正的行資料以產生η徵狀值,其中朽徵狀值被 儲存在Π徵狀值記憶體η〇9中,在所有的資料被P0 ECC動作 處理後,pi徵狀值從PI徵狀值記憶體1409令被讀取且PIECC^ 作被施行。 接著’記憶體元件1401以及資料緩衝器11〇1中的錯誤資料 14 1334132 被讀取且EDC記憶體中的EDC結果透“ EDC更正器1413被更 新。Π和P〇 ECC動作會持續交替執行直到執行次數達到一預定 數目或沒有錯誤資料存在為止。而且,錯誤更正系統14〇〇可更包 s δ己憶體元件,其位於預先EDC確認元件1105以及預先pi ECC解碼器1201之間。 第6圖至第8圖所示的實施例與第3圖至第5圖的實施例相 同’其差異在於第3圖至第5贿示的EDC確認元件係為預先 EDC確5忍元件’也就是EDC確認元件係位於資料緩衝器之前,但 在第6圖至第8圖所示的實施例中,EDC確認元件係位於資料緩 衝器之後。因此,第6圖至第8圖所示的實施例與第3圖至第5 圖的實施例在動作上有所不同。 第6圖繪示了根據本發明之第五實施例的錯誤更正系統15〇〇 的方塊圖。請參考第3圖和第6 ,第3圖和第6圖之結構相類 似,但錯誤更正系統1500具有位於資料緩衝器11〇1之後的非線 性EDC確認元件ι5〇1,而不是位於資料緩衝器11〇1之前的預先 EDC確認元件11〇5,因此錯誤更正系統12〇〇和錯誤更正系統 1500具有不同的動作。 對錯誤更正系統1500而言,解調器11〇3所解調的資料被傳 送至資料緩衝器1101以及預先Π ECC解碼器12〇1。然後預先 PI ECC解碼器12〇1直接對來自解調器11〇3的資料施行pi ecc 15 1334132 動作。接著當足夠解碼的資料被儲存至資料緩衝器11〇1後,開始 執行底下的動作:資料緩衝器1101中包含資料、以及ρι/ρ〇碼字 的ECC區塊被讀取,同時PI' p〇徵狀值根據π、p〇碼字被產生 並被儲存至徵狀值記缝11Q9。_g_第—方向的Ecc動作被施行。 與ECC區塊從資料緩衝器1101被讀取的同時,非線性EDC確認 凡件1501對ECC區塊施行一非線性EDC動作以產生一 EDC結 果且EDC結果被儲存在EDC記憶體1113中。若發覺資料缓衝 。中有錯誤> 料便予以更正,同時相對應的徵狀值透過ECC 解焉器⑴1中的一徵狀值更正電路(未緣示)被更新,且EDC記 隱體1113中的edc結果透過EDC更正器1115被更新。接著, 下=方向的ECC動作(此例中為p〇)係直接讀取儲存在徵狀值記 ,體11(39中的徵狀值,而不是根據資料緩衝器1101中的資料計 算徵狀值。兩方向的ECC動作會_交行·執行次數達到 一預定數目或沒有錯誤#料存在為止。 須注意的是,關於線性和非線性EDC動作的詳細描述,可參 R f國專利申錢第11/53128Q的專利,此專利制相同申請人以 及相同發明人所申請。 ^ 圖3示了根據本發明之第六實施例的錯誤更正系統1600 的方塊圖。箪4 isw — 圖和第7圖之結構相類似,但錯誤更正系統1600 位於貞料緩啦11Q1之後的非雜EDC確認元件臟,而 讀於資料緩衝器削1之前的預先EDC確認元件11〇5,因此 16 1334132 錯誤更正系統1300和錯誤更正系統1600具有不同的動作。解調 器1103所解調的資料被儲存至記憶體元件1203。記憶體元件12〇3 用以暫存ECC區塊的一部份列,然後預先pi ECC解碼器π⑴ 用以對記憶體元件1203中的ECC區塊施行PI ECC動作以產生更 正後的ECC區塊。第7 ®所示的錯誤更正系統刪接下來的動 作和第8圖所示的錯誤更正系統丨類似,故在此不再贅述。與 第1圖所示的習知技術比較起來,第7圖所示的錯誤更正系統膽 ^包含-預先PIECC解碼H聰以及記憶體元件咖。而且, 第7圖所7F的錯誤更正錢獅巾的EDC顧树係為非線性 EDC確認元件而不是線性EDC確認元件。因此,錯誤更正系統 觸因為預— Ecc解碼器具有較佳之效能,並可因為記 隐體;τ:件1203減少頻寬。而且,非線性EDC確認元件醜的使 用亦可協助克服幀鎖定同步偏移的問題。 第8圖緣不了根據本發明之第七實施例的錯誤更正系統17〇〇 的方塊圖。請參考第5圖和第8目’第5圖和第8圖之結構相類 似仁錯誤更正系統17〇〇具有位於資料緩衝器U⑴之後的非線 性EDC確認元件17〇1,而不是位於資料緩衝器腿之前的預先 確^元件1105,因此錯誤更正系统测和錯誤更正系統 1700具有不同的動作。 ,對錯誤更正系統17⑻而言,解繼歷所解調的資料被傳 L至貝料緩衝益11〇1以及預先n ecc解碼器削。然後預先 17 U34132 H ECC解碼器1201直接對來自解調器1103的資料施行PI ECC 動作。接著當足夠解碼的資料被儲存至資料緩衝器11〇1後,開始 執行底下的動作:ECC區塊自資料緩衝器ιι〇1被讀取,且非線 性EDC確認元件1701對ECC區塊施行非線性EDC動作以產生 —EDC結果’此EDC結果被儲存至EDC記憶體1411中。 資料緩衝器1101中的ECC區塊之部份行被讀取並暫存至記 憶體兀件1401 ’且一 p〇 ECC動作被施行在記憶體元件14〇1的行 資料中以產生勘誤結果。然後EDC記憶體1411中的EDC結果透 過EDC更正器1413根據勘誤結果被更新。然後,]p〗徵狀值產生 器自記憶體元件1401讀取被更正的行資料以產生PI徵狀值,且 此PI徵狀值被儲存在PI徵狀值記憶體14〇9中,在所有行資料皆. 被PO ECC動作處理後,PI徵狀值自ρι徵狀值記憶體14〇9被讀 取且PI ECC動作被執行。接著,記憶體元件14〇1以及資料緩衝 器1101中的錯誤資料被更正且EDC記憶體1411中的EDC結果 透過EDC更正器1413被相對應的更新。 第9〜12圖繪示了根據本發明之其他實施例,其亦具有資料緩 衝器之後的EDC確認元件。第9圖繪示了根據本發明之第八實施 例的錯誤更正系統1800。如第9圖所示,錯誤更正系統1800包含 一資料缓衝器1801、一解調器1803、一預先PI徵狀值產生器 1805、一 PI徵狀值記憶體1807、一 p〇徵狀值產生器18〇9、— PO徵狀值記憶體1811、一 ECC解碼器1813、一非線性EDC確 18 1334132 認元件1815、一 EDC記憶體1817以及一 EDC更正器1819。解 調器1803用以接收並解調來自光碟的原始資料以產生包含資料、 PI碼字以及PO碼字的的ECC區塊。資料緩衝器1801用以儲存 ECC區塊。預先pi徵狀值產生器1805用以根據ECC區塊的PI 碼字產生Π徵狀值。pi徵狀值記憶體18〇7用以儲存pi徵狀值。 PO徵狀值產生器1805用以根據ECC區塊的PO碼字產生p〇徵 狀值。非線性EDC確認元件1815用以對ECC區塊的主資料施行 非線性EDC動作以產生EDC結果。 PO徵狀值記憶體1811用以儲存P〇徵狀值。ECC解碼器1813 根據PI徵狀值§己憶體18〇7中的pi徵狀值對gee區塊施行pi ECC 動作以產生;PI ECC勘誤結果,以及根據ρ〇徵狀值記憶體an 中的ΡΟ徵狀值對ECC區塊施行POIECC動作以產生ρ〇 ECC勘 誤結果。EDC記憶體18Π用以暫存EDC結果。EDC更正器1819 根據來自ECC解碼器1813的Π ECC勘誤結果或p〇 Ecc勘誤 結果更正EDC結果。 錯誤更正系統1800之動作可簡述如下:來自解調器聰的 貝料被傳送至預先PI徵狀值產生器18〇5以及資料緩衝器18⑴, 且PI徵狀值被儲存在PI徵狀值記憶體18〇7中。接著當足夠解碼 的資料被儲存至資料緩衝器薩後,開始執行底下^作。咖 解碼器1813根據Η徵狀值記憶體_中的η徵狀值對資料緩衝 器刪⑽資料施行一 PI ECC動作,同時ECC解碼器觀内 19 1334132 一徵狀值更正電路相對應的更新PI徵狀值記憶體18〇7中的徵狀 值,且同時EDC更正器1819相對應的更新EDC記憶體1817中 的EDC結果。 而且’ECC區塊自資料缓衝器18〇1被讀取,且p〇徵狀值產 生器1809產生P0徵狀值,其被儲存在p〇徵狀值記憶體1811内, 且ECC解碼器1813和非線性EDC確認元件1815分別根據徵狀 值結果施行POECC動作以及對資料緩衝器18〇1中的主資料施行 非線性EDC動作,其中非線性EDC動作的結果被儲存在EDc記 憶體1817中。ECC解碼器1813更正資料緩衝器臟中的錯誤資 料,同時ECC解碼器1813内-徵狀值更正電路相對應的更新徵 狀值記憶體1807中的徵狀值,且同時EDC更正器1819相對應的 更新EDC記憶體1817中的EDC結果。 下-方向的ECC動作係直接讀取儲存在徵狀值記憶體則 中的徵狀值,而不是根據資料緩衝器18〇1 _的資料計算徵狀值。 PI和PO ECC動作會持、續交替執行直到執行次數達到一預定數目 或沒有錯誤資料存在為止。 PI徵狀值記憶體1807可被整合至資料緩衝器18〇1,如第 圖所示。第1〇圖繪示了根據本發明之第九實施例的錯誤更正系统 1900的方塊圖。除了 PI徵狀值記憶體聰外,第1〇圖所示的錯 誤更正系統19GG與第9圖緣示的錯誤更正系統觸大致相同, 1334132 因此錯誤更正系統測之^件的連接方式以及動作會和錯誤更正 系統1800不同。 錯誤更正祕1_之動作可簡述如下。來自解顧18〇3的 解調資料鋪送至預先H徵狀值產W 以及f料緩衝器 腿,且PI徵狀值被儲存在資料緩衝器18〇1中。接著當足夠解 碼的資料#存至資料緩衝器18〇1後,開始執行底下的動作:Ecc 解碼器1813根據儲存在資料緩衝器18〇1内的ρι徵狀值施行一丹 ECC動作並更正⑽緩衝器聰内的資料,同時ecc解碼器聰 内的徵狀值更正電路(未繪示)更新相對應的徵狀值,同時edc 記憶體1817内的EDC結果亦透過EDC更正器1819被更新。接 著ECC區塊從資料緩衝器18〇1被讀出且?〇徵狀值產生器18〇9 艮據ECC區塊纽PQ徵狀值,Pq徵紐被儲存在pQ徵狀值記 憶體1811内。在P〇徵狀值產生器18〇9計算p〇徵狀值後,poEcc 動作被執行。ECC解碼器1813和非線性EDC確認元件1815分別 根據徵狀值結果施行POECC動作以及對資料緩衝器18〇1中的資 料施行非線性EDC動作,其中非線性EDC動作的結果被儲存在 EDC記憶體1817中。ECC解碼器1813更正資料緩衝器1801中 的錯誤資料,同時ECC解碼器1813内一徵狀值更正電路相對應 的更新PO徵狀值記憶體1811中的p〇徵狀值以及資料緩衝器 1801中的PI徵狀值,且同時拉^更正器1819相對應的更新EDC 記憶體1817中的EDC結果。 下一方向的ECC動作係直接讀取儲存在P0徵狀值記憶體 21 :Γ或資料緩衝器1801中的徵狀值,而不是根據資料緩_ 中的雜計算錄值。ΡΙ和PQ ECC動作會持續交替執行直 執仃次數_ -預定數目或沒有錯誤倾存在為止。 預先PI徵狀值產生器1805可被整合至預SPI Ecc解碼器 如第11圖所不。帛11 _示了根據本發明之第十實施例的 曰誤更正系統2_的方塊《。在此實施例中,來自解調器18〇3 的解調資料被傳送至預先π ECC解碼器2⑻丨以及資料緩衝器 180卜且預先PI ECC解碼器麗中的徵狀值產生器產生ρι徵狀 值並儲存在PI徵狀值記憶體1807之内。預先PI Ecc解碼器2〇〇1 直接對來自解調器1803的資料施行PIECC動作,且預*Hecc 解碼器2GG1中的徵狀值更正電路相對應的修正ρι徵狀值記憶體 18〇7内的PI徵狀值。In this example, the ECC action in the next direction (i.e., the error correction action) is directly read from the syndrome value memory 1109. In addition, the symptom value memory 11〇9 and the EDC brother memory element 1113 can be integrated into the data buffer n 11Q1 '. This variation should also be within the scope of the present invention. The operation of the error correction system 11A can be briefly described as follows: The data demodulated by the demodulator 11〇3 is transferred to the pre-EDC confirmation element 1105 and the data buffer 11〇1, and the EDC result is stored to the data buffer. Then the data decoded by Newton is stored in the data buffer, and the next action is started: f buffer! (9) The stored EDC wire is read and stored in the EDC memory ni3. The data buffer is read with the ECC block of the data, PI, and p〇 codewords. The PI and p〇 values are generated according to the PI and PQ codewords. The ECC action is performed. If the error data is found in the data buffer 11〇1, the error is corrected, and the syndrome correction circuit (not shown) in the ECC decoder 11u updates the corresponding symptom value, and the EDC memory 1113 The coffee-smelling fruit was also updated through the coffee correction device 1115. Then, the ECC_ in the down-direction directly reads the syndrome value of the young value, but does not read the new calculation of the ECC block (4) in the data buffer cry 11 (5) 4132 101. The two Ecc actions continue to intersect until the predetermined number of actions is reached or no more error data exists. Figure 3 is a block diagram of an error correction system 1200 in accordance with a second embodiment of the present invention. Compared with the error correction system remuneration, the error correction system blue contains more - the pre-PIECC code ^ (4) (as mentioned above, the pre-referential data is before the data buffer 11 is entered, the bribe pair is from the de-weaving pair The action of the PI ECC is performed and the ECC result in the data buffer u(1) is corrected based on the result of the errata. Therefore, the error correction system is different from the error correction system. The P injury is different. The data from the demodulator is sent to the pre-PI Ecc decoder 1201 in addition to the above-mentioned π pieces, and the EDC result is added to the rider's mi towel. The pre-piEcc decoder is stored in the data buffer n 11G1 towel. The data rides the pre-PI Ecc action, and the pre-EDC confirms that the component Cong directly performs the EDC action on the data from the demodulator 11〇3. The detailed action and the second action after the sufficiently decoded data is stored in the data buffer 11〇1 The figure is similar and can be easily derived from the above description, so it will not be described again here. Fig. 4 is a block diagram showing the error correction system 13 (10) according to the third embodiment of the present invention. Compared with the error correction system 1200 The error correction system 13 further includes a memory element 13〇1 located between the pre-EDC confirmation component 1105 and the pre-Pi ECC decoder 丄2〇1. Therefore, a portion of the demodulated data from the demodulator 11〇3 The row is temporarily stored in the memory component 1301. The pre-piECC decoder 1201 performs a PIECC operation on the ECc block in the memory component 1301. 12 Moreover, the pre-S EDC confirms that the component is more lightly connected to the memory component. Ϊ́3〇ι performs an EDC action on the master data in the ECC block to generate an edc result. The other actions of the error correction system 130G are the same as the error correction system 12(8), so no further description is made here. FIG. 5 depicts The block diagram of the error correction system of the fourth embodiment of the invention is similar to the error correction system 12, the error correction system includes a data buffer n liGi, -saki n_, "pre-EDC confirmation component 11〇5, and one The pre-PIECC decoder 12 (U. However, the error correction system 14 further includes a memory element just, a p〇 sign generator, an ECC decoder 1405, and a π sign generator 14〇7 , a pi symptom value memory 14〇9 An EDC memory 1411 and an EDC correction unit 1413. The demodulator 11〇3 is configured to receive and demodulate the raw data (Γawdata) to generate an ECC block. The pre-EDC confirmation component 1105 is used to master the ECC block. The data is subjected to an EDC action to generate an EDC result. The data buffer 1101 is used to store the ECC block and the EDC result. The I > I ECC decoder 1201 is used to directly perform the data of the Ecc block from the demodulator 11〇3. The PI ECC action is performed in advance, and the EDC result in the lean buffer 1101 is corrected based on the errata result generated by the pre-pi ECC action. The memory component 1401 is used to temporarily store a portion of the column from the ECC block of the data buffer 1101. The PO symptom value generator 1403 is configured to generate a p〇 symptom value based on the p〇 code word in the memory element 1401. The syndrome value memory 1409 is used to store a portion of the PI symptom value from the syndrome value generator 14A. The ECC decoder 1405 performs error correction based on the PI syndrome value or the PO symptom value. The PI syndrome generator 1407 is configured to generate a PI syndrome value based on the ECC block of 13 1334132 in the memory component 1401. The EDC memory 1411 is used to temporarily store the fat c results. The EDC Corrector 1413 is used to correct the EDC result based on the errata result from the ECC decoder. The error correction action can be briefly described as τ: the demodulated data from the demodulator blue is transmitted to the listening EDC confirming element_, the pre-piEcc decoder 1201, and the data buffer 11〇1. The pre-piECC decoder 12〇1 directly performs a pre-n ECC action on the ECC(4) data from the demodulator 1103, and pre-EDC confirms that the component Cong calculates the EDC result, wherein the EDC result is stored in the data buffer 1UU' and the EDC confirmation component is pre-EDC. 11〇5 Update the EDC result according to the result of the ρι Café errata and then start the execution of the underlying action after the cipher code (4): The EDC result is read from the data buffer 11〇1 and stored in the EDC. Inside the memory 1411. A portion of the ECC block is temporarily stored in the (4) component tape, and the POEO: wave is applied to the line data of the memory component 1401 to produce an errata result. Next, the error data in the data buffer u〇i is corrected and the EDC corrector 1413 updates the EDC result in the EDC memory 1411 based on the errata data. Then, the PI symptom generator 14〇7 reads the corrected line data from the memory element 1401 to generate an η symptom value, wherein the falsification value is stored in the Π 值 value memory η〇9, After all the data were processed by the P0 ECC action, the pi symptom value was read from the PI symptom value memory 1409 and the PIECC^ was executed. Then the 'error memory element 1401 and the error data 14 1334132 in the data buffer 11〇1 are read and the EDC result in the EDC memory is updated. The EDC correction unit 1413 is updated. The Π and P〇ECC actions continue to alternate until The number of executions reaches a predetermined number or no error data exists. Moreover, the error correction system 14 may further include an s δ hex element, which is located between the pre-EDC acknowledgment element 1105 and the pre-pi ECC decoder 1201. The embodiment shown in the figure to Fig. 8 is the same as the embodiment of Figs. 3 to 5 'the difference is that the EDC confirmation component of the 3rd to 5th bribes is a pre-EDC confirmation 5 tolerance element', that is, EDC The confirmation component is located before the data buffer, but in the embodiment shown in Figures 6 to 8, the EDC confirmation component is located behind the data buffer. Therefore, the embodiments shown in Figures 6 to 8 are The embodiments of Figs. 3 to 5 differ in operation. Fig. 6 is a block diagram showing an error correction system 15A according to a fifth embodiment of the present invention. Please refer to Figs. 3 and 6. The structure of Figure 3 and Figure 6 is similar. The error correction system 1500 has a non-linear EDC confirmation component ι5〇1 located after the data buffer 11〇1, instead of the pre-EDC confirmation component 11〇5 located before the data buffer 11〇1, so the error correction system 12〇〇 The error correction system 1500 has different actions. For the error correction system 1500, the data demodulated by the demodulator 11〇3 is transferred to the data buffer 1101 and the pre-Π ECC decoder 12〇1, and then pre-PI ECC decoding. The device 12〇1 directly performs the pi ecc 15 1334132 action on the data from the demodulator 11〇3. Then, after the sufficiently decoded data is stored in the data buffer 11〇1, the bottom action is started: the data buffer 1101 The ECC block containing the data and the ρι/ρ〇 codeword is read, and the PI'p〇 symptom value is generated according to the π, p〇 codeword and stored to the symptom value slot 11Q9. _g_第The Ecc action of the direction is performed. While the ECC block is being read from the data buffer 1101, the non-linear EDC confirms that the piece 1501 performs a non-linear EDC action on the ECC block to generate an EDC result and the EDC result is stored in EDC memory 11 13. If the data buffer is found, there is an error > it is corrected, and the corresponding symptom value is updated by a symptom correction circuit (not shown) in the ECC decoder (1)1, and EDC The result of edc in the hidden body 1113 is updated by the EDC corrector 1115. Then, the ECC action of the lower = direction (in this case, p〇) is directly read and stored in the syndrome value, the sign of the body 11 (39) Instead of calculating the syndrome value based on the data in the data buffer 1101, the value is calculated. The ECC action in both directions will be the number of executions or the number of executions reaches a predetermined number or no error # material exists. It should be noted that a detailed description of the linear and non-linear EDC actions can be found in the patent of the patent application No. 11/53128Q, which is filed by the same applicant and the same inventor. Figure 3 shows a block diagram of an error correction system 1600 in accordance with a sixth embodiment of the present invention.箪4 isw — The structure of the figure is similar to that of Figure 7, but the error correction system 1600 is located in the non-heterogeneous EDC confirmation component after the buffer 11Q1, and the pre-EDC confirmation component 11 before reading the data buffer is cut. 5, therefore 16 1334132 error correction system 1300 and error correction system 1600 have different actions. The data demodulated by the demodulator 1103 is stored to the memory element 1203. The memory component 12〇3 is used to temporarily store a part of the column of the ECC block, and then pre-pi ECC decoder π(1) is used to perform a PI ECC action on the ECC block in the memory component 1203 to generate a corrected ECC block. . The error correction system shown in Figure 7 is similar to the error correction system shown in Figure 8, so it will not be repeated here. In comparison with the conventional technique shown in Fig. 1, the error correction system shown in Fig. 7 includes - pre-PIECC decoding H Cong and memory component coffee. Moreover, the error correction of 7F in Fig. 7 is that the EDC Gushu of Qianshi towel is a nonlinear EDC confirmation component instead of a linear EDC confirmation component. Therefore, the error correction system is because the pre-Ecc decoder has better performance and can reduce the bandwidth because of the hidden body; τ: member 1203. Moreover, the use of non-linear EDC acknowledgment components can also help overcome the problem of frame lock sync offset. Fig. 8 is a block diagram of the error correction system 17A according to the seventh embodiment of the present invention. Please refer to Figure 5 and Figure 8 for the structure of Figure 5 and Figure 8. The error correction system 17 has a nonlinear EDC confirmation component 17〇1 located after the data buffer U(1) instead of the data buffer. The pre-determination element 1105 before the leg, thus the error correction system and error correction system 1700 has a different action. For the error correction system 17(8), the data demodulated by the solution is transmitted to the bedding buffer benefit 11〇1 and the pre-nec decoder. The PI ECC action is then performed directly on the data from the demodulator 1103 in advance by the 17 U34132 H ECC decoder 1201. Then, after the sufficiently decoded data is stored in the data buffer 11〇1, the bottom action is started: the ECC block is read from the data buffer ιι〇1, and the non-linear EDC confirmation component 1701 performs the non-ECC block. Linear EDC action to generate - EDC results 'This EDC result is stored in EDC memory 1411. Portions of the ECC block in the data buffer 1101 are read and temporarily stored in the memory element 1401' and a p〇 ECC action is performed in the line data of the memory element 14〇1 to produce an errata result. The EDC result in the EDC memory 1411 is then updated by the EDC Corrector 1413 based on the errata result. Then, the p-value generator generates the corrected line data from the memory element 1401 to generate a PI symptom value, and the PI symptom value is stored in the PI symptom value memory 14〇9, All line data. After being processed by the PO ECC action, the PI symptom value is read from the ρι symptom value memory 14〇9 and the PI ECC action is performed. Next, the error data in the memory element 14〇1 and the data buffer 1101 is corrected and the EDC result in the EDC memory 1411 is correspondingly updated by the EDC corrector 1413. Figures 9 through 12 illustrate other embodiments of the present invention that also have an EDC validation component after the data buffer. Figure 9 illustrates an error correction system 1800 in accordance with an eighth embodiment of the present invention. As shown in FIG. 9, the error correction system 1800 includes a data buffer 1801, a demodulator 1803, a pre-PI symptom generator 1805, a PI symptom memory 1807, and a p-value. The generator 18〇9, the PO symptom value memory 1811, an ECC decoder 1813, a non-linear EDC confirmation 18 1334132 recognition component 1815, an EDC memory 1817, and an EDC correction device 1819. The demodulator 1803 is configured to receive and demodulate the original data from the optical disc to generate an ECC block containing the data, the PI codeword, and the PO codeword. The data buffer 1801 is used to store ECC blocks. The pre-pi syndrome generator 1805 is configured to generate a syndrome value from the PI codeword of the ECC block. The pi symptom value memory 18〇7 is used to store the pi symptom value. The PO syndrome generator 1805 is configured to generate a p〇 eigenvalue based on the PO codeword of the ECC block. The non-linear EDC validation component 1815 is operative to perform a non-linear EDC action on the master data of the ECC block to produce an EDC result. The PO symptom value memory 1811 is used to store the P〇 symptom value. The ECC decoder 1813 performs a pi ECC action on the gee block according to the pi symptom value in the PI symptom value § 忆 体 18〇7; the PI ECC errata result, and the memory in the memory ang according to the 〇 〇 〇 value The ΡΟ 状 value performs a POIECC action on the ECC block to produce a ρ 〇 ECC errata result. EDC memory 18 is used to temporarily store EDC results. The EDC Corrector 1819 corrects the EDC result based on the Π ECC errata result from the ECC decoder 1813 or the p〇 Ecc errata result. The action of the error correction system 1800 can be briefly described as follows: the bunker from the demodulator is sent to the pre-PI syndrome generator 18〇5 and the data buffer 18(1), and the PI symptom value is stored in the PI symptom value. The memory is 18〇7. Then, when enough decoded data is stored in the data buffer, the next step is executed. The coffee decoder 1813 performs a PI ECC action on the data buffer delete (10) data according to the η symptom value in the syndrome value memory__, and the EPIC decoder view 19 1334132 a symptom value correction circuit corresponding update PI The syndrome value in the memory value 18〇7, and at the same time the EDC result in the EDC memory 1817 corresponding to the EDC corrector 1819. Moreover, the 'ECC block is read from the data buffer 18〇1, and the p〇 symptom generator 1809 generates a P0 symptom value, which is stored in the p〇 symptom value memory 1811, and the ECC decoder 1813 and the nonlinear EDC confirmation component 1815 perform a POECC action according to the result of the syndrome value and perform a nonlinear EDC action on the master data in the data buffer 18〇1, wherein the result of the nonlinear EDC action is stored in the Edc memory 1817. . The ECC decoder 1813 corrects the error data in the data buffer dirty, while the ECC decoder 1813 updates the syndrome value in the symptom value memory 1807 corresponding to the syndrome value correcting circuit, and at the same time the EDC corrector 1819 corresponds. Update the EDC results in EDC memory 1817. The downward-direction ECC action directly reads the symptom value stored in the symptom value memory instead of calculating the syndrome value based on the data buffer 18〇1 _. The PI and PO ECC actions are held alternately until the number of executions reaches a predetermined number or no error data exists. The PI symptom value memory 1807 can be integrated into the data buffer 18〇1 as shown in the figure. Figure 1 is a block diagram showing an error correction system 1900 in accordance with a ninth embodiment of the present invention. In addition to the PI symptom value memory, the error correction system 19GG shown in Figure 1 is roughly the same as the error correction system shown in Figure 9. 1334132 Therefore, the error correction system connection method and action will be corrected. It is different from the error correction system 1800. The error correction secret 1_ action can be briefly described as follows. The demodulated data from the resolution 18〇3 is spread to the pre-H syndrome value and the f-buffer leg, and the PI symptom value is stored in the data buffer 18〇1. Then, after the enough decoded data # is stored in the data buffer 18〇1, the bottom action is started: the Ecc decoder 1813 performs a Dan ECC action according to the ρι symptom stored in the data buffer 18〇1 and corrects (10) The data in the buffer, and the syndrome correction circuit (not shown) in the ECC decoder update the corresponding symptom value, and the EDC result in the edc memory 1817 is also updated by the EDC corrector 1819. Then the ECC block is read from the data buffer 18〇1 and? The syndrome value generator 18〇9 is stored in the pQ symptom value memory 1811 according to the ECC block Newton PQ symptom value. After the P〇 symptom generator 18〇9 calculates the p〇 symptom value, the poEcc action is performed. The ECC decoder 1813 and the non-linear EDC confirming component 1815 perform a POECC action according to the result of the syndrome value and perform a nonlinear EDC action on the data in the data buffer 18〇1, wherein the result of the nonlinear EDC action is stored in the EDC memory. In 1817. The ECC decoder 1813 corrects the error data in the data buffer 1801, and simultaneously updates the p〇 symptom value in the PO symptom value memory 1811 corresponding to a syndrome correction circuit in the ECC decoder 1813 and the data buffer 1801. The PI symptom value, and at the same time, the EDC result in the updated EDC memory 1817 corresponding to the correction device 1819. The ECC action in the next direction directly reads the syndrome value stored in the P0 syndrome memory 21:Γ or the data buffer 1801, instead of the hash value in the data buffer _. The ΡΙ and PQ ECC actions will continue to alternately execute the number of _ _ - the predetermined number or no error dump. The pre-PI syndrome generator 1805 can be integrated into the pre-SPI Ecc decoder as shown in FIG.帛11_ shows the block of the corruption correction system 2_ according to the tenth embodiment of the present invention. In this embodiment, the demodulated data from the demodulator 18〇3 is transmitted to the pre-π ECC decoder 2(8) and the data buffer 180, and the syndrome generator in the pre-PI ECC decoder generates the ρι sign. The value is stored in the PI symptom value memory 1807. The pre-PI Ecc decoder 2〇〇1 directly performs the PIECC action on the data from the demodulator 1803, and the correction value corresponding to the syndrome value correction circuit in the pre-Hecc decoder 2GG1 is in the memory value 18〇7 PI symptom value.

接著當足夠解碼的資料被儲存至資料緩衝器18〇1後,開始執 行底下的動作。ECC區塊從資料緩衝器18〇1被讀取,p〇徵狀值 產生器1809產生PO徵狀值並儲存在P〇徵狀值1811中。Ecc解 碼器1813以及非線性EDC確認元件1815分別在資料緩衝器ι8〇ι 中的資料上根據徵狀值結果施行第一方向的Ecc動作以及非線性 EDC動作。其中非線性EDC動作的結果被儲存在EDC記憶體1817 中。然後’ECC解碼器1813更正資料緩衝器中的錯誤資料, ECC解碼器1813中的徵狀值更正電路相對應的更正?1徵狀值記 憶體1807和PO徵狀值記憶體1811中的PI和p〇徵狀值,EDC 22 記憶體1817内的EDC結果亦透過EDC更正器1819被更新。下 方向的ECC動作係直接讀取儲存在徵狀值記憶體18〇7中的徵 狀值,而不是根據資料緩衝器職中的資料計算徵狀值。pi和 P〇 ECC動作會持續交替執行直到執行次數達到一預定數目或沒 有錯誤資料存在為止。 第11圖中的PI徵狀值記憶體1807可被整合至資料緩衝器 U07,如第12圖所示。第12圖繪示了根據本發明之第十一實施 例的錯誤更正系統21GG的方制。在此實施例中,ρι徵狀值被儲 存在資料緩衝胃麵巾而不是ρι徵錄域體卜其他動作 與錯誤更正系統2000的動作相同,故在此不再贅述。 第13圖至第15圖緣示了本發明之其他實施例的方塊圖。這 些只%例在資料緩衝器前具有預先EDC確認元件,徵狀值產生器 或疋-預先ECC元件,且在資料緩衝旨之後具有相_元件。 第13圖繪示了根據本發明之第十二實施例的錯誤更正系統 2200的方塊圖。如第13圖所示,錯誤更正系統22〇〇包含一資料 緩衝器220卜-解調器2203、-預先EDC確認元件22〇5、一預 先Π徵狀值產生器2207、一 PI徵狀值記憶體22的、一 p〇徵狀 值產生态2211、一 PO徵狀值記憶體2213、一 ECC解碼器、 > EDC記憶體2217、以及一 ;eDC更正器2219。解調器2213用 以接收應解調來自辆的原始資料以產生包含資料、H碼字以及 23 1334132 P0碼字的ECC區塊。預先EDC確認元件22〇5肖以施行一 EDC 動作在來自解調H 2203的主資料上以產生―EDC結果。資料緩 衝器2203用以儲存ECC區塊和EDC結果。預先ρι徵狀值產生器 2207用以根據來自解調器2201的ECC區塊產生PI徵狀值。PO徵 狀值記憶體2209用以儲存來自p〇徵狀值產生器則的阳徵狀 值。ECC解碼器2215根據PI丨P0徵狀值執行ECC動作以產生 勘誤結果。EDC記憶體2217用以暫存EDC結果。EDC更正器2219 用以根據來自ECC解碼器2215的勘誤結果更正EDC結果。 錯誤更正系'统2200的動作可如下所述。來自解調器2203的 解調資料被傳送到Η徵狀值產生器2207、預先EDC確認元件22〇5 以及資料緩衝H迦,其巾PI徵狀健齡在PI錄值記憶體 2209内且EDC結果被儲存在資料緩衝器22〇1 0。接著當足夠解 碼的資料被儲存至資料緩衝器2201後,開始執行底下的動作。 資料緩衝器22G1 _ EDC絲被讀取讀存在EDC記憶體 2217内。ECC解碼器2215根據儲存在pi擇支狀值記憶體22〇9内 的PI徵狀值施行一方向的ECC動作,同時ECC解碼器2215内 的徵狀值更正電路(未繪示)更新PI徵狀值記憶體22〇9*p〇徵 狀值記憶體2213内的PI和p〇徵狀值,同時EDC記憶體内 的EDC結果亦透過EDC更正器2219被更新。資料緩衝器謹 中的ECC區塊被讀取且p〇徵狀值產生器2211計算p〇徵狀值並 儲存在P0徵狀值圮憶體2213内。當一方向的動作被完成 24 1334132 後,下一方向的ECC動作係直接讀取儲存在徵狀值記憶體22〇9 和2211中的徵狀值’而不是根據資料緩衝器22〇1中的資料計算 徵狀值。Μ向的ECC動作會浦交魏行直到執行次數達到一 預定數目或沒有錯誤資料存在為止。 第I4圖繪不了根據本發明之第十三實關的錯誤更正系統 7〇〇的方塊圖。如第14圖所示,錯誤更正系統包含_資料緩 衝器50卜一解調器503、一預先EDC確認元件6〇〗、一預先ρι 徵狀值產生器507、一 PI徵狀值記憶體505、- P〇徵狀值產生 器509、-徵狀值記憶體5U、一 ECC解媽器513…edc記憶 體605、以及- EDC更正器603。ECC解碼器513根據ρι或p〇 徵狀值執行ECC _以產生祕結果。EDC記鐘④巧以暫存 EDC (果。EDC更正器603用以根據來自Ecc解碼器513的勘 誤結果更正EDC結果。 錯誤更正系統700的動作可如下所述。來自解調器5〇3的解 調資料被傳送到預先Η徵狀值產生器5〇7、預先咖確認元件 601以及資料緩衝器通,其中H徵狀值被儲存在ρι徵狀值記憶 體505内且EDC結果被儲存在資料缓衝器501内。接著當足夠^ 瑪的資料被儲存至㈣緩衝器麗後,開始執行底下的動作。 資料緩衝器5〇1内的EDC結果被讀取且儲存在咖纪情體 605内。ECC解碼器513根據儲存在資料緩衝$ 5〇1内的^狀 25 1334132 值施行-方⑽ECC動作’ _ECC解碼器5i3 _徵狀值更 正電路(未繪示)更新徵狀值記憶體5U内的PI_徵狀值,同 時咖記憶體6〇5内的咖結果亦透過咖更正器爾更新。 貧料緩衝ϋ對的ECC區塊_取且ρ〇徵狀健生器,計 异ρ〇徵狀值並儲存徵狀值記憶體511内。當―方向的[動作 被完成後’下-方㈣ECC_係直輯_存在錄值記憶體 511中的徵狀值’而不是根據資料緩衝器5〇1中的資料計算徵狀 值。兩方⑽ECC動作會_㈣執行朗執行讀達到一預定 數目或沒有錯誤資料存在為止。 第15圖繪示了根據本發明之第十四實施例的錯誤更正系統 2300的方塊圖。與第13圖中所示的錯誤更正系統謂比較起來, 錯誤更正纽屬更具有-預“ECC解碼器道,且預先朽 徵狀值產生器22G7被整合至預先PIECC解碼器纖中。因此錯 誤更正系統2200和2300的連接關係和動作有所不@。 曰 錯誤更正系統2300的動作可如下所示:來自解調器22〇3的 解調資料被傳賴預先則CC解碼器咖、預先咖確認元件 2205以及資料緩衝器22(H ’其中Pm狀值被儲存在即文狀值記 憶體2209内且EDC結果被儲存在資料緩衝器22〇1内。接著當足 夠解碼的資料被儲存至資料緩衝器22〇1後,開始執行底下的動 作。資料緩衝器通_ EDC結果被讀取並被儲存在mc記憶 邊⑵7中’且PO徵狀值產生如計算p〇徵狀值並儲存在 26 1334132 徵狀值記憶體中。ECC解碼器2215根據P0徵狀值施行一方向的 ECC動作,同時ECC解碼器2215内的徵狀值更正電路(未繪示) 更新P0徵狀值記憶體2213内相對應的p〇徵狀值,同時EDC記 憶體2217内的EDC結果亦透過EDC更正器2219被更新。 接著ECC解碼器2215根據PI徵狀值施行另一方向的ECC 動作,同時ECC解碼器2215内的徵狀值更正電路(未繪示)更新 徵狀值記憶體2213内相對應的徵狀值’同時EDc記憶體2217内 的EDC結果亦透過EDC更正器2219被更新。下一方向的ECC 動作係直接讀取儲存在PI徵狀值記憶體22〇9和p〇徵狀值記憶 體2213中的徵狀值。兩方向的Ecc動作會持續交替執行直到執 行次數達到一預定數目或沒有錯誤資料存在為止。 錯誤更正系統2300中的pi徵狀值記憶體2209可被整合於資 料緩衝H中’如第丨6騎示。第10睛^ 了根據本發明之第十 實施例的錯誤更正系統2400的方塊圖。在錯誤更正系統〇 :,來自預先PIECC解碼器2301的職狀值被儲存至資料緩衝 裔雇中,而不是Π徵狀值記憶體2209。由於錯誤更正系統期 之動作可由錯誤更正系統23⑻的描述以及錯誤更正㈣2彻之 結構輕易推得,故在此不再贅述。 第Π圖至第2〇圖纷示了本發明之其他實施例的方塊圖。這 些實施例在資料_ n 有預先EDC確認元件,錄值產生器 27 1334132 或是一徵狀值記憶體,且在資料緩衝器之後具有相同的元件。 第17圖繪示了根據本發明之第十六實施例的錯誤更正系統 的方塊圖。如第17圖所示,錯誤更正系統2500包含一資料緩衝 器2501、一解調器2503、一預先EDC確認裝置2505、一預先徵 狀值產生器2507、徵狀值記憶體2509和2511、一 ECC解碼器 2513、一 EDC記憶體2515、以及一 EDC更正器2517。解調器2503 用以接收應解調來自光碟的原始資料以產生包含資料、PI碼字以 及PO碼字的ECC區塊。資料緩衝器2501用以儲存ECC區塊。 預先徵狀值產生器2507用以根據η碼字或p〇碼字產生徵狀值。 徵狀值記憶體2509用以儲存來自預先徵狀值產生器2507的徵狀 值。徵狀值s己憶體2511用以儲存來自資料緩衝器2511的徵狀值。 ECC解碼器2513用以根據儲存在記憶體2511内的徵狀值施行ρι 或PO ECC動作以產生Pi或P〇勘誤結果。EDC記憶體2515用 以暫存來自資料緩衝器25〇1的咖結果。edc更正器2517用以 根據來自ECC解碼器2517的H或p〇勘誤結果更正edc結果。 緩衝器2501中。 錯誤更正系統2500的動作可簡述如下。來自解調器25〇3的 解調資料猶送靖梅翻咖、猶跳顧裝置25〇5、 預先徵狀值產生! 25〇7。徵紐縣从咖絲_存在資料 2501後,開始執 接著當足夠解碼的資料雖存至資料緩衝器 28 1334132 行底下的動作。EDC結果被讀取至EDC記憶體2515。徵狀值結 果被讀取至徵狀值記憶體2511,ECC解碼器2513施行一方向的 ECC動作,同時ECC解碼器2513内的徵狀值更正電路(未繪示) 更新相對應的徵狀值,同時EDC記憶體2515内的EDC結果亦透 過EDC更正器2517被更新。此種動作將持續到每一列都被更新 為止。 在所有列都被更正完後’ ECC解碼器2513根據P0徵狀值結 果施行另一方向的ECC動作,同時ECC解碼器2513内的徵狀值 更正電路(未繪示)更新相對應的徵狀值,同時EDC記憶體2515 内的EDC結果亦透過EDC更正器2517被更新。此種動作將持續 到每一行都被更新為止。 在所有行《處理完後,下—方向的咖動作係直接讀取儲 存在徵狀值記憶體加中的徵狀值,而不是根據資料緩衝器咖 中的資料計算徵紐。兩方⑽咖動作讀敎魏行直到執 订次數達到—預定數目或沒有錯誤㈣存在為止。 並不阳一於針、所不之徵狀值記憶體洲的徵狀值結果 、不限疋於暫存至資料緩衝器咖,如第18圖所示,因此錯誤更 正糸統2500和2_的連制細動作Then, when the sufficiently decoded data is stored in the data buffer 18〇1, the underlying action is started. The ECC block is read from the data buffer 18〇1, and the p〇 symptom generator 1809 generates a PO symptom value and stores it in the P〇 symptom value 1811. The Ecc decoder 1813 and the nonlinear EDC confirming component 1815 respectively perform the Ecc action in the first direction and the nonlinear EDC action based on the result of the syndrome value in the data in the data buffer ι8〇. The result of the non-linear EDC action is stored in the EDC memory 1817. Then the 'ECC decoder 1813 corrects the error data in the data buffer, and the correction of the syndrome correction circuit in the ECC decoder 1813 corresponds to the corresponding correction? The PI and p〇 symptom values in the syndrome value 1807 and the PO symptom value memory 1811, and the EDC results in the EDC 22 memory 1817 are also updated by the EDC corrector 1819. The ECC action in the lower direction directly reads the syndrome value stored in the symptom value memory 18〇7, instead of calculating the syndrome value based on the data in the data buffer job. The pi and P〇 ECC actions continue to alternate until the number of executions reaches a predetermined number or no error data exists. The PI symptom value memory 1807 in Fig. 11 can be integrated into the data buffer U07 as shown in Fig. 12. Fig. 12 is a view showing the manner of the error correction system 21GG according to the eleventh embodiment of the present invention. In this embodiment, the value of the ρι symptom is stored in the data buffer stomach towel instead of the ρι 录 体 卜 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他Figures 13 through 15 illustrate block diagrams of other embodiments of the present invention. These % cases have a pre-EDC confirmation component, a syndrome generator or a 疋-pre-ECC component in front of the data buffer, and have phase-components after the data buffer. Figure 13 is a block diagram showing an error correction system 2200 in accordance with a twelfth embodiment of the present invention. As shown in FIG. 13, the error correction system 22 includes a data buffer 220-demodulator 2203, a pre-EDC confirmation component 22〇5, a pre-argument generator 2207, and a PI syndrome. The memory 22 has a p2 value generating state 2211, a PO symptom value memory 2213, an ECC decoder, > EDC memory 2217, and an eDC corrector 2219. Demodulator 2213 is operative to receive the original data that should be demodulated from the vehicle to produce an ECC block containing the data, the H codeword, and the 23 1334132 P0 codeword. The EDC validation component 22〇5 performs an EDC action on the master data from the demodulated H 2203 to produce an EDC result. Data buffer 2203 is used to store ECC blocks and EDC results. The pre-pig symptom generator 2207 is configured to generate a PI syndrome based on the ECC block from the demodulator 2201. The PO symptom value memory 2209 is used to store the positive sign value from the p〇 symptom value generator. The ECC decoder 2215 performs an ECC action based on the PI 丨 P0 syndrome value to generate an errata result. The EDC memory 2217 is used to temporarily store the EDC results. The EDC Corrector 2219 is used to correct the EDC results based on the errata results from the ECC decoder 2215. The error correction system 2200 can be described as follows. The demodulated data from the demodulator 2203 is transmitted to the syndrome generator 2207, the pre-EDC confirmation component 22〇5, and the data buffer H, which is in the PI recording memory 2209 and EDC. The result is stored in the data buffer 22〇1 0. Then, when the sufficiently decoded data is stored in the data buffer 2201, the next action is started. The data buffer 22G1 _ EDC wire is read and read in the EDC memory 2217. The ECC decoder 2215 performs an ECC action in one direction according to the PI symptom value stored in the pi selection value memory 22〇9, and the symptom correction circuit (not shown) in the ECC decoder 2215 updates the PI flag. The value of the PI and p〇 values in the memory value 2213 of the value memory 22〇9*p〇, and the EDC result in the EDC memory are also updated by the EDC corrector 2219. The ECC block in the data buffer is read and the p〇 value generator 2211 calculates the p〇 symptom value and stores it in the P0 symptom value memory block 2213. When the motion in one direction is completed 24 1334132, the ECC action in the next direction directly reads the syndrome value stored in the syndrome memory 22〇9 and 2211 instead of the data buffer 22〇1. The data is calculated for the syndrome value. The forward ECC action will be sent to Wei Wei until the number of executions reaches a predetermined number or no error data exists. Figure I4 does not depict a block diagram of the error correction system 7〇〇 according to the thirteenth aspect of the present invention. As shown in FIG. 14, the error correction system includes a data buffer 50 demodulator 503, a pre-EDC confirmation component 6A, a pre-pig symptom generator 507, and a PI symptom memory 505. - P〇 symptom generator 509, - symptom value memory 5U, an ECC jammer 513 ... edc memory 605, and - EDC corrector 603. The ECC decoder 513 performs ECC_ according to the ρι or p〇 syndrome value to generate a secret result. The EDC clock 4 is used to temporarily store the EDC (fruit. The EDC corrector 603 is used to correct the EDC result based on the errata result from the Ecc decoder 513. The action of the error correction system 700 can be as follows. From the demodulator 5〇3 The demodulated data is transmitted to the pre-signal value generator 5〇7, the pre-coffee confirmation element 601, and the data buffer pass, wherein the H-choke value is stored in the ρι symptom value memory 505 and the EDC result is stored in Within the data buffer 501. Then, when enough data is stored in the (4) buffer, the next action is started. The EDC result in the data buffer 5〇1 is read and stored in the 605. The ECC decoder 513 performs the - (10) ECC action '_ECC decoder 5i3_ symptom correction circuit (not shown) to update the symptom value memory 5U according to the value of the shape 25 1334132 stored in the data buffer $5〇1. Within the PI_ symptom value, the coffee result in the coffee memory 6〇5 is also updated by the coffee correction device. The ECC block of the poor material buffer pair _ take and the 〇 〇 健 健 , , The symptom value is stored and stored in the symptom value memory 511. When the "direction" action is completed After the 'lower-square (four) ECC_ system direct _ existence of the symptom value in the recorded value memory 511 ' instead of calculating the syndrome value according to the data in the data buffer 5 〇 1. Both (10) ECC action will _ (four) perform a long execution The reading reaches a predetermined number or no error data exists. Fig. 15 is a block diagram showing the error correction system 2300 according to the fourteenth embodiment of the present invention, which is compared with the error correction system shown in Fig. 13. The error correction button has a more - pre-"ECC decoder track, and the pre-mortem value generator 22G7 is integrated into the pre-PIECC decoder fiber. Therefore, the error correction system 2200 and 2300 connection relationship and action are not @ The operation of the error correction system 2300 can be as follows: the demodulated data from the demodulator 22〇3 is passed on the CC decoder, the pre-registration component 2205, and the data buffer 22 (H' where Pm is The value is stored in the text value memory 2209 and the EDC result is stored in the data buffer 22 。 1. Then, when the sufficiently decoded data is stored in the data buffer 22 〇 1, the underlying action is started. Device The EDC result is read and stored in the mc memory side (2)7' and the PO symptom value is generated as calculated p〇 symptom value and stored in the 26 1334132 symptom value memory. The ECC decoder 2215 is based on the P0 symptom value. The ECC action in one direction is performed, and the syndrome correction circuit (not shown) in the ECC decoder 2215 updates the corresponding p〇 symptom value in the P0 symptom memory 2213, and the EDC in the EDC memory 2217. The result is also updated by the EDC corrector 2219. The ECC decoder 2215 then performs an ECC action in the other direction based on the PI syndrome value, while the syndrome correction circuit (not shown) in the ECC decoder 2215 updates the syndrome value memory. The corresponding syndrome value in the body 2213 is also updated by the EDC corrector 2219 in the EDC result in the EDC memory 2217. The ECC action in the next direction directly reads the syndrome values stored in the PI symptom value memory 22〇9 and the p〇 symptom value memory 2213. Ecc actions in both directions will continue to alternate until the number of executions reaches a predetermined number or no error data exists. The pi symptom value memory 2209 in the error correction system 2300 can be integrated into the data buffer H as shown in Fig. 6. The tenth eye is a block diagram of the error correction system 2400 according to the tenth embodiment of the present invention. In the error correction system 〇: the value of the job from the pre-PIECC decoder 2301 is stored in the data buffer employment instead of the symptom value memory 2209. Since the error correction system period action can be easily derived from the description of the error correction system 23 (8) and the error correction (4) 2 structure, it will not be repeated here. The second to second drawings illustrate block diagrams of other embodiments of the present invention. These embodiments have a pre-EDC confirmation component in the data_n, the record generator 27 1334132 or a syndrome memory, and have the same components after the data buffer. Figure 17 is a block diagram showing an error correction system in accordance with a sixteenth embodiment of the present invention. As shown in FIG. 17, the error correction system 2500 includes a data buffer 2501, a demodulator 2503, a pre-EDC confirmation device 2505, a pre-symmetric value generator 2507, symptom value memories 2509 and 2511, and a An ECC decoder 2513, an EDC memory 2515, and an EDC corrector 2517. The demodulator 2503 is configured to receive the original data from the optical disc to generate an ECC block containing the data, the PI codeword, and the PO codeword. The data buffer 2501 is used to store ECC blocks. The pre-symptom value generator 2507 is configured to generate a syndrome value from the n-codeword or the p-codeword. The symptom value memory 2509 is used to store the syndrome value from the pre-symptom value generator 2507. The syndrome value s 2+ is used to store the syndrome value from the data buffer 2511. The ECC decoder 2513 is operative to perform a ρι or PO ECC action based on the syndrome value stored in the memory 2511 to generate a Pi or P errata result. The EDC memory 2515 is used to temporarily store the coffee result from the data buffer 25〇1. The edc corrector 2517 is used to correct the edc result based on the H or p errata result from the ECC decoder 2517. In the buffer 2501. The actions of the error correction system 2500 can be briefly described as follows. The demodulation data from the demodulator 25〇3 is still sent to Jingmei, and the device is 25〇5. 25〇7. After collecting the 250s from the café _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The EDC results are read into EDC memory 2515. The syndrome value result is read to the symptom value memory 2511, and the ECC decoder 2513 performs the ECC action in one direction, and the syndrome correction circuit (not shown) in the ECC decoder 2513 updates the corresponding symptom value. At the same time, the EDC result in the EDC memory 2515 is also updated by the EDC corrector 2517. This action will continue until each column is updated. After all the columns have been corrected, the ECC decoder 2513 performs the ECC action in the other direction according to the P0 syndrome value, and the syndrome correction circuit (not shown) in the ECC decoder 2513 updates the corresponding symptom. The value, while the EDC result in the EDC memory 2515 is also updated by the EDC Corrector 2517. This action will continue until each line is updated. After all the lines are processed, the lower-direction coffee action directly reads the symptom value stored in the symptom value memory plus, instead of calculating the sign based on the data in the data buffer coffee. The two parties (10) coffee action read Wei Wei until the number of orders reached - the predetermined number or no error (four) exists. The results of the symptoms of the memory of the needles and the symptoms of the memory are not limited to the temporary storage to the data buffer, as shown in Figure 18, so the error corrections are 2500 and 2_ Fine action

了根據本發明之第ww J 弟十七貝她例的錯誤更正系統的方塊圖。錯誤争 正系統2600的動作可簡述 圖錯破 來自解調益2503的解調資料被 29 1334132 傳送至資料緩衝器2501、預先EDC確認裝置25〇5、預先徵狀值 產生态2507。徵狀值結果被儲存在徵狀值記憶體25〇9,而EDC 結果被儲存在資料緩衝器25〇1中。 接著當足夠解碼的資料被儲存至資料緩衝器25〇1後,開始執 行底下的動作。EDC結果被讀取至EDC記憶體2515。ECC解碼 器2513根據徵狀值記憶體25〇9内的徵狀值施行一方向的Ecc動 作’同時ECC解碼器2513内的徵狀值更正電路(未繪示)更新徵 狀值記憶體2509内相對應的徵狀值,同時EDC記憶體2515内的 EDC結果亦透過EDC更正器2517被更新。此種動作將持續到每 一列都被更新為止。 在所有列都被更正完後,ECC解碼器2513根據p〇徵狀值結 果施打另一方向的ECC動作,同時ECC解碼器2513内的徵狀值 更正電路(未繪示)更新相對應的徵狀值,同時EDC記憶體乃Μ 内的EDC結果亦透過EDC更正器2517被更新。此種動作將持續 到每一行都被更新為止。 在所有行都被處理完後,下一方向的ECC動作係直接讀取儲 存在徵狀值記憶體2511中的徵狀值,而不是根據資料緩衝器25〇1 中的資料計算徵狀值。兩方向的ECC動作會持續交替執行直到執 行次數達到一預定數目或沒有錯誤資料存在為止。 錯誤更正系統2500可更包含一預先pIECC解碼器27⑴,如 30 1334132 第19圖所示。® 19 ®繪示了根據本發明之第十八實施例的錯誤 更正系統2700的方塊圖,其動作如下所示。來自解調器25〇3的 解調資料被傳送至資料緩衝器2501、預先EDC確認裝置25〇5以 及預先徵狀值產生器2507。徵狀值結果以及EDC結果被儲存在資 料緩衝器2501中。 預先PIECC解碼器2701根據徵狀值產生器的徵狀值對資料 緩衝器2501中的ECC ϋ塊施行- piECC動作以產生徵狀值結果 以及EDC結果,都被儲存在資料緩衝器25〇1中。同時ECC解碼 器2513内的徵狀值更正電路(未纷示)更新徵狀值記憶體内相對 應的徵狀值,同時資料緩衝器2501内的EDC結果亦透過EDC更 正器2517被更新。 接著當足夠解碼的資料被儲存至資料緩衝器25〇1後,開始執 行底下的動作。徵狀值結果被讀取至徵狀值記憶體2511,Ecc 解碼器2513施行一方向的ECC動作,同時ECC解碼器2513内 的徵狀值更正電路(未繪示)更新相對應的徵狀值,同時EDC記 憶體2515内的EDC結果亦透過EDC更正器2517被更新。 然後PI徵狀值結果被讀取至徵狀值記憶體2511,ECC解碼 姦2513施行另一方向的ECC動作,同時ECC解碼器2513内的 徵狀值更正電路(未繪示)更新相對應的徵狀值,同時EDC記憶 體2515内的EDC結果亦透過EDC更正器2517被更新。 31 下彳向的ECC動作係直接讀取健存在徵狀值記憶體训 中的徵狀值,而不是根據資料緩翻咖中㈣料計算徵狀值。 兩方向的ECC動作會_錢執行朗執行缝朗—預定數目 或沒有錯誤資料存在為止。 徵狀值記憶體2511的徵狀值結果並不限定於暫存至資料緩 衝器25〇1,如第20圖所示,因此錯誤更正系統27〇〇和2獅的動 作和連接關係有所不同。第2〇圖繪示了根據本發明之第十九實施 例的錯誤更正系統2_的方額,其動作可如下所述。來自解調 器細的解調資料被傳送至資料緩衝器25〇1、預先edc確認裝 置2505以及預先徵狀值產生器25〇7。 預先PI ECC解碼器2701根據徵狀值產生器的徵狀值對資料 緩衝器2501中的ECC區塊施行一 piECC動作以更新徵狀值記憶 體25〇9内的徵狀值。徵狀值結果被儲存在程支狀值記憶體μ的以 及EDC結果儲存在資料緩衝器25〇1内。同時Ecc解碼器Mu 内的徵狀值更正電路(未繪示)更新徵狀值記憶體2,内相對應 的徵狀值,同時EDC記憶體内2515的EDC結果亦透過EDC更 正器2517被更新。 接著當足夠解碼的資料被儲存至資料緩衝器25〇1後,開始執 打底下的動作。EDC結果被讀取至EDC記憶體2515。Ecc解碼 32 1334132 器2513根據徵狀值記憶體2509内的徵狀值施行另一方向的ECC 動作,同時ECC解碼器2513内的徵狀值更正電路(未繪示)更新 相對應的徵狀值,同時EDC記憶體2515内的EDC結果亦透過 EDC更正器2517被更新。 然後PI徵狀值結果被讀取至徵狀值記憶體2509,ECC解碼 器2513施行一方向的ECC動作,同時ECC解碼器2513内的徵 狀值更正電路(未繪示)更新相對應的徵狀值,同時EDC記憶體 2515内的EDC結果亦透過EDC更正器2517被更新。 下一方向的ECC動作係直接讀取儲存在徵狀值記憶體25〇9 中的徵狀值,而不是根據資料緩衝器lOi中的資料計算徵狀值。 兩方向的ECC動作會持續交替執行直到執行次數達到一預定數目 或沒有錯誤資料存在為止。 第21圖繪示了第2圖所示的錯誤更正系統11〇〇之錯誤更正 方法。此方法包含: 步驟3001 接收並解調原始資料以產生一 ECC區塊 步驟3003 根據該ECC區塊的資料施行一 EDC動作以產生一 EDC結果 步驟3005 . 33 1334132 儲存該ECC區塊和該EDC結果 步驟3007 ^據儲存的該ECC區塊的-Π碼字和—p〇碼字產生至少—徵狀 步驟3009 根據該徵狀值施行一 ECC動作 步驟3011 根據該ECC動作的結果以更正該EDc結果 ,據Η或Ρ0徵狀值的ECC _料斷交·複直到 的數篁酬-敢值或沒有錯誤鱗存在為止。 若此方法對應於第3 _示的錯誤更正系統削,其更包 含:對來自步驟3〇01的ECC區塊施行一 piECC動作,以更正錯 誤資料並根據HECC動作的結果修IEDC結果。 日 若此方法對應於第4麟示的錯誤更正㈣,其更包含:儲 存來自。步驟3〇〇1的ECC區塊,並施行—PI ECC動作在儲存的 ECC區塊上。而且,步驟3〇〇3更在η Ecc動作之後施行EDC 動作以產生EDC結果。 34 丄兮丄 其他洋細特徵已揭露於第2 不再贅述。 圖至第4圖的描述當中,故在此 步驟3101 接收並解調原始資料以產生—Ecc區塊; 步驟3103 根據該ECC區塊的資料施行一咖動作以產生一腦結果; 步驟3105 儲存ECC區塊和該EDC結果; 步驟3107 對該ECC區塊施行一 PIECC動作,以更正該ECC區塊,並用以 根據該PIECC動作之一結果更正該EDC結果 步驟3109 暫存一部份的該儲存ECC區塊; 步驟3111 根據步驟3109中暫存的該ECC區塊之一 PO碼字產生一 p〇徵狀 35 …4132 值; 步驟3113 根據該ECC區塊之一 Π碼字產生一 Pi徵狀值; 步驟3115 根據該Η徵狀值以及該P0徵狀值至少其一施行一 ECC動作;以 及 步騍3117 根據該ECC動作之一結果更正該EDC結果。 根據Η或Ρ0徵狀值的ECC動作將不斷交替重複直到重覆 的數量剩—預定值姐有錯誤資料存在為止。 此外其他細節已揭示在第5_描述中,故於此省略。 s第23圖綠不了對應第6圖所示的錯誤更正系統1500之錯誤 更正方法,其包含: 步驟3201 接收並解調原始資料以產生-ECC區塊 步驟3203 36 1334132 對來自步驟3201的ECC區塊施行一 PIECC動作以產生更正後 ECC區塊 步驟3205 儲存ECC區塊以及更正後ECC區塊 步驟3207 對步驟3205中儲存的ECC區塊施行一非線性EDC動作以產生 £DC結果。 步驟3209 根據步驟3205中儲存的ECC區塊之Π碼字和p〇碼字產生至少 一徵狀值。 步驟3211 根據徵狀值施行一 ECC動作。 步驟3213 根據ECC動作之結果更正jgDc結果。 此方法之徵狀值包含PI徵狀值和p〇徵狀值至少其一。根據 Η或K)徵狀值的ECC動作將不斷交替重複直到重覆的數量到到 —預定值或沒有錯誤資料存在為止。 37 若第21圖所示的方法對應於第 1_ ’其更包含:儲縣自步驟伽 於第7圖 變化可由前述說明令得知。 圖所示的錯誤更正系統 +的部份ECC區塊。其他 若第21騎示的方法對應於第A block diagram of the error correction system of the example of the ww J brother seventeen in accordance with the present invention. The operation of the error contending system 2600 can be briefly described. The demodulation data from the demodulation benefit 2503 is transmitted to the data buffer 2501, the pre-EDC confirmation device 25〇5, and the pre-signal generation state 2507. The result of the syndrome is stored in the syndrome memory 25〇9, and the EDC result is stored in the data buffer 25〇1. Then, when the sufficiently decoded data is stored in the data buffer 25〇1, the underlying action is started. The EDC results are read into EDC memory 2515. The ECC decoder 2513 performs an Ecc operation in one direction based on the syndrome value in the syndrome memory 25〇9. The syndrome value correction circuit (not shown) in the ECC decoder 2513 updates the syndrome memory 2509. The corresponding syndrome value, while the EDC result in the EDC memory 2515 is also updated by the EDC corrector 2517. This action will continue until each column is updated. After all the columns have been corrected, the ECC decoder 2513 applies the ECC action in the other direction according to the p〇 symptom value result, and the syndrome correction circuit (not shown) in the ECC decoder 2513 updates the corresponding one. The EEG value of the EDC memory is also updated by the EDC Corrector 2517. This action will continue until each line is updated. After all the lines have been processed, the ECC action in the next direction directly reads the syndrome value stored in the symptom value memory 2511 instead of calculating the syndrome value based on the data in the data buffer 25〇1. The ECC actions in both directions will continue to be alternated until the number of executions reaches a predetermined number or no error data exists. The error correction system 2500 can further include a pre-pIECC decoder 27(1) as shown in Fig. 19 of 30 1334132. ® 19 ® illustrates a block diagram of an error correction system 2700 in accordance with an eighteenth embodiment of the present invention, the actions of which are as follows. The demodulated data from the demodulator 25〇3 is sent to the data buffer 2501, the pre-EDC confirming means 25〇5, and the pre-signal value generator 2507. The syndrome values and EDC results are stored in the data buffer 2501. The pre-PIECC decoder 2701 performs a -piECC action on the ECC block in the data buffer 2501 according to the syndrome value of the syndrome generator to generate the syndrome value result and the EDC result, which are all stored in the data buffer 25〇1. . At the same time, the syndrome correction circuit (not shown) in the ECC decoder 2513 updates the corresponding symptom value in the syndrome memory, and the EDC result in the data buffer 2501 is also updated by the EDC corrector 2517. Then, when the sufficiently decoded data is stored in the data buffer 25〇1, the underlying action is started. The syndrome value result is read to the symptom value memory 2511, and the Ecc decoder 2513 performs the ECC action in one direction, and the syndrome correction circuit (not shown) in the ECC decoder 2513 updates the corresponding symptom value. At the same time, the EDC result in the EDC memory 2515 is also updated by the EDC corrector 2517. Then, the PI symptom value result is read to the symptom value memory 2511, and the ECC decoding flag 2513 performs the ECC action in the other direction, and the syndrome value correction circuit (not shown) in the ECC decoder 2513 updates the corresponding one. The syndrome value, while the EDC result in the EDC memory 2515 is also updated by the EDC corrector 2517. The lower ECC action is directly reading the symptom value in the training of the symptomatic memory, rather than calculating the symptom based on the data. The ECC action in both directions will be executed by the execution of the money - the predetermined number or no error data exists. The result of the syndrome value of the symptom value memory 2511 is not limited to the temporary storage to the data buffer 25〇1, as shown in Fig. 20, so the error correction system 27〇〇 and the 2 lion's action and connection relationship are different. . Fig. 2 is a diagram showing the scale of the error correction system 2_ according to the nineteenth embodiment of the present invention, the operation of which can be as follows. The demodulated data from the demodulator is transferred to the data buffer 25'1, the pre-edc confirming means 2505, and the pre-signal value generator 25'7. The pre-PI ECC decoder 2701 performs a piECC action on the ECC block in the data buffer 2501 based on the syndrome value of the syndrome generator to update the syndrome value in the syndrome memory 25〇9. The result of the syndrome value is stored in the path value memory μ and the EDC result is stored in the data buffer 25〇1. At the same time, the syndrome correction circuit (not shown) in the Ecc decoder Mu updates the corresponding symptom value of the symptom value memory 2, and the EDC result of the E15 memory 2515 is also updated by the EDC corrector 2517. . Then, when enough decoded data is stored in the data buffer 25〇1, the underlying action is started. The EDC results are read into EDC memory 2515. The Ecc decoding 32 1334132 2513 performs the ECC action in the other direction according to the syndrome value in the syndrome memory 2509, and the syndrome correction circuit (not shown) in the ECC decoder 2513 updates the corresponding syndrome value. At the same time, the EDC result in the EDC memory 2515 is also updated by the EDC corrector 2517. Then, the result of the PI symptom value is read to the symptom value memory 2509, and the ECC decoder 2513 performs the ECC action in one direction, and the syndrome correction circuit (not shown) in the ECC decoder 2513 updates the corresponding sign. The value, while the EDC result in the EDC memory 2515 is also updated by the EDC corrector 2517. The ECC action in the next direction directly reads the symptom value stored in the symptom value memory 25〇9, instead of calculating the symptom value based on the data in the data buffer lOi. ECC actions in both directions will continue to alternate until the number of executions reaches a predetermined number or no error data exists. Fig. 21 is a diagram showing the error correction method of the error correction system 11 shown in Fig. 2. The method includes the following steps: Step 3001: Receive and demodulate original data to generate an ECC block. Step 3003 Perform an EDC action according to the information of the ECC block to generate an EDC result. Step 3005. 33 1334132 Store the ECC block and the EDC result. Step 3007: Generate at least a symptom based on the stored -Π codeword and the -p〇 codeword of the ECC block. Step 3009 Perform an ECC action step 3011 according to the symptom value to correct the ECC result according to the result of the ECC action. According to the ECC of the Η or Ρ0 trait value, the number of rewards is up to the value of the sacred value or the horrible value. If the method corresponds to the error correction of the third embodiment, it further includes: performing a piECC action on the ECC block from step 3〇01 to correct the error data and repair the IEDC result according to the result of the HECC action. If this method corresponds to the error correction of the 4th Lin (4), it also includes: the storage comes from. Step 3〇〇1 of the ECC block and perform the –PI ECC action on the stored ECC block. Moreover, step 3〇〇3 performs an EDC action after the η Ecc action to generate an EDC result. 34 丄兮丄 Other fine features have been revealed in Section 2 and will not be repeated. In the description of FIG. 4, the original data is received and demodulated in this step 3101 to generate an -Ecc block; Step 3103 is performed according to the data of the ECC block to generate a brain result; Step 3105 is to store the ECC. Block and the EDC result; Step 3107: Performing a PIECC action on the ECC block to correct the ECC block and correcting the EDC result according to one of the PIECC actions. Step 3109 temporarily storing a portion of the stored ECC a block; step 3111: generating a p 〇 35 35 ... 4132 value according to one of the ECC blocks temporarily stored in step 3109; step 3113 generating a Pi symptom value according to one of the ECC blocks Step 3115 performs an ECC action according to at least one of the syndrome value and the P0 symptom value; and step 3117 corrects the EDC result according to one of the ECC actions. The ECC action according to the Η or Ρ0 symptom value will be alternately repeated until the number of repetitions remains - the predetermined value of the sister has the wrong data. Further details have been disclosed in the fifth description, and thus are omitted here. Figure 23 of the s green does not correspond to the error correction method of the error correction system 1500 shown in Fig. 6, which includes: Step 3201 Receive and demodulate the original data to generate an -ECC block Step 3203 36 1334132 For the ECC area from step 3201 The block performs a PIECC action to generate a corrected ECC block. Step 3205 Stores the ECC block and corrects the ECC block. Step 3207 performs a non-linear EDC action on the ECC block stored in step 3205 to generate a £DC result. Step 3209 generates at least one syndrome value according to the codeword and the p〇 codeword of the ECC block stored in step 3205. Step 3211 performs an ECC action according to the syndrome value. Step 3213 corrects the jgDc result based on the result of the ECC action. The symptom value of this method includes at least one of a PI symptom value and a p〇 symptom value. The ECC action according to the Η or K) symptom value will be alternately repeated until the number of repetitions reaches a predetermined value or no error data exists. 37 If the method shown in Fig. 21 corresponds to the 1_', it further includes: the change of the storage county from the step gamma to Fig. 7 can be known from the above description. The error shown in the figure corrects part of the ECC block of System+. Other If the 21st ride method corresponds to the first

包含為步驟3〇11儲存步驟伽所產生的ρι徵狀值。Contains the value of the ρι pattern generated by storing the step gamma for step 3〇11.

圖的描述當中,故在此不再贅述。 第24圖繪不了對應第8圖所示的錯誤更正系統 1700之錯誤 更正方法,其包含: 步驟3301 接收並解調原始資料以產生一 ECC區塊 步驟3303 儲存ECC區塊以及更正後ECC區塊 步驟3305 38 1334132 在來自步驟3301的ECC區塊上施行一 PI ECC動作以產生更正後 ECC區塊 步驟3307 根據步驟3303中的ECC區塊施行非線性EDC動作以產生EDC 結果 步驟3309 根據步驟3303中的ECC區塊之PO碼字產生一 p〇徵狀值 步驟3311 對步驟3303中的ECC區塊根據PI徵狀值或p〇徵狀值施行gee 動作 步驟3313 根據步驟3303中的ECC區塊之pi碼字產生—ρι徵狀值 步驟3315 根據該ECC動作之一結果更正該EDC結果。 贅述 其他詳細特徵已揭露於第8圖的描述當中,故在此不再 1800 第25圖繪示了對應第9圖〜第20圖所示的錯誤更正系統 與1900之錯誤更正方法。 … 39 1334132 步驟3401 接收並解調原始資料以產生一 ECC區塊 步驟3403 根據步驟3401中的ECC區塊之PI碼字產生-朽徵狀值 步驟3405 儲存ECC區塊 步驟3407 根據步驟3405中的ECC區塊之PO碼字產生- p〇徵狀值 步驟3409 根據步驟3405中的ECC區塊施行非線性EDC動作以產生EDc 結果 步驟3411 根據H徵狀值和PO徵狀值至少其-施行- ECC動作。 步驟3413 根據ECC麵(絲更正EDC結果。 此方法之徵狀值包含PI徵狀值和PO徵狀值至少其一。根據 40 綱爾峨量到到 若第25圖所示的方法對應於第13和Η圖所示的錯誤更正系 統。此方法更根據步驟_中儲存的Ecc區塊產生ρ〇徵狀I 且步驟3403更用以產生pj徵狀值。 此外若第25圖所示的方法對應於第15和16圖所示的錯誤更 正系統,步驟3403更施行一 pj Ecc動作。 若第25圖所示的方法對應於第17圖所示的錯誤更正系統, 更包含儲存徵狀值並提供徵狀值給步驟34〇9。 若第25騎示的方法對應於第19騎示的錯誤更正系統, 更包含儲存徵狀值並提供徵狀值給步驟。 若第25圖所示的方法對應於第2〇圖所示的錯誤更正系統, 更包含更正步驟3405中儲存的ECC區塊之資料以及EDC結果, 並更正儲存的徵狀值。 前述的系統具有不同的結構以及不同的好處。舉例來說,徵 狀值記憶體和徵狀值更正電路的使用可以降低資料緩衝器的頻寬 消耗’EDC §己憶體和EDC更正器的使用亦可以降低資料緩衝器的 頻寬消耗。而且,本發明提供了使用徵狀值記憶體'徵狀值更正 丄334132 電路、EDC記憶體和更正器、以及pI、p〇 Ecc以提供不同 型癌的錯誤更正系統。因此本發明可以符合不同的需求。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範 圍所做之均等變化與修飾,皆麟本發明之涵蓋範圍。 【圖式簡單說明】 第1圖繪不了相關技術之錯誤更正系統的方塊圖。 第®、’.曰示了根據本發明之第一實施例的錯誤更正系統的方 塊圖。 ’一 第3圖、、示了根據本發明之第二實施例的錯誤更正系,统的方 塊圖。 ~ 第4圖繪示了根據本發明之第三實施例的錯誤更正系统的方 塊圖。 第5崎示了根據本發明之第四實施_錯誤更统的方 塊圖。 第6圖㈣了根據本發明之第五實施例的錯誤更 的方 塊圖。 ~ 第7圖缘示了根據本發明之第六#施_錯誤更 的方 塊圖。 ~ 第8圖繪示了根據本發明之第七實施例的錯誤更 的方 塊圖。 第9圖_了祕本發明之第八實施_錯誤更正系統的方 42 塊圖。 第10圖纟會不了根據本發明之第九實施例的錯誤更正系統的 方塊圖。 方塊圖 第11 _示了根據本發明之第十實施例的錯誤更正系統的 第12崎不了根據本發明之第十—實施例的錯誤更正 的方塊圖。 的方騎不了根據本發明之第十二實施例的錯誤更正系統 的方_示了根據本㈣之第十三實關⑽誤更正系統 的方塊圖。圖’不了根據本發明之第十四實施綱錯誤更正系統 的方塊圖。τ 了根據本判之第十五實施綱錯誤更正系統 的方塊圖。θ 了根據本㈣之第十六實施綱錯誤更正系統 第18圖給·矛τ 的方塊圖。、9根據本發明之第十七實施例的錯誤更正系統 第19圖给示了 的方塊圖。 W本發明之第十人實施例的錯誤更正系統 第2〇圖、给- ' 的方塊^ 9不了根據本發明之第十九實施例的錯誤更正系統 43 1334132 第21圖繪示了對應第2圖 流程圖。 第22圖繪示了對應第5圖 流程圖。 第23圖繪示了對應第6圖 流程圖。 之錯誤更正__較正方法之 之錯誤更正系統的錯誤更正方法之 之錯誤更JL系統的錯誤更正方法之 流程圖。 第24圖繪示了對應第8圖之錯誤更正系統的錯誤更正方法之 第25圖繪示了對應第9圖〜第25圖之錯誤更正系統的錯誤更 正方法之流程圖。 【主要元件符號說明】 錯誤更正系統 100, 700, 1100, 1200, 1300, 1400, 1500, 1600, 1700 1800,1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2800 資料緩衝器 101,501,1101,1801,2201,2501 解調器 103, 503, 1103, 1803, 2203, 2503 徵狀值產生器105, 1107, 2507 徵狀值記憶體107, 511,1109 ECC 解碼器 1〇9, 513, 1111,1405, 1813, 2215, 2513 線性EDC確認元件111 EDC 記憶體 113, 605, 1113, 1411,1817, 2217, 2515 EDC 更正器 115, 603, 1115,1413, 1819, 2219, 2517 預先EDC確認元件601,1105 44 1334132 預先 PIECC 解碼器 1201,2001,2301,2701 記憶體元件1301,1401 PI 徵狀值記憶體 505, 1409, 1807, 2209 PI徵狀值產生器507, 1407, 2207 PO 徵狀值產生器 509, 1403, 1805, 1809,2211 非線性 EDC 確認元件 1501,1601,1701,1815 PO徵狀值記憶體1811,2213 預先EDC確認元件2205 徵狀值記憶體2509 2511 45In the description of the figure, it will not be described here. Figure 24 illustrates an error correction method corresponding to the error correction system 1700 shown in Figure 8, which includes: Step 3301 Receive and demodulate the original data to generate an ECC block. Step 3303 Store the ECC block and correct the ECC block. Step 3305 38 1334132 Perform a PI ECC action on the ECC block from step 3301 to generate a corrected ECC block. Step 3307 Perform a non-linear EDC action according to the ECC block in step 3303 to generate an EDC result. Step 3309. According to step 3303. The PO code word of the ECC block generates a p〇 value value step 3311. The ECC block in step 3303 is subjected to a Gee action step 3313 according to the PI symptom value or the p〇 symptom value. According to the ECC block in step 3303 The pi code word generation - ρι symptom value step 3315 corrects the EDC result based on one of the ECC actions. Descriptions Other detailed features have been disclosed in the description of Fig. 8, and therefore no longer 1800 Fig. 25 illustrates the error correction method corresponding to the error correction system and the 1900 shown in Figs. 9 to 20. 39 1334132 Step 3401 Receive and demodulate the original data to generate an ECC block Step 3403 Generate a falsification value according to the PI codeword of the ECC block in step 3401 Step 3405 Store the ECC block Step 3407 According to step 3405 The PO code word generation of the ECC block - p〇 symptom value step 3409 performs a non-linear EDC action according to the ECC block in step 3405 to generate an EDC result. Step 3411 According to the H symptom value and the PO symptom value, at least - the implementation - ECC action. Step 3413 According to the ECC surface (the silk correction EDC result. The symptom value of the method includes at least one of the PI symptom value and the PO symptom value. According to the 40 峨 峨 到 若 若 若 若 若 若 若 若 若 若 若13 and the error correction system shown in the figure. This method generates a ρ 〇 I I according to the Ecc block stored in step _ and step 3403 is used to generate the pj trait value. Corresponding to the error correction system shown in Figures 15 and 16, step 3403 performs a pj Ecc action. If the method shown in Fig. 25 corresponds to the error correction system shown in Fig. 17, it further includes storing the syndrome value and The symptom value is provided to step 34〇9. If the method of the 25th riding corresponds to the error correction system of the 19th riding, the method further includes storing the symptom value and providing the symptom value to the step. Corresponding to the error correction system shown in Fig. 2, it further includes correcting the data of the ECC block stored in step 3405 and the EDC result, and correcting the stored symptom value. The foregoing system has different structures and different benefits. For example, symptom value memory and symptom values Correction of the use of the circuit can reduce the bandwidth consumption of the data buffer. 'EDC § The use of the memory and the EDC correction device can also reduce the bandwidth consumption of the data buffer. Moreover, the present invention provides the use of the syndrome memory. The value correction 丄 334132 circuits, EDC memory and corrections, and pI, p〇Ecc to provide error correction systems for different types of cancer. Therefore, the present invention can meet different needs. The above is only a preferred implementation of the present invention. For example, the average variation and modification of the scope of the patent application of the present invention are covered by the present invention. [Simple Description of the Drawing] FIG. 1 can not depict the block diagram of the error correction system of the related art. A block diagram of an error correction system according to a first embodiment of the present invention is shown. A third figure shows a block diagram of an error correction system according to a second embodiment of the present invention. The figure shows a block diagram of a error correction system according to a third embodiment of the present invention. The fifth embodiment shows a block diagram according to a fourth embodiment of the present invention. The sixth figure (four) is according to the present invention. A block diagram of the error of the fifth embodiment. ~ Fig. 7 is a block diagram showing a sixth embodiment of the invention. ~ Fig. 8 is a diagram showing an error according to the seventh embodiment of the present invention. Fig. 9 is a block diagram of the eighth embodiment of the present invention _ error correction system. Fig. 10 is a block diagram of the error correction system according to the ninth embodiment of the present invention. Figure 11 is a block diagram showing the error correction according to the tenth embodiment of the error correction system according to the tenth embodiment of the present invention. The square can not ride the twelfth according to the present invention. The method of the error correction system of the embodiment shows a block diagram of the system of the error correction system according to the thirteenth (10) of this (4). The figure is a block diagram of the error correction system according to the fourteenth embodiment of the present invention. τ A block diagram of the error correction system according to the fifteenth implementation of this judgment. θ is a block diagram of the error correction system according to the sixteenth embodiment of the present invention, which is given to the spear τ. 9 is a block diagram showing the error correction system according to the seventeenth embodiment of the present invention. The error correction system of the tenth embodiment of the present invention is shown in FIG. 2, and the block of 'the' is not in accordance with the nineteenth embodiment of the present invention. The error correction system 43 1334132 is shown in FIG. Figure flow chart. Figure 22 is a flow chart corresponding to Figure 5. Figure 23 is a flow chart corresponding to Figure 6. The error correction __correction method error correction system error correction method error JL system error correction method flow chart. Fig. 24 is a flow chart showing the error correction method of the error correction system corresponding to Fig. 9 to Fig. 25, showing the error correction method corresponding to the error correction system of Fig. 8. [Main component symbol description] Error correction system 100, 700, 1100, 1200, 1300, 1400, 1500, 1600, 1700 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2800 data buffer 101, 501, 1101, 1801, 2201, 2501 Demodulator 103, 503, 1103, 1803, 2203, 2503 Symptom generator 105, 1107, 2507 Symmetric memory 107, 511, 1109 ECC decoder 1〇 9, 513, 1111, 1405, 1813, 2215, 2513 Linear EDC Confirmation Element 111 EDC Memory 113, 605, 1113, 1411, 1817, 2217, 2515 EDC Corrector 115, 603, 1115, 1413, 1819, 2219, 2517 Pre-EDC confirmation component 601, 1105 44 1334132 Pre-PIECC decoder 1201, 2001, 2301, 2701 Memory component 1301, 1401 PI symptom memory 505, 1409, 1807, 2209 PI symptom generator 507, 1407, 2207 PO symptom generator 509, 1403, 1805, 1809, 2211 Nonlinear EDC confirmation component 1501, 1601, 1701, 1815 PO symptom memory 1811, 2213 EDC confirmation component 2205 Symmetric memory 2509 2511 45

Claims (1)

1334132 十、申請專利範園: 1. 一種錯誤更正系統,包含: 一解調器,肋接收和解糖始資料以產生-ECC區塊; 預先PIECC解媽咨,耗接至該解調器,用以對來自該解調器的 該ECC區塊施行一 PIECC動作以產生一更正後ecc區塊; 一資料緩衝器,用以儲存該ECC區塊和該更正後ecc區塊; 非線EDC確遂裝置,用以根據錯存在該資料緩衝器内的該 / ECC區塊施行—非線性EDC動作以產生—edc結果; 徵狀值產生器,用以根據儲存在該資料緩衝器内的該ecc區塊 之一碼字以產生至少一徵狀值; - ECC解碼器,用以根據該徵狀值施行一 Ecc動作;以及 一 EDC更正器’用以根據該ECC動作之一結果更正該edc結果; 其中該徵狀值包含一 PI徵狀值以及一 p〇徵狀值其中至少之一, 該碼字包含一 PI碼字以及一 P0碼字其中至少之一。 2. 如申請專利範圍第1項所述之錯誤更正系統,更包含一記憶體 元件以儲存來自該解調器的一部份該ECC區塊。 3. 如申請專利範圍第2項所述之錯誤更正系統,其中儲存在該記 憶體元件中的該一部份ECC區塊在被該預先pi eCc解碼琴 處理完後被儲存至該資料缓衝器。 46 4·如申2專利細第丨顧述之錯誤更正系統,射該徵狀值產 生器產生被儲存至—徵狀值記紐巾的該PQ徵狀值,且該 預先PIECC解韻料丹織雜存至該資料緩衝器,藉 此該ECC解碼器更正來自該徵狀值記憶體的該ρ〇徵狀值以 及來自該資料緩衝器的該PI徵狀值。 5. 如申請專利範圍第4項所述之錯誤更正系統,更包含: —Η徵狀值記憶體’用以儲存該預先pi ecc解碼輯產生的該 PI徵狀值; 其中該ECC解碼器根據該ρι徵狀值記憶體内的該ρι徵狀值對該 ECC區塊施行該Ecc動作。 6. 如申μ專利圍第1項所述之錯誤更正祕,其中該原始資料 係儲存在一光碟片中。 7·—種錯誤更正系統,包含: 解調器’用以接收和解調原始資料以產生一 ECC區塊; 預先PIECC解碼器,輕接至該解調器,用以對來自該解調器的 該ECC區塊施行一 ΡΙ Ε(χ動作以產生一更正後ECC區塊; -食料緩動’用以儲存該ECC(1_及該更正後Ε(χ區塊; —s己憶體το件,用以儲存來自該資料緩衝器的一部份該ECC區塊; 一非線性EDC確認裝置,用以對該資料緩衝器中的該ECc區塊 施打一非線性EDC動作以產生—EDc結果; 47 1334132 一 PO徵狀值產生器’用以根據該記憶體元件内的該一部份Ecc 區塊之P0碼字產生一 P〇徵狀值.; 一 π徵狀值產生器,用以根據該記憶體元件内儲存的該部份ECC 區塊產生一 PI徵狀值; 一 ECC解碼器,用以根據該PI徵狀值以及該p〇徵狀值其中至少 之一施行一 ECC動作;以及 一 EDC更正器,用以根據該ECc動作之結果更正該EDc結果。 8. 如申请專利範圍第7項所述之錯誤更正系統,其中該p〇徵狀 值產生器根據該記憶體元件内的該ECC區塊產生該p〇徵狀 值,然後該ECC解碼器根據該p〇徵狀值對該記憶體元件内 的該ECC區塊施行一 p〇 ECC動作。 9. 如申請專利範圍第7項所述之錯誤更正系統,其中該PI徵狀值 產生器根據該記憶體元件内的該ECC區塊產生該PI徵狀 值,然後該ECC解碼器根據該pi徵狀值對該記憶體元件内 的該ECC區塊施行一 PIECC動作。 1〇·如申請專利範圍第7項所述之錯誤更正系統,其中該原始資料 係儲存在一光碟片中。 U.—種錯誤更正方法,包含: (a)接收和解調原始資料以產生一 ECC區塊; 48 (b) 對來自該步驟(a)的該ECC區塊施行一PIECC動作以產生— 更正後ECC區塊; (c) 儲存該ECC區塊和該更正後ECC區塊; (d) 根據該步驟⑹儲存的該ECC區塊施行一非線性EDC動作以 產生一 EDC結果; ㈦根據該步驟⑹儲存的該ECC區塊之一 PI碼字以及一 p〇碼字 產生至少一徵狀值; (f) 根據該徵狀值施行一 ECC動作;以及 (g) 根據該ECC動作之一結果更正該EDC結果; 其中該徵狀值包含一 PI徵狀值以及一 P〇徵狀值其中至少其一。 12. 如申料概_ u項職之錯誤更正方法,更包含在該步 驟(e)中儲存該徵狀值。 13. 如申請專利範圍第u項所述之錯誤更正方法,更包含一步驟 (al):儲存來自該步驟⑷的一部份該Ecc區塊。 14. 如申請專利範圍第13項所述之錯誤更正方法,更包含在被該 步驟⑻處理完後儲存該_ (al)鱗的該一部份咖區 塊。 15. 如申請專利範圍第12項所述之錯誤更正方法,其中該步驟⑹ 產生被儲存的該K)徵狀值,該步驟幅生該ρι徵狀值, 49 1334132 且該Η徵狀值和該P〇徵狀值被儲存至不同的儲存元件 16. 如申請專利範圍帛15項所述之錯誤更正方法,更包含. 儲存該步驟(b)所產生的該PI徵狀值。 17. —種錯誤更正方法,包含: (a)接收和解調原始資料以產生一 ECC區塊; ⑼對來自該步驟⑻的該ECC區塊施行一 piEcc動作以產生— 部份ECC區塊; (c)儲存該ECC區塊以及該部分ECC區塊; ⑼對該步,驟⑹中儲存的該ECC區塊施行一非線性丑加動作以 產生一 EDC結果; (e)根據該步驟(c)中儲存的該部份ECC區塊之p〇碼字產生一 P0徵狀值; ⑺根據該步驟(C)中儲存的該部份£〇::區塊產生一珂徵狀值; (g) 根據該PI徵狀值以及該P0徵狀值其中至少其一對該步驟(c) 中儲存的該ECC區塊施行一 ECC動作; (h) 根據該步驟⑹中儲存的該一部份ECC區塊產生該PI徵狀 值; (1)根據該ECC動作之結果更正該EDC結果。 18·如申請專利範圍第17項所述之錯誤更正方法,其中該步驟(g) 產生該PO徵狀值,然後該步驟(i)根據該p〇徵狀值施行該 50 1334132 ECC動作。 19.如申請專利範圍第17項所述之錯誤更正方法,其中該步驟⑴ 產生該PI徵狀值,然後該步驟(h)根據該PI徵狀值施行一 PIECC動作。 20.如申請專利範圍第17項所述之錯誤更正方法 料係儲存在一光碟片中。 ,其中該原始資 十一、圖式: 511334132 X. Application for Patent Park: 1. A error correction system, comprising: a demodulator, rib receiving and thawing start data to generate -ECC block; pre-PIECC solution to the mother, consumption to the demodulator, Performing a PIECC action on the ECC block from the demodulator to generate a corrected ecc block; a data buffer for storing the ECC block and the corrected ecc block; the non-line EDC is confirmed Means for performing a non-linear EDC action based on the / ECC block in the data buffer to generate an -edc result; a syndrome generator for utilizing the ecc region stored in the data buffer One codeword of the block to generate at least one syndrome value; - an ECC decoder for performing an Ecc action based on the syndrome value; and an EDC Corrector' for correcting the edc result according to one of the ECC actions; The syndrome value includes at least one of a PI symptom value and a p〇 symptom value, the code word including at least one of a PI code word and a P0 code word. 2. The error correction system of claim 1, further comprising a memory component to store a portion of the ECC block from the demodulator. 3. The error correction system of claim 2, wherein the portion of the ECC block stored in the memory component is stored in the data buffer after being processed by the pre-picc decoding piano. Device. 46 4. If the error correction system of the patent of the application of the second patent, the symptom generator generates the PQ symptom value stored to the signature value, and the pre-PIECC solution The woven memory is buffered to the data buffer, whereby the ECC decoder corrects the 〇 〇 来自 value from the syndrome memory and the PI sigma value from the data buffer. 5. The error correction system of claim 4, further comprising: - a symptom value memory for storing the PI symptom value generated by the pre-pi ecc decoding set; wherein the ECC decoder is based on The ρι symptom value in the ρι symptom value memory performs the Ecc action on the ECC block. 6. The error correction as described in item 1 of the patent application, wherein the original data is stored in a disc. a error correction system comprising: a demodulator 'to receive and demodulate the original data to generate an ECC block; a pre-PIECC decoder to which the demodulator is lightly coupled to the demodulator The ECC block performs a Ε χ (χ action to generate a corrected ECC block; - food easing) to store the ECC (1_ and the corrected Ε χ χ χ — — — — — — — — — — — 件For storing a portion of the ECC block from the data buffer; a non-linear EDC confirming device for applying a non-linear EDC action to the ECc block in the data buffer to generate an -EDc result 47 1334132 A PO symptom generator 'for generating a P〇 value according to the P0 code word of the part of the Ecc block in the memory element; a π syndrome generator for Generating a PI symptom according to the part of the ECC block stored in the memory component; an ECC decoder, configured to perform an ECC action according to at least one of the PI symptom value and the p〇 symptom value; And an EDC corrector for correcting the ECC result based on the result of the ECc action. The error correction system of claim 7, wherein the p〇 syndrome generator generates the p〇 symptom value according to the ECC block in the memory component, and then the ECC decoder according to the p〇 syndrome The value is subjected to a p〇ECC action on the ECC block in the memory element. 9. The error correction system of claim 7, wherein the PI symptom generator is based on the memory element The ECC block generates the PI symptom value, and then the ECC decoder performs a PIECC action on the ECC block in the memory element according to the pi symptom value. The error correction system is described, wherein the original data is stored in a disc. U. - A method of error correction, comprising: (a) receiving and demodulating the original data to generate an ECC block; 48 (b) from the The ECC block of step (a) performs a PIECC action to generate - a corrected ECC block; (c) stores the ECC block and the corrected ECC block; (d) the ECC area stored according to the step (6) The block performs a nonlinear EDC action to generate an EDC result; (7) Generating at least one symptom value according to one of the ECC block and the p-code word stored in the step (6); (f) performing an ECC action according to the symptom value; and (g) operating according to the ECC A result corrects the EDC result; wherein the symptom value comprises a PI symptom value and a P〇 symptom value of at least one of them. 12. If the error correction method of the application profile is included in the step The symptom value is stored in (e). 13. The error correction method as described in claim 5, further comprising a step (al): storing a portion of the Ecc block from the step (4). 14. The error correction method according to claim 13 of the patent application, further comprising storing the portion of the _ (al) scale after processing by the step (8). 15. The error correction method of claim 12, wherein the step (6) produces the stored K) symptom value, the step of generating the ρι symptom value, 49 1334132 and the Η symptom value and The value of the P sign is stored to a different storage element. 16. The error correction method described in claim 15 is further included. The value of the PI symptom generated by the step (b) is stored. 17. An error correction method comprising: (a) receiving and demodulating original data to generate an ECC block; (9) performing a piEcc action on the ECC block from the step (8) to generate - a partial ECC block; c) storing the ECC block and the part of the ECC block; (9) performing a non-linear ugly action on the ECC block stored in the step (6) to generate an EDC result; (e) according to the step (c) The p〇 code word of the part of the ECC block stored in the block generates a P0 symptom value; (7) according to the part stored in the step (C): the block generates a symptom value; (g) Performing an ECC action according to the PI symptom value and the P0 symptom value at least one pair of the ECC block stored in the step (c); (h) according to the part of the ECC area stored in the step (6) The block generates the PI symptom value; (1) correcting the EDC result based on the result of the ECC action. 18. The error correction method according to claim 17, wherein the step (g) generates the PO symptom value, and then the step (i) performs the 50 1334132 ECC action according to the p〇 symptom value. 19. The error correction method of claim 17, wherein the step (1) generates the PI symptom value, and then the step (h) performs a PIECC action based on the PI symptom value. 20. The method of error correction as described in claim 17 is stored in a disc. , where the original capital XI, schema: 51
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