TWI332752B - Method and apparatus for loop control - Google Patents

Description

1332752 IX. Description of the invention: ‘Technical field to which the invention pertains. The present invention relates to electronic devices, and more particularly to loop control circuits and methods therefor. [Prior Art] Fig. 1A is a conventional optical storage device. In general, the data stored on the disc is subjected to a step of scaling and digitizing before being transmitted to the decoder to adjust the amplitude of the signal signal to a target value. Variable gain amplifier 102, digital converter 104 and automatic gain controller 106 form an automatic gain controller loop for adjusting the gain of optical signal #RF. The blank detector 110 provides an additional data path for detecting a blankness of the optical signal #RF, wherein the blank state of the optical signal #RF corresponds to at least one blank in a track on the optical disc. Burning sector. If the amplitude of the optical signal #RF is less than a critical value, the optical signal #RF corresponds to a blank state, so the decoder 108 does not start, and the corresponding disc recording sector returns blank. Unburned section. In contrast, if the optical signal # is not blank, the blank detector 110 transmits the coincidence signal signal #en to the decoder 108, causing the decoder 108 to be activated to output the data signal #DATA to the digital converter 104. Perform decoding processing. Figure 1B is a schematic diagram of defining a blank state. When the amplitude of the optical signal #RF is below the critical value (+th and -th), the corresponding record 0758-A32234TWF1 (20070615) 5 1332752 is considered a blank segment. In contrast, when the amplitude of the optical signal #1117 is the value of the over-critical value signal, the corresponding recorded segment is regarded as a non-empty segment, so the decoder 1 8 is activated to process the data signal #DATA. Figure 2 is a circuit loop control circuit conventionally used in electronic devices, such as optical storage devices. The loop loop control circuit mainly includes an automatic consisting of a variable gain amplifier (VGA) 202, a digital converter (ADC), a 204 'peak-to-valley detector 2〇6, and an automatic gain controller (agc) 2〇8. A gain control loop loop, and an offset control loop loop comprised of a variable gain amplifier 202 'digital converter 204, offset controller 21 〇 and adder 212. The variable gain amplifier 2 amplifies the received optical signal #RF and then transmits it to the digital converter 204. If the amplitude of the optical signal #卩 is not adjusted to an appropriate range, the digital converter 204 cannot correctly sample the optical signal #RF to generate a digital data (data signal) #DATA. Therefore, the automatic gain controller 208 adjusts the amplitude of the optical signal #RF by generating a gain value #@心11, and the gain value #§&11 is detected by the peak-to-valley detector 206. The results are determined. The automatic gain controller 208 changes the gain value #gain in a step size according to the threshold value and the valley value #PB output from the peak-to-valley detector 206. The entire gain control loop loop is recursively moved so that the amplitude of the digital data volume is gradually forced into the target value. Therefore, the size of the step is proportional to the convergence rate of the gain control loop. Similarly, the offset controller 210 detects the offset condition of the digital data #DATA and generates a panning signal #offset to compensate for it. Before the optical signal is sent to the variable 0758-A32234TWF1 (20070615) 6 1332752 gain amplifier 202, the adder 212 can directly compensate the translation signal #offset into the optical signal #RF, and the offset controller 21〇 is also used. In another step, the progressive signal recursively updates the translation signal #offset. Thereby, the entire loop loop control mechanism gradually corrects the offset condition of the optical signal #rf. Figure 3 is a waveform diagram for various situations. The figure shows that the optical signal #!^· obtained from the front end is not necessarily suitable for subsequent processing. For example, at stage ti, the optical signal #RF is smaller than the target value (positive target value + target and negative target value - target), and the gain control loop circuit gradually adjusts the optical signal #RF to approach the target value. In phase t2, the amplitude of the optical signal #rf exceeds the target value', so the increasing loop circuit will recursively adjust the amplitude to approach the target value. ^Section (4) is an example of offset compensation. The shift control loop loops through the feedback feedback to the wide-ranging gradual Dina optics (4) #RF, ensuring that the optical money is approaching the correct target value when transmitting the digital converter 2G4. However, the operation of the loop circuit takes time, the degree is too low, and the vibration of the optical signal Wei F is convergent. If the step is too large, the convergence speed: = the clock feedback mechanism will be unstable. Reduce signal quality. Therefore, how to adjust the signal received by 2^b04. Positive V step is a very important one. Please refer to Figure 4. Section 4 & Λ Schematic. As shown in Fig. 4, the section of the A-optical storage medium is taken from the inner ring to the outermost circle. 〇758-A32234TWFl (2〇〇7〇615) 7 1332752 is the inner drive area, and is imported. Lead-in zone, data zone, lead-out zone, and outer drive area. The internal drive zone includes different sub-zones such as an initial zone, an inner disc test zone, a count zone run-in, and an inner disc count zone. , an inner disc administration zone and a table of contents zone. The internal disc test area is used to provide optical storage for disc testing and optimized power control (OPC). The optical storage device emits a plurality of different marks by emitting laser beams of different powers to an internal disc test area of an optical storage medium. Then, the reproduced signal signal obtained by reading these marks is captured as reference information for adjusting the transmission power. Therefore, the optical storage device can control the emitted laser beam to have the best emission power. The Lijia power is generated based on the waveform asymmetry of the §fl signal reproduced from the recorded data. In the prior art, the waveform asymmetry of the recorded data reproduction signal is measured in an analogous manner, and thus requires more layout space and more complicated design. When the data burn density of a CD-ROM (such as a DVD-ROM) or a recordable disc (such as a DVD-RAM) becomes more and more south, the servo error such as tilt or mis-track will seriously affect the quality of the signal. Especially in recordable discs, the servo error that occurs during green burning will affect the green quality, and the servo error will be seriously affected during a suitable part of the regeneration of 0758-A32234TWF1 (20070615) 8 1332752 (reproduction). The quality of the signal. * On DVD-RAM discs, 'Information is burned green in the way of including Land Track and Groove Track, while Land Track and Groove Track are on The disc rotates - the circle (360°) will alternate with each other. The Land Track and the Groove Track are used at the beginning to guide the tracking guide to reduce interference between the high density and narrow tracks. Each track includes a plurality of sectors having the same degree. When you create a disc, the header area is embedded between the sections. The physical address of the segment is recorded in the header area. Each section includes a data area and a header area for recording physical identification data (PID). Fig. 5A shows the physical shape of the relief of the DVD-RAM disc, and Fig. 5B shows the waveform of the read channel 1 signal. Here, the header area is repeatedly set in each section of each track. Four physical identification materials (PID 1 to PID4) having the same value are recorded in a header area. The physical identification data PID 1 and PID 2 are set at the detachment center, and the physical identification data PID3 and PID4 are set at the detachment center in the opposite direction to the physical identification data PID1 and PID2, and thus The laser spot 500 is out of the center of the road and the physical identification data (PID1 to PID4) can still be read correctly. The read channel 1 signal shown in Fig. 5B can be obtained by the embossing, wherein the symbols ISHD1, ISHD2, ISHD3, and ISHD4 are divided into c S) 0758-A32234TWFl (20070615) 9 1332752 .. (variable-frequency k oscillator, VFO) The DC valley of Headerrl, Header2, Header3, and Header4 of the header area. Similarly, the physical identification data (PID1 to PID4) is placed opposite to the relief in the concave pattern, and the 6A is the physical shape of the concave track of the DVD-RAM disc, and the 6B is shown in The waveform of the read channel 1 signal is read by the concave pattern. Fig. 7 is an enlarged view showing the header area #· field shown in Figs. 5A and 5B. In the structure of the header area, the physical identification data PID1, PID2, and the physical identification data PID3 and PID4 are disposed in opposite directions at a certain quantitative position from the center of the track. The ID signal of the VFO signal for synchronizing and detecting the ID signal and having a specific frequency and the physical address of the display section are respectively recorded in each physical identification data. The VFO signal has a recording format of 4T (T is the period of the clock signal) ). As shown in Fig. 7, the 'header area' includes the VF01 area 701 and the PID1 702, the VF02 area 703, and the PID2 704, the VF03 area 705, and the PID3 706, the spring and VF04 area 707, and the PID4 708. In Fig. 7, when the laser spot 700 passes through the header area of the pit track, the read channel 1 signal #1$ as shown in Fig. 8 can be obtained. In Fig. 8, the VF01 signal 802 corresponds to the VF01 area 701 of Fig. 7, and the VF03 signal 803 corresponds to the VF03 area 705 of Fig. 7. Figure 9 shows a conventional device for detecting the center error and tilt error of a DVD-RAM disc. The peak detection circuit 901 detects the peak value of the read channel 1 signal #RF and generates a peak signal, and the valley value is 0758-A32234TWFl (20070615) 1〇1332752 - the detection circuit 902 detects the valley value of the read channel 1 signal #RF And produce a valley value. Signal. The sample and hold circuits 903A and 903B sample the peak and valley signals of the regions VF01 and VF03, respectively, and store the sampled signals until they are sampled by the digital to digital converters (ADC) 905A and 905B. Among them, the digital converters 905A and 905B are analog converters of a low sampling rate. The track center error detector 907 calculates the track center error based on the peak values and valley values sampled by the digital converters 905A and 905B. The tilt error detector 909 calculates the tilt error based on the valley value sampled by the_bit converter 905B. However, since the sample and hold circuits 903A and 903B are analog circuits, they are inferior in accuracy compared to digital circuits. Furthermore, the number of samples of the sample and hold circuits 903A and 903B is limited by the switching frequency. Therefore, it is very difficult to use the sample and hold circuits 903A and 903B to detect the channel 1 signal #RF more frequently in a short time, thereby reducing the detection accuracy. To detect channel 1 signal #RF more frequently, a more complex sample-and-hold circuit must be used. However, this will result in the cost and size of the device used to detect the center of the DVD-RAM disc and the tilt error. SUMMARY OF THE INVENTION The following examples specifically illustrate how the invention can be implemented in a preferred manner. The examples are for illustrative purposes only, and are not intended to limit the scope of the invention. The actual scope is subject to the scope of the patent application. One of the embodiments is an optical storage device for obtaining optical signals for loop control from a light 0758-A32234TWF1 (20070615) 11 1332752. The inclusion of a -variable booster amplifies the optical signal based on the gain value. A peak detector detects a peak and a valley of the amplified optical signal. The controller compares the bee value with the valley value and the threshold value to control the shouting. - The signal control loop updates the gain value based on the material value and the first step of the valley. The first step is regulated by the first control signal of 5 hai. Alternatively, the optical storage device can include a digital converter that uses/takes (four) the output of the variable gain amplifier to generate a data signal. = peak capture detector system, according to the data signal to find the peak and the valley value 0 σ yoke example, the signal control loop includes an automatic gain control, the mode controller includes a "first" comparator and Comparing the peak value and the valley value with a positive high threshold and a negative high threshold, the first mode judges the first comparator and the second one. If the peak exceeds the positive high threshold, the second true value is otherwise output - a false value. If the valley value is low, the second comparator outputs a constant value, otherwise the output is two if the first comparator and the second comparator simultaneously output a true mode determiner to output the first control signal to the automatic gain controller. . ^ Λ The first state further compares the peak value with a positive low threshold value and the second critical value is lower than the positive high critical value. Similarly, the second mouth and mouth compare the valley value with a negative low threshold value, the negative low is 0758-A32234TWF1 (200706 i 5) 12

: /JZ Negative high two-boundary value, the value is lower than the positive low-thickness corner output a true value, otherwise the output-false value. If the threshold is low, the second comparator outputs a straight value, and the output is ::: if the first comparator and the second comparator simultaneously output the first control signal to the second f mode The determiner can be - and gate. Add ": control signal is - true value". The automatic gain controller is added to accelerate the gain control loop formed by the variable gain amplifier, the digital converter and the automatic basin controller. In another example, the signal The control loop includes the following components: The taste shift controller detects the offset of the data signal, and generates an offset-off edge optical (4) offset. The adder updates the optical signal by a translation signal before the optical signal variable gain amplifier. The wide control 11 generates a first control signal according to the peak value of the peak value (four) and the threshold value. The translation signal is based on a second eve 'new' and the second step is determined by the second Control signal adjustment. In the money controller, the -th comparator compares the peak value with a positive height' - the second comparator compares the valley value with the - negative high threshold value: the second mode determiner is coupled The first comparator and the second comparison output. If the peak exceeds the positive high threshold, the first Μ output is - true value 'otherwise output - false value. If the valley value is lower than the negative threshold Value 'the second comparator Output - straight value, otherwise output a false value. If the first comparator and the second comparator have its t - output true 07 58-A32234TWF1 (20070615) 13 1332752 value 'the second mode judgment! I output the first Second control signal to the control benefit. The second mode determiner is a gate (〇R) or a mutual exclusion gate (XOR). If the first control signal is a true value, the control = increase the number Two steps to accelerate the translational control loop formed by the variable gain amplifier, the digital conversion bias controller, and the adder. Another embodiment proposes a loop control method implemented in the above optical storage device. Although the present invention is preferred The description of the embodiment is as above.

It is understood that the scope A of the present invention must be so limited. It is only in the scope of the second = cover that is obvious to the same spirit or to those skilled in the art. Therefore, the scope of patent claims must be the most extensive: [Embodiment] The preferred embodiment (4) according to the present invention will be described below. It is to be understood that the invention has been described by the invention of the invention It is not intended to limit the scope of the invention. 々 $槿; an embodiment of a picture optical storage device. This embodiment: 5: in the. Blank controller! (4) Using the data signal #DATA from the digital conversion ^DATA to detect the blank state, thereby saving the circuit cost on the blank fine U0 data path shown in Fig. = Chatting the way of reading the bit circuit, the cost is lower than the electricity:;; In the L1A picture, the data converter of the digital converter outputs atI to the automatic touch (four) ϋΠ) 6, and the self-ride (four) 0758-A32234TWFl (20070615) 14 1332752 A control signal signal #ctrl to variable gain amplifier 1 〇2 to adjust the gain value of optical signal #RF. Thereby, the size of the signal #DATA gradually approaches a target value during the recursive adjustment. Since the size of the data signal #1) has been changing, the blank detector i 〇2〇 may judge the error. In order to ensure correctness, the present invention proposes a threshold signal generator 1010 for providing a dynamic threshold signal #th proportional to the control signal #; #ctrl. The threshold signal #th is also amplified when the data signal #dΑΤΑ is amplified, so that the function of the blank detector 1〇2〇 detecting the blank state is not affected by the gain of the variable gain amplifier 1〇2. If the blank state continues for a while, the automatic gain controller loop may gradually amplify the gain of the optical signal #RF to approach the value of the target, forming a divergence phenomenon that we are not happy with. Therefore, there is another function in the blank detector 102G to solve this problem. If the size of the data apostrophe #DATA does not exceed the threshold value signal #th, it indicates that the optical signal signal #RF is in a blank state. At this time, the blank detector deletes a pause signal #hold to the automatic gain controller 1〇6, and commands it to pause the update control sfl唬k 5l; #ctd. In this way, the gain of the optical signal #RF in the blank state can be kept constant. At the same time, the blank debt test is still going on. When the data signal #DATA is found to be non-blank, then the automatic gain control H 1 () 6 is restarted, and the control signal signal #ctrl is continuously updated to restore the function of the automatic gain controller loop. The 11A diagram is an embodiment of the threshold signal generator view in Fig. 10. Figure 11B shows the relationship between the gain and the control signal. The threshold value signal #th is substantially equal to the increase in the variable gain amplifier ι〇2, 0758-A32234TWFl (20070615) 15 1332752, which is proportional to the control signal signal. To simplify the implementation of the critical, signal generator 1010, a digital circuit can be employed to generate the linear relationship in a four-way operation. In Fig. 11B, a curve z represents a gain value generated by the variable gain amplifier 102 based on the control signal signal #ctrl. The straight line sum and the representative threshold signal generator 1010 use a curve to generate the threshold signal #th. The threshold signal generator includes an adder 1106, a controller 1102 and a multiplier 1104. The straight line yi and can be expressed as yn=anx+bn where η is an integer, an is the slope, and 匕 is the offset value. In Fig. 11A, the controller 11〇2 generates a slope value #sl〇pe and an offset value #〇ffset according to the size of the control signal signal #ctH. Multiply state 1104 then multiplies control signal red (7) by slope value #si叩 and multiplies the result to adder 1106, which is added to offset value #〇ffset to produce = boundary value L##th. The size of the control ^##tritri can be divided into a plurality of ranges. The range of the mother corresponds to a different set of slope values and offset values. For example, in the UB diagram n is equal to 2, so use two straight lines to approximate the curve z. When the size of the control signal #ctrl is the first range, the control U 102 generates the slope value ai and the offset value. When the size of the control signal #ctrl is the second range, the controller 11〇2 generates the slope value &; and the value of the offset value by n is not limited to 2, and the larger the number, the more accurate the approximation result. In addition, the threshold signal generator ι〇ι〇 can also check the digital table by 3 digits, the query table contains different control signal signals red juice 1, and its corresponding different threshold signal #also. The curve z-pass 〇 758-A32234TWF1 (20〇70615) 16 1332752 is usually determined in the conventional calibration procedure, so the setting of the threshold signal generation β 1010 can also be set at the time of calibration. Fig. 12 is an embodiment of the blank detector 1〇2〇 in Fig. 10. The blank detector 1 〇 2 〇 includes three digital components, a high pass filter 1202, a hysteresis 12 〇 4 and a counter 12 〇 6. The high pass filter 1202 filters the low frequency components of the data signal signal #DATA, leaving a high frequency portion. The hysteresis element 12〇4 is coupled to the high-pass filter • Π02, and quantizes the 5 haibe signal #£) 八1^ into a 幵v type of a square wave signal, which has only two states, 〇 and ,, each having a different Work cycle (duratlon). The counter 丨2〇6 counts the working period of the square wave signal to generate a count value, and uses the count value to determine whether the blank state of the optical signal #rf is established. The threshold value signal #th can be input to the hysteresis element 12〇4 to adjust the sensitivity of the square wave signal generation. When the high-pass filter 12〇2 outputs the bedding material #唬#〇八丁入, the low-level signal signal is output when the amplitude magnitude is lower than the amplitude corresponding to the threshold value signal #th, and the high-pass filter 1202 outputs the data signal sharply. When the size of the Dingba money is higher than the amplitude corresponding to the threshold signal age, the high level signal is output to form the square wave signal. The counter makes it possible to judge the blank state when the low-order square wave signal is detected when the duty cycle of the square wave signal is counted. When the count ϋ 1206 detects the high quasi-square wave signal, it is judged to be a non-blank state, and the enable signal signal is sent (3) to activate the decoder 108, so that the decoder 108 starts decoding the data signal #〇八八八deal with. 0758-A32234TWF1(20〇70615) 17 1332752 In the other way, the threshold value signal #th can also be input to the count • !2〇6, which is used to change whether the blank state is true or not. In the case of a cow, if the count of the low-order quasi-square wave signal is detected at the critical value-expected value, (4) the break is empty ^ fear three counts $1206 to detect the high quasi-square wave signal, ie It is judged as the center of the heart and sends the enabler jg##en to start the decoder 1 〇8, and the decoder —1G8 starts the decoding process of the #material signal#DATA. Figure 13 is a diagram showing the waveform change Φ of the actual application of the present invention. In the U stage, the size of the information signal letter lion does not exceed the threshold value of her, so the optical signal #RF is reported as a blank state, and the automatic gain controller 1G6 is suspended by the control of the pause signal #hold, so that The threshold value signal #th remains unchanged. In the t2 phase, the data signal #D ATA exceeds the threshold signal, so the automatic gain controller loops back to operation. Gradually, the #signal ship is zoomed in to approach the target value (+-target). At the same time, the threshold value signal #th is also amplified as the gain of the data signal #DATA becomes larger. In the 〇 phase, the size of the data signal #DATA is less than the threshold value signal #th, meaning that it enters another segment = white state. It is worth noting that the critical value signal #th at this time is also higher than the critical value signal # at the u stage. If the threshold signal # is not dynamically adjusted, the data signal #DATA of the t3 stage may be erroneously judged to be a non-blank state by the fixed critical ^ signal # t h . Since the 13th stage has been judged to be blank, the automatic gain controller circuit enters the pause state again, so that the critical value signal # is maintained at a constant value as with the gain of the variable gain amplifier 1〇2. In the t4 phase, it indicates that the data letter has exceeded the condition of 0758-A32234TWF1 (20070615) 18 1332752 ::: 'So the operation of the automatic gain controller loop recurs, so when the question is asked, the threshold value signal #th ” The profit fell. The above example illustrates that the present invention dynamically adjusts the threshold value signal #th to avoid erroneous judgment results. The third diagram is a flow chart for measuring the blank state. Hired in steps

If:!, the bulk 1〇2 光学 光学 光学 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据 根据In step 14〇6, the automatic gaining controller updates the control signal signal (4) according to the data signal #DAT. In the step just after, the threshold signal generator ι〇ι〇 provides a threshold value according to the control signal. In step i4i, the blank detector deletes the blank state of the data signal #DATA according to the threshold signal. In step 1412, if the data signal ^DATA is not blank, the decoder 108 is activated to the data signal # DATA is decoded. In step 1414, if the data signal #DATA is blank, the blank detector 1〇2〇 turns off the decoder=8' and suspends the operation of the automatic gain controller 1〇6 to make the automatic gain control benefit The loop circuit does not operate. Figure 15 is a circuit loop control circuit according to an embodiment of the present invention, wherein the control loop circuit can be applied to an optical storage device for looping an optical signal signal obtained from an optical disc. Loop control, the optical signal signal carries corresponding data, but the invention is not limited thereto. Variable gain amplifier 2〇2 'digital converter 2〇4, peak valley The detector 206 and the automatic gain controller 208 form a signal signal 758-A32234TWF1 (20070615) 19 1332752 唬 control loop circuit that controls the gain of the digital data #DATA. The mode controller 1500 determines the relative state of the threshold and the amplitude, The steps used in the automatic gain controller 208 and the offset controller 21A are adjusted to produce whitening. The variable gain amplifier 202 amplifies the optical signal #RF' according to the gain value #gain and the digital converter 204 analog-to-digital conversion The device 204 samples the amplified optical signal #尺1? to generate the digital data #DATA. Subsequently, the peak-to-valley detection benefit 206 detects the large and small peaks and valleys in the digital data #dΑΤΑ. The mode controller 1500 determines the Whether the peak exceeds the positive high threshold + Hth. The positive threshold + Htll can be a value greater than or equal to the positive target value ♦ target. Similarly, the negative high threshold _Hth is a value less than or equal to the negative target value -target. The optical signal #RF is over-amplified by the variable gain amplifier 202 such that the peak exceeds the positive high threshold + mh and the valley is lower than the negative critical value -Hth 'the mode controller 1500 issues a first control The signal signal #〇1:1*11 notifies the automatic gain controller 2〇8 to increase the step of progress, and the gain is updated according to the peak value and the bottom value #1^ and the adjusted step φ step, thereby making The convergence speed of the gain control loop circuit is in the loop loop control circuit, the variable gain amplifier 2〇2, the digit converter 204 'offset controller 210 and the adder 212 form another signal signal control loop loop for performing Offset compensation. If only the peak or valley value exceeds the target value (positive target value or negative target value - target), it means that the offset shown in stage 妃 and t4 in Fig. 3 has occurred. Similarly, the mode controller 15 determines whether or not the offset occurs by the positive high critical value + Hth and the negative high critical value - Hth. If an offset is detected, a second control signal signal #ctrl2 is issued to notify the offset control 0758-A32234TWFl (20070615) 20 丄 332752 . . 210 increases the step of stepping, which speeds up the convergence of the offset control loop. Then, according to the digital data #DATA and the adjusted step progression, the translation signal signal #Gff yarn adder 212 is calculated between the offset control: ?1〇 and the variable gain amplifier 2〇2, which is responsible for first shifting the signal. The U#offSet is compensated to the optical signal #RF before being sent to the variable gain amplifier 202 for amplification.

Above, Fig. 16 is an embodiment of the mode controller 1500 in Fig. 15. j The mode controller includes - a comparator -6i〇 and a first-comparator (10), each comparing the peak valley value with the positive high threshold value Hth. If the peak exceeds the positive high, i.笫 2: What? The device 1610 outputs a true value, otherwise the output-false operator determiner 1640 is coupled to the outputs of the first comparator 1610 and the second coffee. Similarly, if the valley value is lower than the negative high threshold value - the light two comparator 1620 outputs a true value, and vice versa, a false value is output. When Tian Guangzi (4)#RF is over-amplified; =20 will output a true value, and the first-mode is judged; the tiger signal #can is output to the automatic gain controller 208. The second determiner 1640 may be - or _, and the control mode of the control signal signal rU may be === the operation mode can be switched to -2=. If the control signal signal #speed mode is used, the automatic gain controller 208 sets the step value of the step to 1 as the value of the table =. Relatively, admonish. Strolling/sighing is a larger normal mode / 1: wide control signal letter " for. In the expression, the value of the step of step is set to a value smaller than -. In addition, the second 0758-A32234TWF1 (20070615) 21 1332752, the type determiner 1630 is also coupled to the output of the first comparator 1610 and the second comparison =^62〇. When the offset occurs, only one of the first comparator 1610 or the first comparator 1620 outputs a true value, at which time the second mode off state 1630 issues a second control signal #ctrl2 to the offset controller 210. In the present embodiment, the second mode determiner 163 is a mutual repelling gate (XOR). However, it is also possible to use the or gate (〇R). On the other hand, when the amplitude of the digital data #DΑΤΑ is too small, the acceleration mode is also triggered. For example, the first comparator 161 can compare the peak with a positive low threshold + Lth below the target value, and the second comparison 1620 also lowers the valley with a negative lower than the negative target. Threshold - Lth comparison. If the peak value is lower than the positive low threshold + Lth, the first comparator 1610 outputs a true value, otherwise a false value is output. If the valley value is higher than the negative low critical value -Lth, the second comparator 162 outputs a true value. When the digital data #〇人丁人 amplitude is too small, causing the first comparator 161〇 and the second comparator 1620 to simultaneously output the true value, the first mode determiner 164〇 issues the first control signal signal #ctrll having a value of one. The automatic gain controller 20 8 is activated to initiate the acceleration mode. The positive low threshold + Lth and the negative low threshold can also be used in the judgment of the offset. Figure 17 is a waveform diagram generated under the embodiment of the present invention. Stage tl displays a number of digits below the target value and zooms in to the target value in two stages. When the peak is below the positive low threshold + Lth, the automatic gain controller 208 operates in the acceleration mode, so the slope of the envelope is steep. The change principle and peak value of the valley value are the same because of the symmetry. As the amplitude of the digital data #DATA increases, the peak value exceeds the positive low threshold +uh 0758-A32234TWFl (20070615) 22 1332752 Zhuo I 2: The gain control loop loop returns to the normal mode, so the ^, slow slope is displayed. The step-adjustment adjustment allows the gain control loop to converge quickly when the amplitude is significantly different from the target value and to maintain stability when the target value is approached. The western stage t2 shows a digital data higher than the target value #1) 八丁人, the step of approaching the target value is divided into two stages. First, when the peak value of the digital data #DATA spoon has passed the positive threshold, the automatic gain controller 208 = is in the acceleration mode, and the slope is steeper. As the gain loops back and forth, the amplitude of the digital data #data drops to a positive high threshold + Hth, so the gain control loop returns to normal 2, approaching the target with a gentle slope. The positive high threshold +Hth can be specifically the same value as the positive target value +target (the negative high threshold value -Hth and the negative target value _target are also the same), so that the over-amplified digital data #DΑΤΑ will only be performed in the acceleration mode. convergence. Stage t3 shows the status of the offset. The valley value is lower than the negative target value garget, but the peak value does not exceed the positive target value. The offset controller 210 of Fig. 15 adds the translation signal #〇ffset value to the optical signal #RF to compensate for these offsets. It can be seen from the figure that when the valley value is lower than the negative high threshold value -Hth, the offset controller 21 is operated in the acceleration mode by the trigger of the second control signal signal 2, and the slope of the envelope is steep. The offset condition may occur in combination with over-amplification or under-amplification, so the automatic gain controller 208 and the offset controller 21 may alternate to achieve the target value. P white ^ and t4 疋 another example of offset. The peak value exceeds the positive target value. 0758-A32234TWF1(20070615) 23 ij32752 +iarget but the valley value does not exceed • The high threshold value +Hth is the negative value -tet. Compensation is made when the peak value drops to positive. Finally, at time two ===: Step 1: The middle diagram is a flow chart of the loop control method of the present invention. Benefit control. If H system 11208 is required to determine whether it is necessary to add - L step (10) 4, _ peak and valley value for ί. If the bee value is higher than the positive high threshold value and the valley is at the negative critical value -Hth, then in step 18〇6, the automatic gain controller, 208 uses a higher step progression order to determine the value of the dish #gamma. ^ Then, in the step of deleting the normal mode 曰 _ 中 ' If the value is lower than the positive low threshold gamma and valley = :; negative low ^ boundary value pick, will also start the acceleration mode. At step (8) 〇 =, the offset controller 2H) determines whether offset compensation is required. If the letter is OK, step 1812 determines the mode of operation. If peak or . If the value exceeds the positive high threshold + Hth / negative high threshold ship, the acceleration mode is performed in step 1818. Otherwise, the normal mode is performed in step i8i4. When all the steps are completed, the program returns to step 18〇2. - Please refer to Figure 19. Figure 19 is a schematic illustration of an asymmetry measurement device, i i (10), in accordance with one embodiment of the present invention. The asymmetry measuring device 1900 includes a signal signal adjusting module 191A, a digital converter 1904, a detecting unit 1905, an asymmetry calculating unit 19〇6, and a comparator 1907. The signal signal adjustment module 191 is used to adjust the clock 07S8-A32234TWF1 (20070615) 24 1332752 recorded data reproduction number 彳 s number S1; the digital converter 1904 is connected to the signal signal adjustment module 1910 for the adjusted record data The regenerative signal signal si is converted into a digital signal signal S2, and the detecting unit 19〇5 is coupled to the digital conversion benefit 1904 for detecting a plurality of values of the digital apostrophe S2 according to a control signal c2. For example, when the control signal signal is at the level of the level, the detecting unit 19〇5 detects a plurality of values of the digital signal signal S2; otherwise, when the control signal signal C2 is at the low level, the detecting unit 1905 does not detect A plurality of values of the digital signal signal S2 are measured. The plurality of values of the digital signal signal S2 include the peak value, the bottom value, and the average value of the digital signal signal S2. The asymmetry calculation unit 19〇6 is coupled to the detection unit 1905 to calculate the asymmetry value of the digital signal signal S2 according to the plurality of values obtained by the detection unit 1905. The comparator 19〇7 compares the asymmetry value obtained by the asymmetry calculation unit 1906 with a predetermined value ρι to obtain a comparison result. Therefore, the optical storage device can adjust the power of the emitted laser beam based on the comparison result. The 汛唬彳§ adjustment module 191〇 includes an offset (〇ffset) unit 1901, a variable gain amplifier (VGA) 1902, and an equalizer 19〇3. The offset unit 19〇1 is coupled between the recorded data reproduction signal signal S1 and the variable gain amplifier Ϊ902 for adjusting the offset value of the recorded data reproduction signal signal si, and the variable boosting amplifier 1902 is used to amplify the adjusted record. The data reproduction signal signal S1; the equalizer 19〇3 is coupled to the wheel-out end of the variable gain amplifier 19〇2 for equalizing the amplified record data reproduction=signal 0758-A32234TWF1 (20070615) 25 1332752 Μ. . The operating bandwidth of the offset unit 1901 is adjustable and can be adjusted according to the control λ唬彳5唬ci. For example, when the control signal signal C1 is at the upper 2-bit level, the operation bandwidth of the offset unit 19〇1 can be set to the high-frequency broadband, and when the control signal signal C1 is at the low-level level, the offset unit 1901 The operating bandwidth can be set to low frequency broadband. The asymmetry values produced by the asymmetric leaf unit 1906 include, for example, beta values. The beta value can be generated according to the following formula: /^(Aj+A^Aj-AJ ' ApPK-DC and A2=BT-DC, where cold represents beta value, PK represents peak value, Dc represents average value, and BT represents valley value. In addition, in another embodiment of the present invention, the marks burned on the track of the optical storage medium have different lengths for different information messages. Therefore, the reclaimed money of the discipline material is different. The length markers also each have different physical characteristics. For example, the record data reproduction signal signal corresponding to the shorter length mark (short T mark), its peak 'valley or average value will be different from the longer length mark (long τ Marked record # material regenerative signal M. Therefore, the asymmetry value can be generated according to the following formula: asymmetry value = ((PKl + BTl) / 2 - (PKs + BTs) / 2) / (PKl_BTl), wherein PKl represents the peak of the corresponding long T mark, PKs represents the valley of the corresponding short τ mark corresponding to the long τ mark, and BTS code == τ mark, the valley value: in one embodiment, for example, the length of the blu_ray optical storage medium The T mark is 8T mark, and the blu_ray optical storage medium is marked as 2T mark. 75 8-A32234TWF1 (20070615) 26 1332752 In addition, the digital signal signal (4) can be provided for optical use as a lean material detection. Please refer to Figure 20 for display. Figure 20 is a schematic example according to the present invention. A schematic diagram of the asymmetry measuring device 2. The system is a non-intentional asymmetry measuring device according to the second embodiment of the present invention. The asymmetry measuring device is similar to the weighing stem. The measurement device only differs in that the asymmetry measuring device 2000 replaces the signal (9) adjustment module 1910 touched by the asymmetry measuring device in the figure as a signal signal adjusting module 2〇ι〇, ^ς =1= can be exactly the same. For the convenience of description, the related descriptions in Figure 4 are the same as those in the same paragraph. The signal signal adjustment module includes Qualcomm and Waves, 2G02 and equalizers. The wave device fiber is used to filter the low frequency noise of the poor material regenerative signal signal S1; the variable gain amplifier 2002 handle is connected to the high pass filter fiber for amplifying the output signal data regenerative signal signal S1; equalizer 2 〇〇3 is coupled to variable gain The output of the device 2002 is used to equalize the amplified record data regenerative signal S1. The fine operation bandwidth of the high-pass filter is adjustable, and can be, according to the ^_ ancient system. The hole number heart 5 tiger C1 Adjustment. For example, when the control signal signal Μ:·', "57" level is accurate, the operating bandwidth of the high-pass filter 2001 can be as follows: frequency see band '· vice versa when the control signal signal C1 is low level The operating bandwidth of the quasi-day Ding's main pass chopper 2001 can be set to low frequency broadband.

. 21st picture of the monthly multiple test. Figure 21 is a - timing diagram of the asymmetry measurement method of the present invention. In Fig. 21, the blank signal signal W 0758-A32234TWF1 (20070615) 27 Ϊ 332752 indicates whether the recorded data reproduction signal signal is generated from a non-empty area (such as a data area) of the optical storage medium. That is to say, when the blank signal signal bl is at a low level, 'representing that the recorded data reproduction signal signal is generated from the data area of the optical storage medium; when the blank signal signal bl is at the south level, the record data is indicated. The reproduced signal signal is not generated from the data area of the optical storage medium. Therefore, the control signal C1 can be generated based on the blank signal signal bl. In Fig. 21, when the blank signal signal Μ is at the low level, the control signal signal C1 is set to the low level after a first delay interval du. In this way, the operating band of the offset unit 1901 and the high-pass filter 2001 can be adjusted to the low band after the first delay interval dtl. In addition, the operating frequencies of the offset unit 1901 and the high-pass filter 2〇〇1 are both set to high frequency band 0. The control signal C2 (address flag signal signal) is generated according to the address of the optical storage medium. . In Figure 21, 'the recorded record between address i and address 2 (4) regenerative signal money S1 read (4) the corresponding power of the power of 1 is recorded on the optical storage medium; 2, the recorded data retrieving signal signal between the address and the address 3 is read from the corresponding value of the power of the power 2 recorded on the optical storage medium; the record taken from the wire 3 and the address 4 _ The data reproduction signal signal S1 is read from the corresponding mark recorded on the optical body by the power level of the power 3. Therefore, when the recorded data reproduction signal 2 1 is generated, the control signal signal is set to the high level level via the -stage delay. The control signal c2 is used to enable a plurality of values of the 0758-A32234TWF1 (20070615) 28 3 element 2 = bit signal signal S2. Such a symmetry value] 22 2 pairs of Qing 'corresponds to the power 2 does not come out. ^ The asymmetry value /53 of force rate 3 can be separately generated. The 帛22 diagram is the asymmetry of the invention: = map. Control signal signal. It is generated based on the address of the optical storage medium. Between the address 1 and the address 2 ' ′ ' ' 再生 regenerative signal signal S1 is read from the power record on the optical storage medium corresponding mark; in the bit ~ t address 3 The recorded data of the regenerated signal signal S1 is the power level of the second power 2 recorded on the optical storage medium. The address is 3 and the address is 4, and the record data obtained by ## The signal S1 is read from the corresponding mark recorded on the optical whole sub-media by the power level of the power 3. Therefore, after the record data reproduction signal is generated, after a second delay time, the control signal C1 is set to the low level. In this way, the operating frequency of the offset unit 19〇1 and the high-pass filter 2001 can be adjusted to the low frequency band when the control signal signal C1 is at the low level. In addition to this, the operating frequencies of the offset unit 1901 and the NAND pass filter 2 〇〇 1 are both set to a high frequency band. The control signal signal C 2 (address flag signal signal) is generated based on the address of the optical storage medium. Therefore, when the recorded data reproduction signal signal si is generated, the control signal signal c2 is set to the south level level after a delay. The control signal C2 is used to enable the detecting unit 1905 to detect a plurality of values of the digital signal S2. In this way, 〇758-A32234TWF1(20070615) 29 1332752 corresponds to the asymmetry value 0 1 of power 1, the asymmetry value corresponding to power 2 cold 2, the asymmetry value corresponding to power 3 cold 3 can be generated separately . The spirit of the present invention is to digitally detect a plurality of values of a recorded data reproduced signal signal and thereby calculate its asymmetry value. Therefore, the components used for detection and calculation can be easily designed. The apparatus and method for asymmetry measurement described above are merely exemplary embodiments for utilizing different power-coded record data reproduction signal signals to adjust the transmit power of the optical storage device without limiting the present invention to the above-described embodiments. The present invention is applicable to any write operation that dynamically adjusts power based on a pre-marked reproduced signal signal. Fig. 23 is a block diagram showing the track center compensation and tilt control of the optical disk according to the present invention. The optical pickup 2302 has a separate optical detector 2303' for detecting the intensity of the laser light and converting the detected laser light intensity into an electrical signal. Separate optical detection Is 2 3 0 3 can be divided into a given number of optical detection elements. As previously mentioned, a DVD-RAM disc has a signal consisting of a concave track and a embossed track, and the data can be read and written to the concave track and the ridge track or one of the concave and convex lines. Similarly, as shown in Fig. 7, there are interleaved header areas Header 1, Header 2, Header 3, and Header 4 at the beginning of each section. Therefore, when the DVD-RAM disc 2301 is set, or when the read/write operation is performed, the laser light emitted from the laser diode of the optical pickup 2302 will be projected onto the DVD-RAM disc 2301. The spot light of the predetermined state is supplied to the DVD-RAM disc 2301, and the laser light reflected by the signal track of the 0758-A32234TWF1 (20070615) 30 1332752 DVD-RAM disc 2301 is reflected to the optical detector 2303. Furthermore, when the spot passes through the header area (non-write area) of the DVD-RAM disc 2301, the optical detector 23〇3 is proportional to the intensity of the laser light detected and output by the optical detecting element respectively. The electronic signal generates a detection signal (optical signal) #RF. Therefore, the optical signal #1117 detected by the read channel 第 shown in Fig. 8 can be obtained. In order to convert the analog optical signal #RF into a digital signal by a digital converter (ADC) 2305, the signal adjustment module 2304 is required to adjust the signal level of the optical signal #RF to be in the working range of the digital converter 23〇5. And it is better to be located near the center of the working range. After adjusting the signal level of the optical ###RF, the signal adjustment module 23〇4 generates the adjusted optical signal #^^ and outputs it to the digital converter 23〇5. The signal adjustment module 2304 has an offset control device in accordance with an embodiment of the present invention. According to another embodiment of the invention, the signal conditioning module 23〇4 has a high pass filter (HPF). The digital converter (ADC) 2305 converts the analog optical signal #RF' with an offset adjusted to a digital signal SD. Detection circuit 2306 includes optical tilt error detector 2306A and track center detector 2306B. The detecting circuit 2306 detects the servo detecting signal according to the digital signal SD. The laser light reflected by the DVD-RAM disc 2301 may deviate from the preset path due to some tilting state, such as the tilt of the DVD_RAM disc 23〇1. The optical tilt error detector 23〇6A detects the DC valley value of the digital signal SD and generates an optical tilt error TL according to the detection result. According to an embodiment of the present invention, the optical tilt error TL at the center of the track can be obtained by 0758-A32234TWF1 (20070615) 1332752 ... Formula (1): * TL = [(ISHD1 + ISHD2) - (ISHD3 + ISHD4)] / 2I 〇 (1) Where ISHD1, ISHD2 'ISHD3, and ISHD4 represent the DC valleys of the VFO signal in Headerrl, Header2, Header3, Header4, respectively, shown in Figure 6B, and 10 is the DC level of the mirrored area. According to another embodiment of the present invention, the optical tilt error TL can be obtained by simplifying the formula (1) into the formula (2): TL = ISHD1 - ISHD3 (2) When the optical tilt error TL is obtained, the optical tilt error detector The 2306A outputs an optical tilt error TL. After being chopped by the low pass filter 2307A, the filtered optical tilt error TL is output to the tilt controller 2308. The tilt controller 2308 generates control signals TL to Ctrl to correct the incident angle of the light spot supplied to the DVD-RAM disc 2301 in accordance with the optical tilt error TL. The track control includes detecting an obedience error signal from an electronic signal generated according to a state of the beam and driving the optical track reader (actuat〇r) according to the obstruction error signal to move the optical pickup head. A target lens is in the radial direction of the disc, thus changing the position of the beam to track the target. According to an embodiment of the invention, the push-pull detector 2309 receives the debt measurement signal from the tracking channel and calculates the track error based on the detection signal of the channel. To compensate for the orbital error estimated by the 0758-A32234TWFl (20070615) 32 1332752 push-pull detector 2309, the track center debt detector 2306B detects the peak and valley of the digital signal SD output by the digital converter (ADC) 2305. And generate the center error TC according to the detection knot. According to an embodiment of the present invention, the track center error TC can be obtained by the formula (3): TC=(ISVFOHDl-ISVFOHD3)/(ISVFOHDl+ISVFOHD3) wherein ISVFOHD1 and ISVFOHD3 are VFO signals respectively in the header area shown in FIG. 6B The amplitude of Headerl and Header3. According to another embodiment of the present invention, the traffic center error TC can be obtained by simplifying the formula (3) into the formula (4): TC=ISVFOHDl-ISVFOHD3 (4) After obtaining the center error TC, the track center detection The 2306B outputs a track center error TC. After being filtered by the low pass filter 2307B, the filtered center error TC is output to the seek controller 2310. The tracking controller 2310 generates a control signal TC_ctrl to correct the position of the spot supplied to the DVD-RAM disc 2301 in accordance with the position of the track error estimated by the push-pull detector 2309. It must be noted that the optical tilt error TL and the track center error TC can be obtained from the VFO signals of the header areas Headerl and Header3, because the signals of the header area Header 1 and Header 3 are 〇758-A32234TWFl(20070615) 33 1332752 The amplitude is more uniform and easy to detect. However, the VFO signal of other header areas can also be used to detect the optical tilt error TL and the center error TC. Figure 24A is a block diagram showing a detection circuit 2306 and a digital converter 2305 according to an embodiment of the invention. Optical signal #RF is provided to signal conditioning module 2304 to adjust the signal level to the operating range of digital converter 2305. The signal conditioning module 2304 includes a variable gain amplifier (VGA) 2402, an offset controller 2403A, and an equalizer 2404. The variable gain amplifier 2402 adjusts the gain of the optical signal #RF. The offset controller 2403A adjusts the level of the optical signal #RF to the operating range of the digital converter 2305. The equalizer 2404 equalizes the optical signal #RF to produce an adjusted adjusted optical signal #11?'. Here, the operation bandwidth of the offset controller 2403A is adjustable, and the adjustment of the operation bandwidth is controlled by the control signal C4 provided by the clock generating means 2401. The digital converter 2305 converts the adjusted optical signal #1〇7' into a digital signal SD for detection by the detecting circuit 2306. The detecting circuit 2306 detects the digital signal SD output from the digital converter 2305 and provides the generated optical tilt error TL and the center error TC to the tilt controller 2308 and the tracking controller 2310, respectively. Here, the action of the detecting circuit 2306 to detect the digital signal SD is controlled by the control signal C5 provided by the clock generating means 2401. Furthermore, the offset controller 2403B offsets the digital signal SD to offset the difference between the junctions of the header regions Header2 and Header4 and other signal offsets. After shifting the digital signal SD using the offset controller 2403B offset 0758-A32234TWF1 (20070615) 34 1332752, the digital signal Sd is suitable for use as a signal prediction. Here, the operation of the offset controller 2403B offsetting the digital signal SD is controlled by the control signal C6 supplied from the clock generating means 2401. Furthermore, the output signal of the tilt controller 2308 or the seek controller 2310 can be suppressed or ignored according to the invalid signal INVALID. Figure 24B is a block diagram showing a detection circuit 2306 and a digital converter 2305 according to another embodiment of the present invention. The difference from Fig. 24A is that the offset controllers 2403A and 2403B are replaced by high pass filters 2403C and 2403D, and the elements denoted by the same reference numerals operate in the same manner. The operating range of the high pass filter 2403C is adjustable and is controlled by the control signal C4 provided by the clock generating means 2401. Furthermore, the high pass filter 2403D offsets the digital signal SD to offset between the junctions of the header regions Header2 and Header4 and other signal offsets. The digital signal SD is suitable for use as a signal guess after the high-pass filter 2403D is used to offset the digital signal SD. Here, the operating range of the high pass filter 2403D is adjustable and controlled by the control signal C6 provided by the clock generating means 2401. The clock generating means 2401 may include a clock generating unit to generate control signals C4, C5, C6 in accordance with a predetermined waveform, in accordance with an embodiment of the present invention. Fig. 25 is a timing chart showing the track center error and the tilt error according to an embodiment of the present invention. The signal IDGATE is a header prediction signal provided by the clock generating means 2401. When the signal IDGATE is at a high logic level, the optical pickup 2302 is located in the header area of the DVD-RAM disc 2301, and when the signal IDGATE is at the low logic level, 0758-A32234TWF1 (20070615) 35 1332752 optical pickup 2302 is located The data area of the DVD-RAM disc 2301. In order to offset the signal offset of the header area and the data area, the bandwidth of the offset controller 2403A and the high-pass filter 2403C is switched from the control signal C4 to the high working bandwidth 'and the offset controller 24〇3B and the high-pass 遽The bandwidth of the waver 2403D is switched from the control signal C6 to the high operating frequency. The bandwidth of the offset control 2403A and the local pass filter 2403C is set to a high operating bandwidth when the control signal C4 is at a high logic level, and is set to a low operating bandwidth when the control signal C4 is at a low logic level. The action of the control signal C6 is similar to the control signal C4, but differs from the header area Header 1 in that the control signal C6 is also set to a high logic level at the beginning of the header area Header3 to offset the header areas Header2 and Header3. Signal offset for data detection. Control signal C5 is at a high logic level in regions VFO1 and VF03. Detection circuit 2306 is enabled to detect peaks, valleys, and averages when control signal C5 is at a high logic level. After passing through the area VF03, the center of the mission and the tilt error can be calculated. Figure 26 is a timing diagram showing the invalid signal INVALID used to perform the track center error and the tilt error, in accordance with an embodiment of the present invention. When a detection error occurs, the clock generating means 2401 sets the invalid signal INVALID and transmits it to the tilt controller 2308 or the tracking controller 2310, or ignores the detection results of the tilt error detector 2306A and the track center detector 2306B. Figure 26 shows an example of a detection error. When control signal C5 is set and invalid signal INVALID is low logic level, as indicated by reference numeral 2600, invalid signal INVALID is set to suppress tilt controller 2308 or seek controller 0758-A32234TWF1 (20070615) 36 1332752 result 'or ignore tilt Error _ 2 test and track LT detect, then steal the detection result of 2306B. Although utrr is disclosed above in the preferred embodiment, it is not intended to limit the dry circumference of this month. Anyone who is familiar with the skill of the art and r fi allows a ^ to not fall away from the hair 4 and the dry circumference. Make a few changes and refinements, because the scope of protection of the = as attached, please define the patent scope as a simple description of the drawing. Figure 1A is a conventional optical storage device. The f 1B map is a schematic diagram defining a blank state. Figure 2 is a 35-turn control circuit used in conventional optical storage farms. Figure 3 is a waveform diagram for various situations. Figure 4 is a cross-sectional view showing an optical storage medium. Fig. 5A shows the physical shape of the ridge track of the DVD_RAM disc. Figure 5B shows the waveform of the read channel 1 signal displayed on the embossed track. Fig. 6A shows the physical form of the concave pattern of the DVD-RAM disc. Figure 6B shows the waveform of the read channel 丨 signal displayed on the concave track. Fig. 7 is an enlarged view showing the header area shown in Figs. 5A and 5B. Figure 8 shows the read channel 1 signal obtained from the 〇758-A32234TWF1 (20070615) 37 1332752 when the spot passes through the concave region of the concave pattern. Figure 9 shows a conventional device for detecting the track center error and tilt error of a DVD-RAM disc. The first diagram is an embodiment of an optical storage device. The UA diagram is an embodiment of the threshold generator in the first diagram. = Chart does not benefit and control signal signal #ctrl diagram. Figure 12 is an embodiment of a blank detector 1020 in Figure 10. The 13 diagram is a schematic diagram of the waveform change when the invention is actually applied. Figure 14 is a flow chart for detecting blank states. Figure 15 is a loop control circuit of one embodiment of the present invention. Figure 16 is an embodiment of the mode controller of Figure 15. Figure 17 is a waveform diagram generated under the embodiment of the present invention. Figure 18 is a flow chart of the loop control method of the present invention. Fig. 19 is a view showing an asymmetry measuring apparatus according to an embodiment of the present invention. Fig. 20 is a view showing an asymmetry measuring apparatus according to another embodiment of the present invention. Figure 21 is a timing chart showing the asymmetry measurement according to an embodiment of the present invention. Fig. 22 is a timing chart showing the asymmetry measurement according to another embodiment of the present invention. Figure 23 is a block diagram showing the track center compensation and tilt control of an optical disk according to an embodiment of the present invention. Figure 24A shows a block diagram of a detection circuit 0758-A32234TWF1 (20070615) 38 1332752 2306 and a digital converter 2305 in accordance with an embodiment of the present invention. Figure 24B is a block diagram showing a multi-circuit circuit 2306 and a digital converter 2305 according to another embodiment of the present invention. Fig. 25 is a timing chart showing the track center error and the tilt error according to an embodiment of the present invention. Figure 26 is a timing chart showing the invalid signal INVAUD. used to perform the center error and the tilt error according to an embodiment of the present invention. [Description of main component symbols] 102, 1902, 2002, 202, 2402 ~ variable gain amplifier; 104, 1904, 204, 2305, 905A, 905B, ADC ~ digital converter; 106, 208~ automatic gain controller; Decoder; 110, 1020 ~ blank detector; 206 ~ peak valley detector; 210 ~ offset controller; 212 ~ adder; 701 ~ VF01 area; 703 ~ VF02 area; 705 ~ VF03 area; VF04 area; 702, 704, 706, 708, PID1, PID2, PID3, PID4~ physical identification data; 802~VF01 signal; 803~VF03 signal; 901~peak detection circuit; 902~ valley detection circuit; 903A, 903B~ sample and hold circuit; 0758-A32234TWFl (20070615) 39 1332752 907~ track center error detector; 909~ tilt error detector; 1010~threshold signal generator; 1020~ blank detector; 1102~ controller 1104~multiplier; 1106~adder; 1202, 2001, 2403C, 2403D~high-pass filter; 1204~hysteresis component; 1206~counter; 1500~mode controller; 1610~first comparator; 1620~second comparison 16; 40~first mode determiner; 1630~second mode determiner; 1900~ asymmetry measuring device; 1901~offset unit; 1903, 2003, 2404~ equalizer; 1905~detecting unit; 1906~ Symmetry calculation unit; 1907~ comparator; 1910, 2010, 2304~ signal adjustment module; 2000~ asymmetry measurement device; 2301~DVD-RAM optical disc; 2302~ optical read head; 2303~ optical detector 2306~detection circuit; 2306A~ optical tilt error detector; 2306B~ track center j detector; 2307A, 2307B~ low pass filter; 2308~ tilt controller; 2309~ push-pull detector; -A32234TWFl(20070615) 40 1332752 23 10~ Tracking controller; 2403A, 2403B~offset controller; #ctrl, #ctrll, #ctrl2, Cl, C2, C4, C5, C6, TL_ctrl #DATA~ digital data, Data signal; #en~Enable signal; #gain~gain value; #hold〜pause signal; #offset〜translation signal; #offset, bi, b2~offset value; #PB~peak, valley value; #RF~ Read channel 1 signal, detection signal, optical signal; #RF'~ adjust detection No.;! # Slope, a, a2~ slope value; # th, + th, -th~ threshold value, the threshold value signal; bl~ blank signal;

Headerl, Header2, Header3, Header4~header area; INVALID~invalid signal; P1~predetermined value; S1~record data reproduction signal; S2, SD~digital signal;

TC ~ obey center error; TC_ctrl ~ control signal; yi, y2 ~ line; TL ~ optical tilt error; tl, t2, t3, t4 ~ stage; z ~ curve. 0758-A32234TWFl(20070615) 41

Claims (1)

, the scope of application for patents · · 1. An electronic device contains: a loop control of the data signal, a large variable gain amplifier, according to the - gain value will be (four) material signal value and - - valley ^ secret after the (four) a signal-peak-mode controller that connects the peak and the threshold value to the peak and _ ^ . , to generate a first control signal; The control signal generates a first--and according to the peak value and the valley value, the electronic device described in the first step of the patent is further coupled to the variable gain The amplifier samples the output of the binary signal to generate a digital data signal, wherein the peak value detection system finds the bee value and the bottom value based on the digital data signal. 3. For example, the signal control loop contains the automatic gain controller. 4. The electronic device of claim 1, wherein the mode controller comprises: a first comparator that compares the peak value with a positive high threshold; a second comparator that compares the valley value with a Negative high threshold comparison; to 输出 758-A32234TWFl (2〇〇70615) 42 1332752 comparator output; wherein if the peak is higher than the positive high threshold value, otherwise a false value is output; the first mode Mmn ' _ the first comparator and the second ratio of the first comparator are rotated if the valley value is lower than the negative high threshold value, the second comparator turns out the true value 'otherwise outputs a false value; If the first comparator and the second comparator simultaneously output the true mode determiner to output the first control signal to the automatic gain control, the electronic device of claim 4, wherein: the comparator is a step of comparing the peak to a positive low threshold value, the positive low threshold value being less than the positive high critical value; the second comparator further comparing the bottom value to a negative low critical value 'the S low threshold value is greater than the a negative high threshold; and if the peak is below the positive low threshold, the first comparator outputs a true value 'otherwise outputs a false value; if the valley value is above the negative low threshold, the second comparator The true value is output, otherwise a false value is output; and if the first comparator and the second comparator simultaneously output a true value, the =-mode determiner outputs the first control signal to the automatic gain controller. 6. The electronic device of claim 5, wherein the first mode determiner is an AND gate. 7. The electronic device of claim 5, wherein the 0758-A32234TWFl (20070615) 43 1332752 automatic gain controller increases or decreases the first step according to the first control signal to adjust the variable A gain control loop formed by a gain amplifier, a digital converter, and an automatic gain controller. The electronic device of claim 1, wherein the signal control circuit comprises: an Bayi offset controller coupled to the gain amplifier to detect an offset of the data signal, and generate a translation signal To eliminate the offset of the data signal; and an adder coupled to the output of the offset controller and the variable input, the input of the variable state, before the data signal is input to the variable gain amplifier to translate The signal updates the data signal; wherein: the mode control mode generates a second control signal according to the peak value and the comparison between the valley value and the threshold value; and the offset controller generates a second signal according to the second control signal Steps, and updating the translation signal in the second step. 9. The electronic device of claim 8, wherein the mode controller comprises: comparing the peak value to a positive high threshold value; the first comparator, the valley value is a negative high Threshold comparison; and. a second mode determiner coupled to the output of the first comparator and the second comparator; wherein: if the peak is higher than the positive high threshold, the first comparator outputs a true value, otherwise the output is false Value; 0758-A32234TWFl(2〇〇7〇615) 44 The value of 44 is lower than the negative high threshold, the second comparator outputs the output-false value; and the value, then the first-first comparator And one of the second comparators outputs a true controller. " a mode determiner outputs the second control signal to the offset second; the electronic device of claim 9, wherein the -, the type determiner is a gate (OR) or a mutual Repel (X0R). The electronic device of claim 9, wherein the second, the second control signal is increased or decreased according to the second control signal, the variable gain amplifier, the digital converter, and the offset A translational control loop formed by the controller and the adder. 12. A loop control method for loop control of a data signal, comprising: amplifying the data signal according to a gain value; detecting a peak value and a valley value of the amplified data signal; The valley value is compared with a threshold value to generate a comparison result; and the data signal is loop controlled based on the comparison result. 13. The loop control method of claim 12, further comprising sampling the amplified data signal to generate a digital data signal, wherein the peak value and the valley value are based on the digital data signal. 14. The loop control method according to claim 12, wherein the step of loop control of the data signal comprises: 0758-A32234TWFl (20070615) 45 1332752 according to the comparison result to generate a first step; The first step updates the gain value. 15. The loop control method of claim 12, wherein the step of comparing the peak value and the valley value to a threshold value comprises: comparing the peak value with a positive high threshold value; A high threshold comparison; and if the peak is above the positive high threshold and the valley is below the negative threshold, a first control signal is set to a true value. 16. The method of loop control as recited in claim 1 , wherein the step of comparing the peak and the valley to a threshold further comprises: comparing the peak to a positive low threshold; The value is compared to a negative low threshold; and if the peak is below the positive low threshold and the valley is above the negative low threshold, the first control signal is set to a true value. 17. The loop control method of claim 16, further comprising, if the first control signal is a true value, increasing the first step to accelerate the update of the gain value. 18. The loop control method of claim 12, wherein the step of loop control of the data signal comprises: detecting an offset of the data signal, generating a translation signal to cancel the offset of the data signal And generating a second control signal according to the comparison between the peak value and the valley value and the threshold value; 〇 758-A32234TWF1 (200706l5) 46 generating a second step according to the second control signal; updating the second step The translation signal; and, before the amplification of the poor signal, the translation signal is translated according to the translation signal. 19. The loop control method of claim 8, wherein the generating the second control signal comprises: comparing the peak value with a positive high threshold value; and using the valley value with a negative high threshold value Ratio matching; and if the peak is higher than the positive high threshold, or the valley is lower than the negative high threshold, setting the second control signal to a true value. 0758-A32234TWF1(2007〇615) 47