TWI330466B - All-digital phase-locked loop circuit and control method thereof - Google Patents

Description

Nine, invention description: [Technology of the invention belongs to the jaw] This case relates to a phase-locked loop circuit and method', especially to a phase-locked loop circuit and method for a full-digital component. [Prior Art] The conventional phase-locked loop method 'has roughly the following classifications: 1 · Analog phase-locked loop: consists of a phase detector, a charging pump, a loop filter, a voltage control, and a frequency-dividing circuit. It is realized by manual layout, and the loop filter is a circuit using RC components, which consumes additional layout area and is susceptible to process drift and noise influence. Refer to the previous technical literature [1] (C.-C· Chung, and C.-Y Lee, "An all-digital phase_1〇cked loop for high-speed clock generation, " /£££ j Solid-State Circuits, vol. 38, no. 2, pp. 347- 351, Feb. 2〇〇3) and [2](T. Olsson, and P. Nilsson, "A digitally c〇ntr〇jje(j pll for SoC applications, ''IEEE J. Solid-State to, vol 39, no. 5, pp. 751-760, May 2004·). 2. Digital phase-locked loop: consisting of phase frequency detector, control unit, digitally controlled oscillator and frequency-dividing circuit. To achieve 'not easy to modify the design specifications and modify the design time is too long, refer to the previous technical literature [3] (J.-S. Chi Ang, and K.-Y Chen,"The design of an all-digital phase-locked loop with small DCO hardware and fast ίοςίς^ » IEEE Trans. Circuits and Systems //, vol. 46,7,pp. 945- 950, July 1999.) and [4] (J. Dunning, G. Garcia 5 j. Lundberg, and Ed Nuckolls, "An all-digital 113769.doc 1330466 phase-locked loop with 50-cycle lock time suitable for high- Performance microprocessors, " IEEE J. Solid-State . C/rctz, v〇l. 30, no. 4, PP. 412-422, Apr. 2004.). 3. Full digital phase-locked loop: Similar to the structure of digital phase-locked loop, the biggest difference is that the implementation method is to use standard component library with synthetic software, automatic layout and winding software. Refer to the previous technical literature [丨], [2] And [5] (T.-Y. Hsu, C.-C. Wang, and C.-Y. Lee, "Design and ^ analysis of a portable high-speed clock generator, - IEEE Trans. Circuits Systems II, Vol. 48, no. 4, pp. 367-375, Apr. 2001_). Use; quasi-component library design, although avoiding the variation of artificial layout, but using the standard component library design process, all signals are full swing, although it can ensure that each transistor can operate normally, but also pay Excessive power consumption. Therefore, it is necessary to provide an innovative and progressive phase-locked loop circuit and method for all-digital components to solve the above problems. φ [ SUMMARY OF THE INVENTION One object of the present invention is to provide a phase-locked loop circuit for a full-digital component, which generates an output clock signal corresponding to a frequency according to a frequency division ratio and a reference clock. The circuit includes: a phase The frequency detector, a control circuit, an output digital control oscillator, a feedback digital control oscillator and a frequency dividing circuit. The phase frequency detector generates a leading or trailing signal according to the error of the input reference clock and the feedback clock. The control circuit generates at least one corresponding control signal according to the leading or trailing signal.忒 Output digital control oscillator according to the control signal of the control circuit, generating H3769.doc 1330466 the corresponding frequency of the round-trip clock signal. The feedback digital control oscillator generates a feedback clock signal corresponding to one of the corresponding frequencies according to the control signal of the control circuit. The frequency dividing circuit divides the feedback clock signal according to the frequency dividing ratio ', and calculates the feedback clock to be fed back to the phase frequency detector.

In one case, the control circuit has a clock controller for processing each of the two reference pulse periods, wherein when the first reference clock positive edge is triggered, the enable feedback control device is enabled. Aligning the feedback clock with the reference h pulse as the JL edge. When the second reference clock is triggered, the phase frequency detector detects the error between the reference clock and the feedback clock; When the reference clock edge triggers, according to the leading or trailing signal of the phase frequency (four), the control signal is sent to the feedback digital control oscillator, and the feedback digital control oscillator is disabled at the same time. Therefore, the phase-locked loop circuit of the full digital component of the present invention is processed at each

During the period, 'will disable the feedback digital control oscillator half reference clock period' reduce the working time of the feedback digital control oscillator to reduce power consumption and make the phase-locked loop circuit of the full digital component of the present invention In order to use the lower power consumption, the same effect can be achieved, and no additional analog components and circuits are required. Another object of the present invention is to provide a phase-locked loop control method for a full-digital component, which is applied to a phase-locked loop control circuit of a full-digital component such as claim i. The phase-locked loop control method is used for every two reference clocks. Period: - Processing period '纟 contains the following steps: (4) When the first reference clock is triggered by the positive edge, enable the (four) digit control shaker to make the feedback clock and the reference \ 13769.doc The pulse is positively aligned. (8) When the second reference clock is triggered by the positive edge, the frequency detection detects the error between the reference clock and the feedback clock, and the first reference clock negative edge. When triggered, according to the first or last signal of the phase frequency detector, the control signal is sent to the feedback digital control to oscillate. ° and disable the feedback digital oscillator at the same time. [Embodiment] > FIG. 1 is a circuit block diagram showing a phase-locked loop circuit of a full-digital component of the present invention. The phase-locked loop circuit 1 of the full digital component of the present invention generates an output clock signal corresponding to a frequency according to a frequency division ratio (MOD) and a reference clock (CLK_REF). The phase-locked loop circuit of the all-digital component of the present invention 〇匕έ 'phase-frequency detector, control circuit 12 (power-balance controller, _TRL), the digital-controlled shake-in device 13 (feedback digital- The controlled oscillator (FB_DC〇), an output digital-controlled oscillator's OUT-DCO, and a frequency divider (DIV). The phase frequency detector η generates a leading signal (up) or a backward signal (DO WN) according to the error of the input reference clock (CLK_REF) and a feedback clock (CLK-FB). This error can be an error in phase or frequency. Referring to Figure 2, there is shown a block diagram of a phase frequency detector of the present invention. The phase frequency detector U includes: a first-input stage asynchronous reset D-type flip-flop 111, a second input-stage asynchronous reset type flip-flop Π2, two-digit pulse amplifiers 113, 114, The first round of the asynchronous reset D-type flip-flop 115 and the second output stage asynchronous reset D-type flip-flop H3769.doc 116. 1330466 The first input stage asynchronous reset D-type flip-flop The 1U and the second input stage asynchronous reset D-type flip-flops 112 respectively have a clock input port, a data port (D), a reset port (CLR), and an output port (Q). The reference clock (CLK_REF) and the feedback clock (CLK_FB) are respectively the first input stage asynchronous reset D-type flip-flop ill and the second round-level asynchronous reset D-type flip-flop The clock input of 112 is 埠. This data 埠(D) is connected to a high potential (1). The reset port (CLR) is an output signal and an external reset of the first input stage asynchronous reset type flip-flop 111 and the second input stage asynchronous reset D type flip-flop η] The signal (RESET-B) is a logic operation feedback signal, and the output 埠(Q) is the first input stage asynchronous reset D-type positive and negative state 111 and the second input stage asynchronous reset type D Positive and negative device 112

The two-bit pulse amplifier includes a first digital pulse amplifier 113 and a second digital pulse amplifier 114. Since the first input stage asynchronously resets the D-type flip-flop 111 and the second input stage asynchronously resets the D-type flip-flop Η], the round two-digit pulse is generated due to the two-time phase difference. The pulses, the amplifiers 113, 114 are used to delay the amplification of the signals of the first input stage asynchronous reset d-type flip-flop ill and the second input stage asynchronous reset-type flip-flop 112. The first output stage asynchronous reset D-type flip-flop 115 and the second input stage asynchronous reset D-type flip-flop 116 respectively have a clock input 埠, a data itch (1), and a child 埠 (CLR) ) and one round of exit (Q - the reference clock (CLK - REF) and the feedback clock (Clk_FB) are respectively the first round of the non-113769.doc • 10- 1330466 with v reset D-type positive and negative gg 115 and the second output stage asynchronously reset the clock input port of the D-type flip-flop 116. The data 埠(D) is connected to a high potential. (1) The #reset port (CLR) is connected to the second The output of the digital pulse amplifiers U3, U4. The output outputs Q(Q) are respectively the first output stage asynchronous reset D-type flip-flop 115 and the second output stage asynchronous reset D-type flip-flop 116 Q埠, and the leading signal (up) and the backward signal (DOWN) respectively. • Referring to Figure 3, there is shown a circuit diagram of the digital pulse amplifier of the present invention. The digital pulse amplifier 113 is taken as an example to illustrate that it will be extremely short pulsed. The input signal (ουτυ) is delayed and extended by the pulse length to output (Bu), so that the digital pulse amplifier] The output signal (BU) of 3 can be discriminated by the first output stage asynchronous reset D-type flip-flop 115. Referring again to Figure 1, the control circuit 12 generates a corresponding signal according to the leading or trailing signal (UP'DOWN). At least one control signal, the control signal includes a coarse control signal (c〇arse), a fine control signal (Fine) and an activation signal (R-FB). The feedback digital control oscillator 13 is based on The control signals of the control circuit 12 generate a feedback signal (DCO_OUT) corresponding to one of the corresponding frequencies. Referring to Figure 4', there is shown a circuit diagram of the feedback control oscillator of the present invention. The feedback digital control oscillator 13 includes a coarse adjustment circuit 131, a fine adjustment circuit 132 and a reverse gate 133. The input of the reverse gate 133 is the start signal (R-FB) and the feedback clock signal (DC〇一〇υτ), The action of the start signal from the low level to the high level causes the output of the back gate 33 to generate a start signal. ll3769.doc -11 - 1330466 The coarse adjustment circuit 13 1 is configured to receive the start signal, and Output a coarse adjustment output signal (COARSE_OUT), the coarse adjustment Road 131 has a plurality of series

The coarse adjustment units 134, 135, 136, 137 and a first many-to-one multiplexer 138. Each coarse adjustment unit outputs a corresponding coarse adjustment multiplex signal, and the first multi-to-one multiplexer 138 is configured to receive the coarse adjustment multiplex signals from the coarse adjustment units and control the signals according to the coarse adjustment ( Coarse), output the coarse output signal (C0ARSE_0UT). In this embodiment, the first many-to-one multiplexer 138 is a first many-to-one single-coded multiplexer. The fine adjustment circuit 132 is configured to receive the coarse output signal (C0ARSE_OUT) and the fine control signal (Fine), output the feedback clock sfl number (DCO_OUT), and feed back to the inverse gate 133. The feedback digital control oscillator 13 controls the signal by coarse or fine adjustment of the input (c〇arse,

Fine), to select different delay paths' to generate the feedback clock signal (DC0_0UT) of different frequencies.

Referring to Figure 5', there is shown a circuit diagram of the coarse tuning unit of the present invention. Taking the coarse adjustment unit 134 as an example, the first coarse adjustment unit 134 includes: a plurality of serial connection buffer gates 501, 502, 503 and a second many-to-one multiplexer 5〇5. The buffer gates 501, 502, 503 are configured to receive a unit input signal (CELL_IN), each buffer gate outputs a path output signal, and the output of the last buffer gate 503 is a unit output signal (CELL_〇υτ). The second plurality of pairs of multiplexers 505 are configured to receive the unit input signals and the path output signals, and rotate the coarse adjustment multiplex signals (CELL_MX_0UT) according to the coarse control signal (c〇arse). In the present embodiment, the second many-to-one multiplexer 505 is a "second multiple-pair" single thermal code multiplexer. The coarse input order 113769.doc -12· 1330466 yuan 'unit input signal (CELL_IN) can be selected by the second multi-to-one single thermal code multiplexer 505 by selecting a different path by a coarse control signal (Coarse). Adjust the multiplex signal (CELL_MX_OUT), or directly output the unit output signal (CELL 0UT) through a plurality of serial buffer 501, 502, 503. Referring to Figure 6, there is shown a circuit diagram of the fine tuning unit of the present invention. The fine tuning unit 13 2 includes a plurality of cascaded fine tuning architectures, each fine tuning architecture comprising: four buffer gates and a four-to-one multiplexer for receiving the coarse adjustment output signal (COARSE-OUT) and the Fine-tune the control signal (Fine) and output the feedback clock signal (DCO_OUT). The four buffer gates are available in different sizes. The fine adjustment unit outputs the §fl number (COARSE-OUT) through the coarse adjustment of the input fine control signal (Fine) and outputs the feedback clock signal (DCO_OUT). Referring to FIG. 1 again, the output digital control oscillator 14 generates an output clock signal (CLK_OUT) corresponding to the control signal according to the control signals (Avg_coarse, Avg_fine, and R_〇UT) of the control circuit 12. The circuit of the output digital control oscillator 14 is similar to the circuit of the feedback digital control oscillator I] and will not be described here. The frequency dividing circuit 15 divides the feedback clock signal (DCO_OUT) according to the frequency dividing ratio (He 〇 1), and calculates the feedback clock (CLK-FB) to be fed back to the phase frequency. The detector 丨i. Referring to Figure 7, there is shown a schematic diagram of a binary search algorithm employed by the control circuit of the present invention. Whenever the phase frequency detector 发生 output changes polarity, the search step is halved, and the search direction is also inverted until the minimum step is stopped. The aforementioned search step is a unit for increasing or decreasing the current control signal 113769.doc •13· 1330466 (Coarse, Fine) in the control circuit 12. = Figure I: shows the method of reducing power control of the control circuit of the present invention. In conjunction with the phase contrast, the control controller 121' of the present invention is configured to treat each of the two reference clock cycles as a processing cycle, which is to be triggered by the first reference. Time (the time point is this feedback digital control oscillator 13 to make this (CLK shoulder and the reference clock (CL: again when the clock reference clock positive edge trigger, 0|, ^ AJ phase frequency detection The error between the detector 11 test clock (CLK_REF) and the feedback clock (CLK_fb) == when the test pulse negative edge is triggered (time point C), according to the phase frequency, the number is two: first Or behind the signal, send the control signal to the second two: the shock ""13' and at the same time disable the feedback control of the digital control oscillator waiting for the next processing cycle. Before, the power consumption of the feedback digital oscillator U is successfully reduced, and the overall operation of the oscillator is not affected. The phase-locked loop circuit 10 of the full-digital component of the local secret is disabled in each processing cycle. Grant digital control oscillator 13 half reference clock force ^, minus 回 4 feedback digital control oscillator 1 The working time of 3 is to reduce the power consumption, and the phase-locked loop circuit 10 of the full digital component of the present invention achieves the same effect by using the low power consumption of the vehicle, and does not need to add any analog components and circuits. Referring to Figure 9, #贴丄 operation method ^1: The power reduction method used in the circuit is divided into four stages: initial stage, coarse adjustment stage, 'field adjustment stage and lock stage. After the set is the initial stage I I3769.doc 1330466. When the phase frequency detector 11 detects the phase frequency error of the reference clock (CLK_REF) and the feedback clock (CLK_FB) (up d〇wn = οι 0Γ 1 〇), that is, enter the coarse adjustment phase, otherwise the initial phase is maintained; when the phase frequency debt detector 11 detects that the reference clock (CLk_REF) and the feedback clock (CLK-FB) have the same phase frequency (UP, d) 〇 wn = 11), that is, enter the lock phase. When the circuit is in the coarse adjustment phase, the control circuit 12 only controls the coarse control signal (coarse) of the coarse adjustment electric circuit 131, and roughly adjusts the feedback digital control effect. Output clock (DCO_〇UT). When When the coarse search step is one and the reference clock (CLK_REF) and the feedback clock (CLK_FB) still have a phase frequency difference (UP, DOWN = 01 or 1 〇), that is, enter the fine adjustment phase, That is, the coarse adjustment phase is maintained. 'When the phase frequency detector 11 detects that the reference clock (CLK_REF) and the feedback clock (CLK_FB) have the same phase frequency (UP, D〇WN = 11), the lock phase is entered. When the circuit is in the fine tuning phase, the control circuit 12 only controls the fine control signal (Fine) of the fine tuning circuit 132, and adjusts the output clock of the digitally controlled oscillator 13 (DCO_〇U1〇). . When the parameter + # ^ (CLK_REF) and the feedback clock (CLk_FB) still have a phase frequency difference (UP, DOWN = 01 or 1〇), continue to maintain the fine tuning phase; when the phase frequency is detected, then the device 11彳贞When the reference clock (CLK_REF) and the feedback clock (CLIC FB) have the same phase frequency (UP, DOWN=ll), they enter the lock phase. When the circuit is in the lock phase, the control circuit 12 enables the output of the control oscillator 14' and sends the control signal average (Avg_coarse, Avg_fine) of the past 64 reference clock cycles to the output control oscillator 14, which will be 113769. Doc •15· 1330466 The lock signal (LOCK) s is high, and the output digital can be fine-tuned to control the pulse frequency _ (CLK_〇υτ) when the oscillator is turned out to reduce the jitter of the output clock signal. When the reference clock (CLK_REF) and the feedback clock (<31^-1^) still have a phase frequency difference (1;?, 0 &> 1 = 01 〇 1 < 10), that is, back to fine tuning Phase; when the phase frequency detector i丨 detects that the reference clock (CLK_REF) and the feedback clock (CLK_FB) have the same phase frequency (UP'DOWN^11), it remains in the lock phase. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram of a phase-locked loop circuit of a full digital component of the present invention; FIG. 2 is a circuit block diagram of a phase frequency detector of the present invention; and FIG. 3 is a circuit diagram of a digital pulse amplifier of the present invention. 4 is a schematic circuit diagram of a feedback control unit of the present invention; FIG. 5 is a circuit diagram of a coarse adjustment unit of the present invention; FIG. 6 is a circuit diagram of a fine adjustment unit of the present invention; Schematic diagram of the search algorithm; FIG. 8 is a schematic diagram showing the waveform of the power reduction control method of the control circuit of the present invention; and FIG. 9 shows the operation method of reducing power of the control circuit of the present invention. [Main component symbol description]

S S 113769.doc .16- The phase-locked loop circuit of the full digital component of the invention phase frequency detector control circuit feedback digital control oscillator output digital control oscillator frequency divider circuit first input stage asynchronous reset D type positive Counter second input stage asynchronous reset D-type flip-flop first digital pulse amplifier second digital pulse amplifier first output stage non-synchronous reset D-type flip-flop second output stage non-synchronous reset D-type positive and negative Clock controller coarse adjustment circuit fine adjustment circuit reverse gate first coarse adjustment unit second coarse adjustment unit η-1 coarse adjustment unit η coarse adjustment unit first many to one single thermal coding multiplexer buffer brake buffer Gate buffer gate second many-to-one single thermal code multiplexer < S >

Claims (1)

1330460 X. Patent application scope: - A phase-locked loop circuit of all-digit 7C parts is based on - in addition to the frequency ratio and /% of the pulse, the output-corresponding frequency output clock signal, the circuit includes: Shi-phase frequency detection The detector generates a leading or trailing signal according to the error of the reference clock and the feedback pulse of the input; the control circuit generates at least one corresponding control signal according to the leading or trailing signal; Controlling the oscillator, according to the control signal of the control circuit, generating an output clock signal of the corresponding frequency; 〇D granting a digital control to the display device, according to the control signal of the control circuit, generating a corresponding frequency--the feedback clock The signal; and the frequency-dividing circuit 'receives the frequency-receiving frequency to the frequency-receiving frequency signal, and then the feedback clock is sent back to the phase frequency detection 1; wherein the control circuit Having a -clock controller for each of the two f-times of the pulse period, wherein when the first reference clock is triggered, the feedback digital control is enabled to cause the feedback clock to The clock is positively aligned; the second reference clock positive edge triggers the X phase frequency detection. The reference clock and the edge of the feedback clock are triggered by the second reference clock edge. The leading or trailing signal 'sending the control signal to the feedback digital control oscillator' is detected according to the phase frequency and the feedback digital control oscillator is disabled at the same time. 2. The phase-locked loop circuit of the requester, wherein the phase frequency predator packet 113769.doc includes: input stage (four) step reset D-type flip-flop and 1 two-input stage 5 v reset D-type flip-flop , having _clock input 埠, ::: is: Γ埠 and one round of exit; the reference clock and the feedback clock j are the first input stage asynchronous reset D-type flip-flop and the second The input stage asynchronously resets the clock input of the D-type flip-flop, such information 埠Connected to a high potential, the reset 槔 is the feed signal of the first-input-level non-synchronous reset D-type flip-flop and the second input-level asynchronous reset d-type flip-flop and The external reset signal is a logic operation feedback signal; the feeds are respectively the first-input-level non-synchronous reset D-type flip-flop and the first-stage non-synchronous reset D-type flip-flop The second digital pulse amplifier is used to delay the amplification of the signal of the output ;; - the first-round non-synchronous reset D-type flip-flop and the second output-stage non-synchronous reset D-type positive and negative The device has a clock input port, a data, a reset port, and an output port; the reference clock and the feedback clock are respectively the first round out-of-synchronous reset D-type flip-flops and The second round of out-of-synchronization resets the clock input bee of the D-type flip-flop, the data is connected to a high potential, and the resets are respectively connected to the outputs of the two-digit pulse amplifiers. The output 埠 is the Q埠 of the first-stage out-of-order asynchronous reset D-type flip-flop and the second output-stage asynchronous reset d-type flip-flop. Respectively for the leading signal and the backward signal. 3. The phase-locked loop circuit of the game of claim 1, wherein the control signal of the control circuit includes a coarse control signal, a fine control signal, and a start signal 113769.doc -2- 1330466. 4. The phase-locked loop circuit of claim 3, wherein the feedback digital control oscillator comprises: a reverse gate, the input is the start signal and the feedback clock signal, and the signal is low by the S-hai start signal The action of changing to the south potential causes the output of the anti-gate to generate a start signal; a coarse adjustment circuit for receiving the start signal and outputting a coarse adjustment signal: the coarse adjustment circuit has a plurality of strings a coarse adjustment unit and a first multi-to-one multiplexer, each coarse adjustment unit outputs a corresponding coarse adjustment multiplex signal, and the first multi-to-one multiplexer is configured to receive the coarse adjustment multiplex signals, and And outputting the coarse adjustment signal according to the coarse control signal; and the fine adjustment circuit for receiving the coarse adjustment signal and the fine control signal, outputting the feedback clock signal and feeding back to the reverse gate. 5. The phase-locked loop circuit of claim 4, wherein the coarse tuning unit comprises: a plurality of serial buffers for receiving a unit input signal, each of the buffer gates outputting a path output signal; and a second The multi-pair multiplexer is configured to receive the unit round-in signal and the path output signals 'and output the coarse-tuning multiplex signal according to the coarse control signal. 6_ The phase-locked loop circuit of claim 4, wherein the fine-tuning unit comprises a complex-level serial fine-tuning architecture, each fine-tuning architecture comprising: four buffer gates and a four-pair-multi-guard to receive the The coarse output signal and the fine control signal 'round the feedback clock signal. 7. A phase-locked loop control method for all-digital components, as applied in the request item 113769.doc 5 锁 phase-locked loop control cycle 'which contains the following ::: «every (4) in the "" reference clock positive When the edge is triggered, enabling the feedback digital control oscillator to align the feedback clock with the reference clock; (b) when the second reference clock is triggered, the phase frequency detector detects Measuring the error between the reference clock and the feedback clock; and (C) when the second reference clock is triggered by the edge, the leading or trailing signal of the phase frequency extractor sends the control signal to the back The digital control oscillator is also disabled and the digital feedback oscillator is disabled at the same time. 113769.doc