1330384 坎 '發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實施方式及圖式簡單說明) 【發明所屬之技術領域】 本發明係與一種在一半導體之一表面上刻紋之方法有 關，以及有關於一種半導體材料，其表面具有紋路’以降 低其反射率，且/或可增加該半導體吸收光線的能力。 5 【先前技術】 為了增加矽太陽能電池、檢測器或是光電二極體的效 率，最重要的是增加吸收於石夕中的波長小於llOOnm的光 線的總量。一般有兩種方式會造成光吸收的總量降低。光 10 線被矽的表面反射，或者進入矽中並且未被吸收的光線在 一段時間後離開矽。前述之二種方式可以將矽表面粗造化 或刻紋之方式來降低。降低光反射損失是藉由增加光線多 次撞擊矽表面的機率而達成，而降低光吸收損失是藉由限 制光於矽中（亦稱為光捕捉）。 15 一種刻紋技術，其係利用蝕刻（100)方位之單晶體矽， 所使用的溶液為氫氧化鉀（potassium hydroxide, KOH)以及 異丙醇（isopropyl alcohol, IPA)。其結果會造成一表面被複 數個方形基底的錐體所覆蓋。然而，這種方式不可以應用 於非（100)結晶方位（crystallographic orientation)的石夕表 20面。其他還有數種發展中的刻紋技術，其不必僅應用於一 特疋之結晶方位，例如活性離子餘刻（reactive ion etching, RIE)。然而，這些技術所需之費用相當昂貴，而且會造成 其他缺點，例如會增加矽表面上的媒介再組合。此外，這 些技術僅可適用於在平面的晶圓上刻紋，而且不能適用 續次頁（發明說明頁不敷使用時，請註記並使用續頁） -4- 1330384 於’例如’在@定於晶圓_補之未被«的表面上刻 紋。相關的先前技術揭露於世界專利申請案號w〇 5【發明内容】 本知月之主要目的在於提供一種半導體刻紋方法，其 可降低半導體表面的反射率。 為達成前述之發明目的，本發明第一較佳實施例係提 供一種半導體刻紋方法，其係用以在一半導體材料之一表 10面上刻紋，包含有下列步驟： 設置一保護體層於前述之半導體材料之表面上，其中 該保護體層的厚度相當薄，而且具有複數個微孔，以及 使該保護體層與該半導體材料接觸一蝕刻劑，且該蝕 刻劑截刻该半導體材料的速率快於該保護體層，該姓刻劑 15疋至少經由該等微孔而與該半導體材料接觸，經預定的時 間與在預定的條件下，該半導體材料會在鄰近該等微孔的 部位被該蝕刻劑所蝕刻，藉以使該半導體形成一具有刻紋 之表面，但是該保護體層大體上未被蝕刻。 設置該保護體層的步驟可為一單一步驟，或者其可先 20製造一保護體層，其僅具有少數之微孔或無微孔，接著將 該保護體層變薄，直到其上形成複數個微孔。該保護體層 原先並不是呈現光滑的狀態，而後使其某些部分比其他部 分變薄。因此’當保護體層的表面與蝕刻劑接觸後，其上 較薄的部分會比其他部分先被蝕刻掉，而形成前述之微 1330384 基此，本發明第二較佳實施例提供一種半導體刻紋製 程，其係用以在一半導體材料之表面刻紋路，包含有下列 步驟： 5 置—健體層於前述之半導n材料之表面上； 大體均勻地使該保護體層變薄，直到該保護體層形成 複數個微孔，以及 使該保護體層與該半導體材料接觸一能夠蝕刻該半導 體材料比蝕刻該保護體層還快的蝕刻劑，該蝕刻劑至少是 10經由該等微孔而與該半導體材料接觸，經預定的時間與在 預疋的條件下，该半導體材料會在鄰近該等微孔的部位被 該蝕刻劑所蝕刻，藉以使該半導體形成一具有刻紋之表 面，但是該保護體層大體.上並未被蝕刻。 本發明第三較佳實施例是提供一種半導體材料，其至 15少具有一表面，而該表面至少有一部分具有複數個凹窩， 其中該等凹窩係呈不規則之狀態分佈於該表面上，而且該 等凹窩各具有一内侧面，其至少一部分係呈圓形。 本發明第四實施例係提供一種半導體材料，其至少具 有一表面’而該表面至少有一部分具有複數個凹窩，其中 20該等凹窩係呈不規則之狀態分饰於該表面上，而且該等凹 窩I度不超過ΙΟμηι。 本發明第i實施例係提供一種半導體，其一表面上之 至少一部分是利用本發明第一或第二實施例所提供的方法 刻上紋路。 -6- 1330384 本發明第六實施例係提供一種半導體，其具有一表 面，該表面上至少有一部分被刻紋，其是利用透過設於該 表面上之一保護體層的多數個微孔而蝕刻該表面者，而該 保護體層之微孔是以將該保護體層變薄之方式形成的。 5 本發明更提供一種半導體材料，其至少一表面之至少 一部分設置有一保護體層，該保護體層具有複數個微孔， 而該微孔是以將該保護體層變薄之方式形成的。 利用本發明所提供之刻紋方法刻上紋路之半導體材 料，可應用於製造太陽能電池。是以，本發明第七實施例 10 是提供一種太陽能電池，其具有如第三至第六較佳實施例 所述之半導體材料者。 在本發明所提供之製程中，其所謂之”大體上未被蝕 刻（substantially unetched)”是表示钱刻發生於以下之狀 況：該半導體材料（semiconductor material)在鄰近保護體 15 (protective substance)上所具有之微孔（apertures)附近之部 份被蝕刻，然而直至蝕刻完畢，足夠的保護體仍保留在該 半導體材料之表面，以保護該半導體*避免該半導體在非 鄰近該微孔之區域亦被蝕刻者。 “大體均勻（substantially uniformly)’’是表示薄化 20 (thining)發生於以下之狀況：保護體層之所有表面大約以 相同之速率被薄化，以致於，在一預定時間内，保護體層 表面之所有部份均被移除大約相同之厚度。 在本發明所提供之製程中，該保護體可為任何物質其 可抵抗蝕刻中之至少一種可蝕刻半導體材料之蝕刻劑1330384 kan' invention description (description of the invention should be clarified: the technical field, prior art, content, embodiment and schematic description of the invention) TECHNICAL FIELD The present invention relates to a surface of a semiconductor The method of engraving relates to, and relates to, a semiconductor material having a texture on its surface to reduce its reflectivity and/or to increase the ability of the semiconductor to absorb light. 5 [Prior Art] In order to increase the efficiency of a solar cell, a detector or a photodiode, it is most important to increase the total amount of light absorbed in the stone in the wavelength less than llOOnm. There are generally two ways to reduce the total amount of light absorption. The light 10 line is reflected by the surface of the crucible, or the light that enters the crucible and is not absorbed leaves the crucible after a period of time. The two methods described above can be reduced by roughening or engraving the surface of the crucible. Reducing the light reflection loss is achieved by increasing the probability of light hitting the surface of the crucible multiple times, while reducing the light absorption loss by limiting light in the crucible (also known as light trapping). 15 A embossing technique that utilizes an etched (100) orientation of a single crystal crucible using a solution of potassium hydroxide (KOH) and isopropyl alcohol (IPA). The result is that a surface is covered by a plurality of square base cones. However, this method cannot be applied to the 20th surface of the non-(100) crystallographic orientation. There are several other developmental engraving techniques that do not have to be applied only to the crystal orientation of a particular feature, such as reactive ion etching (RIE). However, the cost of these techniques is quite expensive and can cause other disadvantages, such as increased media recombination on the surface of the crucible. In addition, these techniques can only be applied to scribe on a flat wafer, and can not be applied to the continuation page (please note and use the continuation page when the invention page is not available) -4- 1330384 at 'for example' at @定The surface is embossed on the surface of the wafer. The related prior art is disclosed in the World Patent Application No. WO 5 [Invention] The main purpose of the present invention is to provide a semiconductor engraving method which can reduce the reflectance of a semiconductor surface. In order to achieve the foregoing object, a first preferred embodiment of the present invention provides a semiconductor engraving method for engraving a surface of a semiconductor material, comprising the steps of: providing a protective layer On the surface of the foregoing semiconductor material, wherein the protective layer has a relatively thin thickness and has a plurality of micropores, and the protective layer is in contact with the semiconductor material with an etchant, and the etchant cuts the semiconductor material at a fast rate. In the protective layer, the surname 15 is contacted with the semiconductor material through at least the micropores, and the semiconductor material is etched at a portion adjacent to the micropores for a predetermined time and under predetermined conditions. The agent is etched whereby the semiconductor forms a textured surface, but the protective layer is substantially unetched. The step of disposing the protective layer may be a single step, or it may firstly fabricate a protective layer having only a few micropores or no micropores, and then thinning the protective layer until a plurality of micropores are formed thereon. . The protective layer was not originally in a smooth state, and then some portions were thinner than others. Therefore, when the surface of the protective layer is in contact with the etchant, the thinner portion thereof is etched away from the other portions to form the aforementioned micro 1330384. The second preferred embodiment of the present invention provides a semiconductor engraving. The process for engraving a surface of a semiconductor material comprises the steps of: 5 placing a body layer on the surface of the aforementioned semiconducting n material; substantially uniformly thinning the protective layer layer until the protection Forming a plurality of micropores in the body layer, and contacting the protective layer with the semiconductor material, an etchant capable of etching the semiconductor material faster than etching the protective layer, the etchant being at least 10 via the microvias and the semiconductor material Contacting, under predetermined conditions and under pre-tanning conditions, the semiconductor material is etched by the etchant adjacent to the micropores, whereby the semiconductor forms a textured surface, but the protective layer is substantially The top is not etched. A third preferred embodiment of the present invention provides a semiconductor material having a surface having at least a portion having at least a portion having a plurality of dimples, wherein the dimples are distributed on the surface in an irregular state. And the dimples each have an inner side surface, at least a portion of which is circular. A fourth embodiment of the present invention provides a semiconductor material having at least one surface 'having at least a portion of the surface having a plurality of dimples, wherein 20 of the dimples are irregularly attached to the surface, and The dimples do not exceed ΙΟμηι. The first embodiment of the present invention provides a semiconductor in which at least a portion of a surface is engraved with the method of the first or second embodiment of the present invention. -6- 1330384 A sixth embodiment of the present invention provides a semiconductor having a surface on which at least a portion is etched by etching through a plurality of micropores provided through a protective layer disposed on the surface The surface is formed, and the micropores of the protective layer are formed by thinning the protective layer. The present invention further provides a semiconductor material having at least a portion of at least one surface provided with a protective layer having a plurality of micropores formed by thinning the protective layer. The semiconductor material in which the grain is engraved by the engraving method provided by the present invention can be applied to the manufacture of a solar cell. Therefore, the seventh embodiment 10 of the present invention provides a solar cell having the semiconductor material as described in the third to sixth preferred embodiments. In the process provided by the present invention, the so-called "substantially unetched" means that the money is generated in a situation in which the semiconductor material is adjacent to the protective substance 15 (protective substance). The portion near the apertures is etched, but until the etching is completed, sufficient protective body remains on the surface of the semiconductor material to protect the semiconductor* from avoiding the semiconductor in a region not adjacent to the microvia Etched to the person. "Substantially uniformly" means that thinning occurs in the following condition: all surfaces of the protective layer are thinned at about the same rate, so that the surface of the protective layer is protected for a predetermined period of time. All portions are removed to approximately the same thickness. In the process provided by the present invention, the protective body can be any material that is resistant to at least one etchable semiconductor material etchant in etching.
發明說萌續匿 1330384 發明說明續直 較佳實施例之製程中，被沉積之該保護體層之厚度大於該 第-較佳實施賴狀厚度，㈣於#該保護^被設置Λ 於該半導體材料上時是沒有微孔的n _個被設置於 -表面上之保護體層是不可能具有完全均勾的厚度而合 如此的保護體層被逐漸薄化的過程中，最終會有複數個: 孔在敍刻前最薄的位置形成。換言之，當該層被薄化該 層，厚度大體上會-致地減少，直到某些部位财透，如 此β亥保遵體層上即形成複數個微孔。 在本發明第二較佳實施例中，薄化該保護體層之步驟 ω基本上係為-典型祕刻步驟，使用之姓刻劑可為任何可 以均勻地敍刻該保護體之敍刻劑。該等姓刻劑為熟知本項 技藝者所熟知的，包括有各種酸、酸混合物以及電浆。如 果該保護體為聚合物，最好是使用電聚钱刻法來薄化該保 護體層’典型的是使用氧電漿。 15 20 基本上，在該保護體層中之微孔大體上是隨機分佈於 該保護體的表面上，因職孔是由於絲㈣層厚度的不 同所產生的。因此，當進行過第—或第二實施例之步驟後， 辭導體㈣會許㈣所形叙㈣，其為隨機分佈於 該半導體材料之表面。該等㈣凹离的内側面其可視為 該半導體材料表面之中空部分，通常，但不是一定，為至 少-部分是圓形。亦即’雖然該等#刻凹窩内側面上具有 許多琢面（faceting) ’該内側面上之至少—部分通常未被琢 面而且是平面’而是因㈣劑作用在該半導體材料上之結 果會出現至少-部分的凹形區域。最典型的該錄刻凹窩 -9- 1330384 發明®1^； 的内側面至少一半為圓形的。最好， β玄蝕刻凹窩的内側面 上大體沒有琢面。該等蝕刻凹窩由苴 ^ /、上方來看，除非凹窩 父錯’典型上為圓形。然而在某歧 —4况下，该等蝕刻凹窩 尤其上方觀之大體是並不是圓形的，其是與該半導體材料 之結晶方向有關。無論該等蝕刻凹窩的形狀為何，狂徑 最向大約/為、'lOjim。通常該等蝕刻凹窩的尺寸範圍在低於 Ιμηι到大約5μίΏ t間。該等蝕刻凹窩間係由若干牆所區 格，該等牆的厚度比凹窩寬度薄。通常，至少有—部分的 牆大體上未被姓刻的。然而，多數的牆是形成於該等=疊 的蝕刻凹窩之間，因此形成於其上方之一點。 15 在第-與第二實施例中所使用的姓刻劑可以為任何可 银刻半導體材料速率快於㈣該保護體祕刻劑。如此之 蝕刻劑為熟知本項技藝者所熟知的。當一種蝕刻劑被利用 ^第二實施例之步驟以使保護體層變薄時，其可為相同或 疋不同於蝕刻半導體的蝕刻劑。如果該保護體層為聚合物 層’電漿是通常被利用於蝕刻半導體者。 本發明之製程之目的在於減低一半導體材料之表面之 反射性，有別於一拋光表面，以及/或者改進半導體材料 中之光限制（光捕捉）(light confinement (light trapping))。 20 本發明之製程中’癥結點在於該半導體表面之刻紋之 最佳程度是否已經到達以及何時蝕刻應被停止，其以幾種 方式來決定。其中一種方式為監視被刻紋的表面，例如藉 由目視或是以可量測光在表面的反射性的裝置來達成。第 二種方式為預定一些條件（亦即保護體的本質、厚度、蝕 -10- 1330384 發明說明 刻劑的成分以及溫度）時間以取得最佳的結果。這可由在 適當條件下的蝕刻範例來得到，例如在不同蝕刻時間長度 然後量測反射性以及/或光捕捉行為。這樣的量測結果可 供決定最佳蝕刻時間。然而，可惜的是，如果一種蝕刻劑 5 被用於蝕刻許多晶圓（wafers)或是許多批次的晶圓時，該 蝕刻劑溶液之成份將隨著時間而改變。如此，蝕刻的時間 需要被調整藉以得到最佳的刻紋效果。 本發明之製程中，使半導體材料接觸蝕刻劑的步驟可 能會造成該保護體在某些部分被蝕刻，這取決於所使用的. 10 蝕刻劑以及蝕刻條件。如果在本步驟中該保護體有某部分 被蝕刻，將造成該保護體會擁有更多的微孔，相較於在進 行本步驟前該保護體所擁有的微孔數。 在使半導體材料接觸蝕刻劑的步驟之前，在該保護體 層中之微孔是很小的，典型的直徑小於100 nm，更典型 15 的直徑小於10 nm。隨著蝕刻步驟進行，微孔的尺寸會加 大且數量會增多。在蝕刻步驟結束，微孔的數量以及半導 體材料上蝕刻凹窩的數量在每ΙΟΟμηι2有10〜1000個。 在第一與第二實施例的製程中與第三、第四、第五以 及第六實施例之半導體材料，該半導體材料均為矽。當該 20 半導體材料為矽，本發明之製程之保護體典型為氮化矽， 钱刻齋典型為氫多_較（hydrofluoric acid)以及硝酸（nitric acid)混合物，例如：比重49%氫化氟（HF)水溶液之體積比 1:50混合物（亦即100g水溶液中有49g HF)以及比重70% 的硝酸。其他化學物可添加入該蝕刻劑溶液中以提供預定 1330384 發明說賣.¾ 的蝕刻性質，例如提高半導體表面的溼度。如此之添加物 為熟知半導體蝕刻技藝者所熟知的。當該半導體材料為 矽，其可能為單結晶矽、微結晶矽或是多結晶矽。另一種 可能之用以蝕刻氮化矽的蝕刻劑為四氟化碳（cf4)以及氧 5 電漿。 本發明之製程中更包含一步驟：在蝕刻該半導體材料 以使表面產生複數個蝕刻凹窩之步驟之後，將該保護體移 除。該保護體之移除可以施用一種蝕刻劑，其蝕刻該保護 體之速率快於蝕刻該半導體材料。例如：當該半導體材料. 10 為矽而且該保護體為氮化矽，該保護體可以活性離子蝕刻 (reactive ion etching)或是在升溫中（大約180°C)接觸填酸 (phosphoric acid)之方式移除之。另一種較佳之方式為在石夕 基板上移除氮化砂是在氫氟酸(hydrogen fluoride)水溶液中 (典型的比重為5%)進行钱刻。 15 更為典型的是，本發明之製程更包含有在蝕刻該半導 體材料以使其表面產生蝕刻凹窩之後，再移除該保護體 層，然後以習知的方法在所有表面上設置一防反射層 (antireflective layer)之步驟。以此種方式會得到，相較於 僅單獨設置防反射層，大體上很大的反射性降低。 20 典型上，第一或第二實施例之製程可使一表面對於可 見光的反射度，相較於磨光的表面，降低大約50%。如果 在加上設置一抗反射層，可再大幅降低可見光的反射。 如果該半導體材料為秒而該保護體層為2nm厚之氣化 矽，蝕刻該半導體之步驟可由接觸以如前所述之比例1:50 -12- 1330384 發明說 之氫氟酸/硝酸混合液，經幾分鐘（典型為2-5分鐘），在― 般室溫下進行蝕刻。 有時候該矽基板上會在氮化矽沉積之前長出一氧化石夕 的薄層（例如20-30nm)。此種氧化物的生成是本發明之製 5 裎中不需要之物質（經觀察發現，存在於氮化矽保護體下 方之氧化矽層，除了稍許增加反應時間外並不影響本發明 之製程）。然而，該氧化物層之產生可避免該矽基板之電 子特性之降低，此專現象在氮化梦保護層下方無氧化層存 在時，有時可以被觀察到。 1〇 木發明之製程對於在不易輻射之表面刻紋具有特別的 優點，該等表面例如世界專利申請案號w〇 〇2/45143號專 利案所述固定於一支架上而生產的矽條表面。因此’本發 明之一較佳形式，該半導體材料為一矽條，其具有小於 1 ΟΟμιη的厚度以及最大寬度為3mm以及其中至少一對相 反之表面以本發明之製程刻紋。亦即，每一個至少一對之 相反表面具有複數個大體上隨機分佈之凹窩該等凹窩具 有一内側面其至少一部分為圓形的，且/或其寬度最^為 ΙΟμητ 〇 【實施方式】 -〇 為了詳細說明本發明之構造及特點所在，茲舉以下之 較佳實施例並配合圖式說明如后，其中： 第一圖係顯示一矽條之表面被刻紋的示意圖； 第：Α圖至第二D圖係顯示本發明之方法之流程圖； 第二圖係為一曲線圖，顯示經本發明之方法所製作之 -13- 1330384The invention discloses a continuation of 1330384. In the process of the preferred embodiment, the thickness of the deposited protective layer is greater than the thickness of the first preferred embodiment, and (4) the protective layer is disposed on the semiconductor material. In the process of n _ a protective layer which is not provided with micropores, it is impossible to have a completely uniform thickness, and in the process of gradually thinning the protective layer, there will be a plurality of holes: The thinnest position is formed before the engraving. In other words, when the layer is thinned, the thickness is substantially reduced until a certain portion is soaked, so that a plurality of micropores are formed on the layer. In the second preferred embodiment of the present invention, the step of thinning the protective layer ω is basically a typical secreting step, and the surname used may be any stencil which can uniformly describe the protective body. Such surnames are well known to those skilled in the art and include various acids, acid mixtures, and plasmas. If the protective body is a polymer, it is preferable to use an electric polyger to thin the protective body layer. Typically, an oxygen plasma is used. 15 20 Basically, the micropores in the protective body layer are substantially randomly distributed on the surface of the protective body because the working holes are caused by the thickness of the wire (four) layer. Therefore, after the steps of the first or second embodiment have been carried out, the conductor (4) may be referred to as (4), which is randomly distributed on the surface of the semiconductor material. The (four) concave inner side surface can be considered as a hollow portion of the surface of the semiconductor material, usually, but not necessarily, at least - partially circular. That is, 'although there are many facetings on the inner side of the #dents, 'at least the part of the inner side is usually not kneaded and planar' but acts on the semiconductor material by the (four) agent. As a result, at least a partial concave area will appear. The most typical of the recorded dimples -9- 1330384 invention® 1^; at least half of the inner side is circular. Preferably, the inner side of the beta etched dimple has substantially no facets. The etched dimples are viewed from 苴 ^ /, above, unless the dimples are typically circular. However, in the case of a certain ambiguity, the etched dimples are generally not generally circular in shape, and are related to the crystallographic direction of the semiconductor material. Regardless of the shape of the etched dimples, the madness is most about /, 'lOjim. Typically, the etched dimples range in size from less than ημηι to about 5μίΏ. The etched dimples are compartmentalized by a plurality of walls that are thinner than the dimples. Usually, at least some of the walls are largely unnamed. However, most of the walls are formed between the etched dimples of the stack, thus forming a point above it. The surname engraving agent used in the first and second embodiments may be any silver engraved semiconductor material at a rate faster than (iv) the protector secret agent. Such etchants are well known to those skilled in the art. When an etchant is utilized in the second embodiment to thin the protective layer, it may be the same or different than the etchant for etching the semiconductor. If the protective layer is a polymer layer, the plasma is generally used to etch semiconductors. The process of the present invention is directed to reducing the reflectivity of a surface of a semiconductor material, distinguishing it from a polished surface, and/or improving light confinement (light trapping) in a semiconductor material. 20 The hallmark of the process of the present invention is whether the optimum degree of engraving of the semiconductor surface has been reached and when etching should be stopped, which is determined in several ways. One such method is to monitor the surface being scored, for example by visual inspection or by means of measurable light reflectivity on the surface. The second way is to predetermine the conditions (i.e., the nature of the protector, the thickness, the composition of the etchant and the temperature) to achieve the best results. This can be obtained by etching examples under appropriate conditions, such as measuring the reflectivity and/or light capturing behavior at different etch time lengths. Such measurements can be used to determine the optimum etch time. However, unfortunately, if an etchant 5 is used to etch many wafers or many batches of wafers, the composition of the etchant solution will change over time. Thus, the etching time needs to be adjusted to obtain the best embossing effect. In the process of the present invention, the step of contacting the semiconductor material with the etchant may cause the protective body to be etched in certain portions, depending on the etchant used and the etching conditions. If a portion of the protective body is etched in this step, the protective body will have more micropores compared to the number of microwells the protective body possesses prior to performing this step. Prior to the step of contacting the semiconductor material with the etchant, the micropores in the protective layer are small, typically less than 100 nm in diameter, and more typically 15 are less than 10 nm in diameter. As the etching step proceeds, the size of the micropores will increase and the number will increase. At the end of the etching step, the number of micropores and the number of etching dimples on the semiconductor material are 10 to 1000 per ΙΟΟμη2. In the processes of the first and second embodiments, and the semiconductor materials of the third, fourth, fifth, and sixth embodiments, the semiconductor material is tantalum. When the 20 semiconductor material is germanium, the protective body of the process of the present invention is typically tantalum nitride, which is typically a mixture of hydrofluoric acid and nitric acid, for example, a specific gravity of 49% hydrogen fluoride ( The HF) aqueous solution has a volume ratio of 1:50 (i.e., 49 g of HF in 100 g of aqueous solution) and 70% of nitric acid. Other chemicals may be added to the etchant solution to provide the etch properties of the semiconductor, for example, to increase the humidity of the semiconductor surface. Such additives are well known to those skilled in the art of semiconductor etching. When the semiconductor material is ruthenium, it may be a single crystal ruthenium, a microcrystalline ruthenium or a polycrystalline ruthenium. Another possible etchant for etching tantalum nitride is carbon tetrafluoride (cf4) and oxygen 5 plasma. The process of the present invention further includes the step of removing the protective body after the step of etching the semiconductor material to cause the surface to produce a plurality of etched dimples. The removal of the protector can be applied with an etchant that etches the protector at a faster rate than etching the semiconductor material. For example, when the semiconductor material is 10 and the protective body is tantalum nitride, the protective body can be reactive ion etching or contact with phosphoric acid during heating (about 180 ° C). Way to remove it. Another preferred method is to remove the nitride sand on the Shixi substrate by engraving in an aqueous solution of hydrogen fluoride (typically 5% by weight). More typically, the process of the present invention further includes removing the protective layer after etching the semiconductor material to cause etching recesses on its surface, and then providing an anti-reflection on all surfaces in a conventional manner. The step of an antireflective layer. In this way, it is obtained that substantially large reflectivity is reduced as compared with the case where only the antireflection layer is separately provided. 20 Typically, the process of the first or second embodiment reduces the reflectance of a surface to visible light by about 50% compared to a polished surface. If an anti-reflection layer is added, the reflection of visible light can be greatly reduced. If the semiconductor material is seconds and the protective layer is 2 nm thick vaporized germanium, the step of etching the semiconductor may be contacted with a hydrofluoric acid/nitric acid mixture of the invention in the ratio of 1:50 -12 to 1330384 as described above. After a few minutes (typically 2-5 minutes), etching is performed at room temperature. Sometimes a thin layer of oxidized stone (e.g., 20-30 nm) grows on the ruthenium substrate prior to the deposition of tantalum nitride. The formation of such an oxide is not required in the preparation of the present invention. It has been observed that the ruthenium oxide layer existing under the tantalum nitride protective body does not affect the process of the present invention except for slightly increasing the reaction time. . However, the generation of the oxide layer can avoid a decrease in the electronic characteristics of the germanium substrate, which is sometimes observed when an oxide layer is not present under the nitride protective layer. 1 The process of the invention of the eucalyptus has particular advantages for the embossing of the surface which is not easily irradiated, such as the surface of the crepe which is produced by being fixed on a support as described in the patent application No. WO 2/45143. . Thus, in one preferred form of the invention, the semiconductor material is a string having a thickness of less than 1 ΟΟμηη and a maximum width of 3 mm and wherein at least one pair of opposite surfaces are scribed by the process of the present invention. That is, each of the at least one pair of opposite surfaces has a plurality of substantially randomly distributed dimples having an inner side surface at least a portion of which is circular, and/or having a width of at most ΙΟμητ 〇 [embodiment BRIEF DESCRIPTION OF THE DRAWINGS In order to explain the structure and features of the present invention in detail, the following preferred embodiments will be described with reference to the accompanying drawings, wherein: FIG. 1 is a schematic diagram showing the surface of a string being scribed; Figure 2 to Figure 2D show a flow chart of the method of the present invention; the second figure is a graph showing the-13-1330384 produced by the method of the present invention.
矽條可吸收光的總量（部分進入矽條的光量）與一雙面均磨 亮之石夕晶圓之比較，以及 第四圖至第六圖為電子顯微照片，顯示矽的表面經本 發明之方法刻紋路後之型態。 5 圖示之詳細說明： 藉由圖示可使本發明更方便地被了解。第一圖與第二 A圖至第二D圖並未明確表示出尺寸而且僅為示意圖。 第一圖表示一矽條1沿著由本發明第一實施例之製程 之刻紋的斷面圖。刻紋的步驟如下：一氮化矽2的薄層以. 10 低壓化學蒸氣沉積法（low pressure chemical vapour deposition, LPCVD)設置於該矽條基層1上。此技術可在 該基層表面上形成一均勻且保角（conformal)的氮化石夕層 2。重要地，該氮化矽2同樣是以LPCVD法成形在窄通道 或是溝槽以及矽條之側牆上，該矽條以世界專利WO 15 02/45 L43號專利案中所揭之方法製成。僅有一非常薄之氮 化石夕層2，幾個原子層厚，被沉積。如此相當薄的層會具 有許多孔，其使該矽基層可經由該等孔5而被暴露。然 後該矽條1被適當的蝕刻劑所蝕刻，例如：氫氟酸與硝酸 以1:50的比例之混合溶液。在室溫下，這種蝕刻劑蝕刻 20 氮化石夕的速率比餘刻石夕的速率低300倍。一般而言，#刻 凹窩6會在該矽條1之孔5的位置形成。在幾分鐘後，大 部分之表面均會覆蓋尺寸最大為幾個微米的蝕刻凹窩6。 而蝕刻步驟在此結束。蝕刻步驟可由改變氮化矽沉積的參 數，其會影響該層2上孔5的密度，與改變蝕刻的時間與 -14- 1330384 發明說明續 溫度來達成。如果是在一低飯刻溫度下，即會得到一個钱 刻氮化矽2比蝕刻矽i為低的速率。例如：在旳下蝕 刻劑餘刻乳化石夕2的速率比钮刻石夕的速率低_〇倍。在 本1明之衣程中亦可進行二次前述之刻紋步驟，以得到更 5 進一步之紋路性質。 第一 A圖至第二D圖顯示，以輪廓的形式一矽表 面之斷面圖’分別顯示經本發明第二實施例之製程之不同 階段之示意圖。一氮化矽層2,厚度為2_4nm，被以LPcvd 法沉積於-硬基層！之表面上。帛2A圖顯示财基層i 10被氮化物沉積後之情形。氮化物層2，其被設置於該矽表 面1上，並非均勻平滑之薄膜，其具有厚度之變異。第二 A圖中顯示凹部3, 4。根據氮化物層之厚度，凹部可能會 延伸於該矽基層之表面上，而於該氮化物層產生複數個微 孔’或者凹部僅延伸分佈於該矽基層表面之一部分如第 15 — A圖所示。第二A圖亦顯示該等凹部具有不同之深度。 在該等凹部僅延伸於該矽基層表面之一部分的情形 下，該矽基層被沉浸於一用以蝕刻該氮化矽之溶液中。該 溶液可為比重為49%的硝酸水溶液以1〇倍的水稀釋，或 者虱乱酸與端酸混合，例如比重49%的氫敦酸水溶液與比 20 重70〇/❶的硝酸以體積比1:50的比例混合。該氮化石夕層被 逐漸地且均勻地被薄化。最後該氮化物層變的报薄而使該 等最深的凹部3穿透該氮化物層而使下方之矽基層1表面 被暴露，而使該氮化物層產生複數個微孔5，如第二b圖 所示。較淺之該等凹部4並未在此階段中穿透該氮化物層 -15- 1330384 發明說明 1。 矽基層1現在沉浸於一可蝕刻矽快於蝕刻氮化矽之溶 液中，例如：比重49%的氫氟酸水溶液與比重70%的補酸 以體積比1:50的比例混合。其結果會造成蝕刻凹窩6會 5 在矽基層1位於該等微孔5之位置，如第二C圖所示。突 出該蝕刻凹窩6上之氮化矽2薄層是非常脆弱的而且容易 破損，可讓新的蝕刻劑進入該等蝕刻凹窩6中。該等蝕刻 凹窩6會隨著蝕刻程序之進行而變得較大。 在該蝕刻程序中，該氮化矽層2也會輕微地變薄。或. 10 者會使該氮化矽層2上形成其他的微孔7。這些微孔7也 會使該矽基層上形成蝕刻凹窩8,如第二D圖所示。當得 到最佳之刻紋程度後即可停止蝕刻程序。這種情況會在大 部分的矽1表面均被刻紋，但仍有一小部分未被刻紋。 蝕刻程序亦可在一溫度範圍被使用。特別是較低的溫 15 度通常產生一比蝕刻矽較低之蝕刻氮化矽速率，因此例如 在0°C下進行蝕刻，而不是在室溫下，在某些情況下是可 行的。該氮化矽層亦可被處理以降低其在一範圍内之矽蝕 刻劑之蝕刻率。例如：高溫氮化矽（1000〜1100°C)退火後 一般脅造成石夕银刻劑餘刻該氮化石夕之速率降低。 20 前述之刻紋技術特別適合於薄膜矽電池，因為在刻紋 製程中僅會消耗少數之矽（每刻紋表面大约2-3微米）。本 刻紋技術可被應用於石夕晶圓（wafers)或多變晶粒尺寸之薄 膜。 範例： -16- 1330384 發明說明 在以下所有範例中，沉積氮化矽均是以低溫化學蒸氣 沉積法，溫度為750°C並以一二氯石夕烧（dichlorosilane)流 速為30標準立方公分/每分鐘（seem)，一氨水（ammonia)流 速為120 seem以及壓力70Pa。典型之沉積時間為75秒。 5 例一： 一厚度大約為2 nm之氮化矽層被沉積於一磨亮之（111) 方位之石夕晶圓上。一樣本自該晶圓切斷，且以一 1:50之 氫氟酸與硝酸溶液，溫度為〇°C，進行蝕刻。此樣本利用 矽樹脂被包覆於1 mm厚之低金屬玻璃中，而且其反射度. 10 是以一具有一完整球體之分.光光度計（spectrophotometer) 測量之。此樣本在一 900 nm波長下具有11%之反射度， 而一磨光被包覆的參考矽晶圓之反射度為24%，而一以 (100)方位矽，其被刻上倒錐形之紋路，在相同波長下具有 8%之反射度。這些結果顯示該刻紋製程對於降低該矽表 15 面反射度相當有效。 例二：蝕刻薄矽條 一直徑100 mm、厚度1 mm、（ 110)方位之石夕晶圓被使 用。該晶圓上具有複數個薄矽條，間距為105微米，厚度 大約為70微米，係依照世界專利WO _^/4JJL4^號專利案 20 中所揭之方法製成。如此獲得之薄矽之側壁上係高度地被 磨亮。在該等側壁上刻紋可當作太陽能電池中面對太陽之 表面。 一氮化矽之薄層被沉積於該晶圓上。該等薄矽條之其 中一者被從該晶圓上打破並且固設於該晶圓之表面上。在 -17- 1330384 發明麵續頁 此方式中，在蝕刻過程中，其中一矽條之側壁表面係清楚 可見的。再經過5分鐘的蝕刻，溫度為室溫、蝕刻劑與例 一相同，該等矽條被刻紋的狀況最佳，而且結束蝕刻。此 時該等矽條的厚度大約為65微米。 5 量測被刻紋之矽之光限制（光捕捉）的程度。第三圖係 顯示65微米厚之已刻紋之矽條，與70微米厚之未刻紋之 矽條之光吸收量比較圖。其清楚地顯示本刻紋程序對於波 長為S50-1100 nm之光捕捉有顯著地改進，因此，如果本 刻紋方法被應用於矽太陽能電池中將會顯著地提升能量轉 10 換率。 例三：表面純化 許多（111)方位，>1000 ohm-cm之滲硼浮動區域之矽 晶圓（boron doped float-zoned silicon wafers)被使用。一大 約為30 nm厚之氧化物熱生長於該等晶圓上。一氮化矽的 15 薄層之後被沉積而且該等晶圓被以例二之方法刻紋。在刻 紋之後，該晶圓上設置一填擴散層（phosphorus diffusion) 並熱生長一 30 nm厚之氧化物層。然後該等晶圓在5%氫 與95%氮之混合物中，以430°C之溫度下退火30分鐘。 在經過前述之處理後，每一邊的發射體餘和電流強度 20 (emitter saturation current density)為 20-25 fA/cm2。這個低 的數值表示在被刻紋的表面上具有優越之表面鈍化效果。 本發明之製程之優點為： 本發明之製程為一種較為簡單與不昂貴的方法可降低 一半導體材料之一表面之反射度。此外，本發明之製程可 1330384 發明說ups 使不暴露於輻射線中之表面，例如不能以活性離子蝕刻刻 紋之表面刻上紋路（致使反射度降低）。更有一點，本發明 之製程可施用於（111)晶格方位的表面，其無法以非等方性 的I虫刻劑（anisotropic etchants)，例如鱼氧化钾，钱刻以刻 5 上紋路。 本發明之發明範圍並非僅侷限於說明書中圖示與範例 所敘述之方法，任何以相同之原理之變異之方法而為熟悉 本項技藝可輕易實施者，應仍屬於本發明之範圍。 -19- 1330384The total amount of light absorbed by the purlin (the amount of light entering part of the purlin) is compared with a double-sided polished Shi Xi wafer, and the fourth to sixth figures are electron micrographs showing the surface of the crucible The method of the invention is a type of engraved road. 5 Detailed Description of the Drawings: The present invention will be more readily understood by way of illustration. The first and second A through second D figures are not explicitly shown and are merely schematic. The first figure shows a cross-sectional view of a string 1 along a scribe of the process of the first embodiment of the present invention. The step of engraving is as follows: a thin layer of tantalum nitride 2 is placed on the base layer 1 of the stringer by a low pressure chemical vapour deposition (LPCVD) method. This technique forms a uniform and conformal nitride layer 2 on the surface of the substrate. Importantly, the tantalum nitride 2 is also formed by a LPCVD method on a narrow channel or a trench and a side wall of a beam, which is manufactured by the method disclosed in the patent of WO 15 02/45 L43. to make. There is only a very thin layer of nitrogen oxide layer 2, several layers of atoms thick, deposited. Such a relatively thin layer will have a plurality of apertures through which the base layer can be exposed. The stringer 1 is then etched with a suitable etchant, for example, a mixed solution of hydrofluoric acid and nitric acid in a ratio of 1:50. At room temperature, this etchant etches 20 nitrides at a rate that is 300 times lower than the rate of the ruthenium. In general, the #刻窝6 is formed at the position of the hole 5 of the stringer 1. After a few minutes, most of the surface will cover the etched dimples 6 up to a few microns in size. The etching step ends here. The etching step can be accomplished by varying the parameters of the tantalum nitride deposition, which affects the density of the holes 5 in the layer 2, as well as changing the etching time and the continued temperature of the invention. If it is at a low cooking temperature, a rate of tantalum nitride 2 is lower than the etching 矽i. For example, the rate of emulsified stone eve 2 in the underarm etchant is _〇 times lower than the rate of the button etched. The above-described second marking step can also be carried out in the course of the present invention to obtain further grain properties. The first to second figures D show a cross-sectional view of a surface in the form of a contour showing a different stage of the process of the second embodiment of the present invention. A layer of tantalum nitride 2, having a thickness of 2_4 nm, is deposited on the hard substrate by the LPcvd method! On the surface. Figure 2A shows the situation where the base layer i 10 is deposited by nitride. The nitride layer 2, which is disposed on the crucible surface 1, is not a uniformly smooth film having a variation in thickness. The recesses 3, 4 are shown in the second A diagram. Depending on the thickness of the nitride layer, the recess may extend over the surface of the ruthenium base layer, and a plurality of micropores may be formed in the nitride layer or the recess may extend only over a portion of the surface of the ruthenium base layer as shown in FIG. Show. Figure 2A also shows that the recesses have different depths. In the case where the recesses extend only over a portion of the surface of the base layer, the base layer is immersed in a solution for etching the tantalum nitride. The solution may be diluted with water of a nitric acid having a specific gravity of 49% by 1 time, or mixed with a terminal acid, for example, a volume ratio of a 49% by weight aqueous solution of hydrogen peroxide to a nitric acid having a specific gravity of 70 〇/❶. 1:50 ratio mixing. The nitride layer is gradually and uniformly thinned. Finally, the nitride layer is thinned such that the deepest recesses 3 penetrate the nitride layer to expose the underlying base layer 1 surface, and the nitride layer generates a plurality of micropores 5, such as a second Figure b shows. The shallower recesses 4 do not penetrate the nitride layer at this stage -15 - 1330384. The ruthenium base layer 1 is now immersed in a solution which can be etched faster than the etched tantalum nitride. For example, a hydrofluoric acid aqueous solution having a specific gravity of 49% and a supplemental acid having a specific gravity of 70% are mixed at a volume ratio of 1:50. As a result, the etching recess 6 will be placed at the position of the pupil layer 1 at the microholes 5, as shown in the second C. The thin layer of tantalum nitride 2 protruding from the etched recess 6 is very fragile and easily broken, allowing a new etchant to enter the etched recesses 6. These etched dimples 6 become larger as the etching process proceeds. In the etching process, the tantalum nitride layer 2 is also slightly thinned. Or 10 may form other micropores 7 on the tantalum nitride layer 2. These micropores 7 also form etched dimples 8 on the ruthenium base layer, as shown in Figure 2D. The etching process can be stopped when the optimum degree of engraving is obtained. In this case, most of the surface of the crucible 1 is engraved, but a small portion is still not engraved. The etching process can also be used over a range of temperatures. In particular, a lower temperature of 15 degrees generally produces a lower rate of etch tantalum nitride than etch 矽, so etching at, for example, 0 ° C, rather than at room temperature, is possible in some cases. The tantalum nitride layer can also be treated to reduce the etch rate of the etchant in a range. For example, after annealing at a high temperature tantalum nitride (1000~1100 °C), the general threat causes the rate of the nitrite to decrease. 20 The aforementioned engraving technique is particularly suitable for thin-film tantalum batteries because only a few defects are consumed in the engraving process (about 2-3 microns per textured surface). This engraving technique can be applied to wafers or wafers of variable grain size. Example: -16- 1330384 DESCRIPTION OF THE INVENTION In all of the following examples, the deposited tantalum nitride is a low temperature chemical vapor deposition method at a temperature of 750 ° C and a dichlorosilane flow rate of 30 standard cubic centimeters / Every minute (seem), an ammonia flow rate of 120 seem and a pressure of 70 Pa. A typical deposition time is 75 seconds. 5 Example 1: A layer of tantalum nitride with a thickness of approximately 2 nm is deposited on a polished (111) azimuth wafer. A sample was cut from the wafer and etched with a 1:50 hydrofluoric acid and nitric acid solution at a temperature of 〇 °C. This sample was coated with enamel resin in a 1 mm thick low metallic glass, and its reflectance. 10 was measured by a spectrophotometer with a complete sphere. This sample has a reflectivity of 11% at a wavelength of 900 nm, while a polished coated reference 矽 wafer has a reflectance of 24%, and one is engraved with a reverse cone at (100) orientation. The grain has a reflectance of 8% at the same wavelength. These results show that the engraving process is quite effective in reducing the reflectance of the surface. Example 2: Etching a thin strip A silicon wafer having a diameter of 100 mm, a thickness of 1 mm, and a (110) orientation is used. The wafer has a plurality of thin rafters having a pitch of 105 microns and a thickness of about 70 microns, which is made in accordance with the method disclosed in Patent No. 20 of the World Patent No. WO _^/4JJL4. The side walls of the thus obtained thin enamel are highly polished. Engraving on these sidewalls can be used as the surface of the solar cell facing the sun. A thin layer of tantalum nitride is deposited on the wafer. One of the thin strips is broken from the wafer and secured to the surface of the wafer. In the manner of the -17- 1330384 invention, the sidewall surface of one of the rafters is clearly visible during the etching process. After another 5 minutes of etching, the temperature was room temperature, and the etchant was the same as in Example 1. The ridges were etched in the best condition and the etching was ended. At this point the thickness of the beams is approximately 65 microns. 5 Measure the extent of the light limit (light capture) of the engraved enamel. The third figure shows a comparison of the light absorption of a 65 micron thick textured strip with a 70 micron thick uncut strip. It clearly shows that the engraving process has a significant improvement in light capture with a wavelength of S50-1100 nm, so if the engraving method is applied to a solar cell, the energy conversion rate will be significantly improved. Example 3: Surface Purification Many (111) orientations, > 1000 ohm-cm boron doped float-zoned silicon wafers were used. A large oxide of approximately 30 nm thick is thermally grown on the wafers. A thin layer of 15 turns of tantalum nitride is deposited and the wafers are patterned by the method of Example 2. After the embossing, a diffusion layer (phosphorus diffusion) is placed on the wafer and a 30 nm thick oxide layer is thermally grown. The wafers were then annealed at 430 ° C for 30 minutes in a mixture of 5% hydrogen and 95% nitrogen. After the foregoing treatment, the emitter and current intensity 20 of each side is 20-25 fA/cm2. This low value indicates superior surface passivation on the surface being embossed. An advantage of the process of the present invention is that the process of the present invention is a relatively simple and inexpensive process which reduces the reflectance of a surface of a semiconductor material. Furthermore, the process of the present invention can be used in the form of 1330384 to say that ups are not exposed to the surface of the radiation, for example, the surface of the active ion etched etch is not engraved (causing the reflectance to decrease). More specifically, the process of the present invention can be applied to a (111) lattice-oriented surface that cannot be engraved with an anisotropic etchants, such as fish potassium oxide. The scope of the invention is not limited to the embodiment of the invention, and is to be construed as being limited to the scope of the invention. -19- 1330384
【圖式簡單說明】 第-圖係顯示-矽條之表面被刻紋的示音圖· 第二A圖至第二D圖係顯示本發明之方法之流程圖； 第二圖係為一曲線圖，顯示經本發明之方法所製作之 5矽條可吸收光的總量（部分進入矽條的光量）與一雙面均磨 亮之矽晶片之比較，以及 第四圖至第六圖為電子顯微照片，顯示矽的表面經本 發明之方法刻紋路後之型態。 10【圖式符號說明】 1石夕基層 2氮化石夕層. 3, 4凹部 5，7微孔 6，8钮刻凹窩 -20-[Simple diagram of the drawing] The first diagram shows the sound diagram of the surface of the beam being embossed. The second to second diagrams show the flow chart of the method of the present invention; the second diagram is a curve. The figure shows the total amount of absorbable light (the amount of light entering part of the purlin) produced by the method of the present invention is compared with a double-sided polished wafer, and the fourth to sixth figures are electrons. A photomicrograph showing the surface of the crucible after being textured by the method of the present invention. 10 [schema description] 1 stone base layer 2 nitride layer layer. 3, 4 concave 5,7 micropores 6,8 button engraved pocket -20-