TWI327711B - Boot-switching apparatus and method for multiprocessor and multi-memory system - Google Patents

Description

1327711 IPD070011TW 23277twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a booting device and method, and more particularly to a multi-processor and multi-memory switching using a single timer Boot device and method. [Prior Art] Over the past few years, with the advancement of information technology, the speed of processors has also multiplied. In order to achieve leadership status, processor manufacturers Intel and AMD are not working hard to develop more. High frequency processor. Today, the processor's clock cycle has evolved from 10 megahertz (MHz) to more than 1 gigahertz (GHz). However, as the processor clock cycle increases, so does the complexity of the hardware. Processor manufacturers, in pursuit of speed, realize that the speed of the processor still has its limits. To develop, other laws are needed at this time. As a result, the multiprocessor architecture has evolved into the latest generation of processor technology, using the ideal combination of multiple processors in tandem to achieve multiplex processing. When the multi-processing system is powered on, it must select one of the processing ports as a bootstrap processor to execute the program for booting the system, and the remaining processors are regarded as application processors. As an aid to booting the processor. Among them, when the system is powered on, each processor will perform a built-in self-test function. If any processor has a boot error due to some factor, it will send a status flag to know. 5 1327711 IPD070011TW 23277twf.doc/n, this situation is the same, and the system does the follow-up. However, if the original boot processor has a boot error, it must use another application processor to replace its task in order to perform the boot function normally. In this case, the conventional practice is to use a Fault Resilient Booting (FRB) technology, through the Basic Input/Output System (BIOS), and the Baseboard Management Controller (Baseboard Management Controller). , BMC) or other hard φ body to perform the boot response action. The following is an introduction to the conventional FRB technology with a system including two processors. 1 is a schematic diagram of a conventional dual processor system using a BMC for FRB, and FIG. 2 is a flow chart of a conventional dual processing system using BMC for FRB. Referring to FIG. 1 , in the dual processor system, the processor 11 and the processor 120 are connected to the enabling pin 131 and the enabling pin 132 of the BMC 130. The processor for booting. In addition, the BMC 130 has a built-in timer 133 and is connected to a universal input wheel (General purp〇se j叩ut/〇utput,) of the m〇s system. 'Please refer to FIG. 1 and FIG. 2 at the same time, before the system 1 is turned on, that is, firstly, the function of executing the FRB by the processor in the wrist (3) 0 (step S210), including setting a pause time (Time-out), The enabler pin 131 and the enable pin I32 of the BMC 130 are set such that the processor 110 and the processor 120 are enabled after being turned on. Whenever the system 100 is powered on (P〇Wer〇n) or restarted (step S220), the BMC 130's FRB timer 133 will be activated to start the countdown pause 6 1327711 IPD070011TW 23277twf.doc/n ( Step S230) 'It is also determined whether a timer disable signal is received (step S240). When the BIOS system successfully performs the Power On Self Test (POST), the general-purpose input/output pin 140 can be used to issue a disable signal to notify the BMC 130 to disable the frb timer 133 (Disable). The processor 〇 and the processor 120 can continue the normal boot process (step S25 〇). However, if the processor 110 for booting fails when booting, the system 100 cannot be turned on normally, and the FRB timer 133 is not disabled by the BI〇s system. Therefore, when the FRB timer 133 is suspended, it is judged. When the time countdown ends (step S260), the BMC 130 turns off the function of the processor 110 by setting the enable pin 131 to 0 (step S270), and restarts the system 100 instead of being processed by the processor 120. The device 11 is turned on (step S280). The above principle is also applied to the technology of dual BIOS read only memory (ROM). The dual BIOS ROM technology, as the name implies, is to configure two BIOS ROMs on the motherboard to store the BIOS system data, using dual BIOS ROM. The system can avoid the dilemma when the BIOS is upgraded because the BIOS file does not match the motherboard, the BIOS file is modified, or the upgrade process is interrupted. FIG. 3 is a block diagram of a conventional dual BIOS ROM system, and FIG. 4 is a flow chart showing the operation of a conventional dual BIOS ROM system. Referring first to FIG. 3, the BIOS ROM system 300 includes an input/output control (Super 1/0, SIO) chip 310, which is transmitted through the address / 7 1327711 IPD070011TW 23277twf.doc/n \ data (Address/Data The line is connected to the read-only memory 320 and the read-only memory 330 and is connected to the read-only memory 320 and the read-only memory 330 by a selection pin 311, respectively, where a read-only memory is assumed. The 320 series is used as the main power-on, and the read-only memory 33 is reserved. At this time, the signal sent by the selection pin 311 is 1, and the read-only memory 32 is enabled. This signal is converted via the inverter 340. After that, it is sent to the read-only memory 330 to disable it. In addition, a timer 312 is disposed in the SIO chip 31 for selecting the BIOS to be read by the read only memory 32 and the read only memory 330. Referring to FIG. 3 and FIG. 4 simultaneously, after the system 300 is powered on or restarted (step S410), the ROM timer 312 is started to start the countdown pause time (step S420), and it is determined whether the timer disable signal is received (step S430), if the BIOS system can execute P〇ST normally, the R can be disabled by sending a disable signal to the DDR1 by a general-purpose input/output pin 350. At this time, the signal that does not affect the output of the selection pin 311' is still started with the read-only memory 32 (step S440). However, if read-only memory 320 occurs at boot time

Error 'At this time, the B丨〇S system cannot be turned on normally, and the R〇M timer 312 cannot be disabled. When it is judged that the pause time of the ROM timer 312 is completed (step S450), the read-only memory is performed. The switching of the body (step S460) sets the signal sent by the selection pin 311 to 〇, and at this time, only the hidden object 320 is disabled and the read-only memory 33 is enabled. Finally, the system is restarted, and the read-only memory 330 is turned on (+ step S470).乂8 1327711 IPD070011TW 23277twf.doc/n It can be seen from the above that when multiple processors use one timer as the cut and double read system, when the error occurs, the money may be generated, and the timer of the system startup is counted down first. , in the absence of a processor (such as BIOS R〇M) caused by 蚌, p涘疋 is the other party (such as the possibility of system misjudgment. __ caused by, but the default device can be a normal timer After the countdown is completed, the system: the machine is wrongly riding, and then restarted due to the processing. In this case, the fault occurs in the most f. ..., to successfully start the system to open [invention] The present invention provides a multiprocessor And more = set only _ pin connected to the processor; test =: = r timers to determine the processing of the error = The present invention provides a multi-heart == boot: boot switching crack determination system can not open '= table ::- A faulty or inoperable processor or memory is wrong to start the action. And the moon is enough to hang the execution of the converter == in the supply - 7 kinds of ^ multi-memory system boot, - in the 糸Countdown to the beginning of the boot - pause time, and When the countdown 9 1327711 IPD070011TW 23277twf.doc/n is completed, 'first judge whether the processing p has an error, and then find the "memory of the memory proposed by the present invention - the problem of the multi-lulu two-lift boot. Replace the device, this device is configured ^ ^ $ and multi-memory system boot cutting system, its ^ = ^ = _; * called a memory of Zhao's multiple memory selection pins and a::: eve: processor detection pin, foot system respectively To the processor: ^ 'The processor enable pin has a - enable signal to the processor to: =, pin: the upper setting is also lightly connected to the processor, and here cry: processing benefit detection / then pin In response to the working state of the processor, I Qing is suitable for detecting the selected pin and is coupled to the above-mentioned record S. The memory is selected in these memories. Set the signal, Γτ. , a ten-time state includes setting a reciprocal when paused, and two or two ^ in the system _ when 'the pause time from the start of the foot on the A-between count, the judgment of each processor enable pin, it wealth side _ Whether the signal of the _ signal is correct: if the middle right signal does not match the signal, the corresponding The processing pin disables the processor; if all the enabling signals and the integrated signal: pay', the memory used is switched by the money and the body selection stitch. In one embodiment of the present invention, the multiprocessor described above The multi-memory=system switching device further includes a warning device adapted to issue a warning message when the 5th memory is switched and the system is still unable to be normally turned on. In an embodiment of the present invention In the above memory, the memory is stored in the Basic Input/Output System (BIOS), only reading 1327711

IPD070011TW 23277twf.d〇c/n Read Only Memory (ROM). The power-on switching device described above is disposed in a BaseBardard Management Control (BMC) device. In addition, the above timer includes a Fault Resilient Booting (FRB) timer. In an embodiment of the invention, the enabling signals of the processor enable pins described above are each pre-set to an enabled state. On the one hand, the above-mentioned note, the selection signal of the body selection stitch includes pre-slipping one of the above-mentioned memories into a missing state, and the shouting is set to the forbidden state, and when = the memory is to be switched, This includes setting the other Wei body to enable the evil and the rest of the memory is set to the disabled state. The invention proposes a multiprocessor and multi-memory system, which includes two places: a device, a plurality of memories, and a power-on switching device. The power-on switch includes a plurality of processing 1^ enable pins, a plurality of processor detection pins, a memory selection pin, and a timer. : The system is tapped to the processor, and each processor is enabled or disabled. The processor detects pin 7 and processes 5, and pursues some processing (5). The pin is suitable for the status of the counter test and obtains a signal. The memory is selected by the memory of the _ to the upper 34, which is suitable for setting a selection signal, and switching between the memory. The timer includes setting a pause number, which is appropriate - when the system is turned on, 'from the pause time: the upper signal and the side signal of each processor_pin are phase-to-right. The enable signal does not match the signal. , the processor is disabled by the corresponding processing η 1327711 IPD0700HTW 23277twf.d〇c/n enable pin; if the phase is right, all the messages to the right and the detection signal are 'received' The body selection pin switching is such that, in the embodiment of the present invention, a multiplexer j is also provided between the pin and the memory, which is adapted to transfer the selection signal in an embodiment of the present invention, and further includes a group. (10) Configured between processing (4) between the stylus and the processor, it is suitable for detecting whether the processor is working properly and sending the corresponding rip signal to the processing to detect the stitch. The invention proposes a multi-processing! ! And the booting method of multi-memory systems. A system that handles multiple limbs, this method includes the following steps: when starting a job, start counting down a pause time. In the countdown, determine whether a timer disable signal is received. If the timer is not received, the timer is disabled. When the countdown is completed, it further detects whether the processor is functioning properly and obtains corresponding multiple jobs. Then, it is determined whether each _test signal is consistent with the corresponding < enable m number. If the product test signal does not match the corresponding enable signal, the enable signal is set to the disabled state to disable the corresponding processor. On the other hand, if all the detection signals match the corresponding enable signals, adjust the selection signal sent to the memory to switch the memory for booting. In an embodiment t of the present invention, after the step of determining whether the timer disable signal is received, if the timer disable signal is received, the power-on operation is performed by the currently set processor and the memory. In one embodiment of the present invention, the manner in which the reciprocal of the pause time is canceled includes the reversal of the pause time by the 12 1327711 IPD070011TW 23277twf.doc/n basic input/output system when the basic input/output system normally performs the power-on action. In an embodiment of the present invention, after the step of disabling the corresponding processor and switching the memory, the system further includes restarting the system and performing the booting operation with the switched processor and the memory.

In an embodiment of the present invention, before the system is powered on, the method further includes setting all the enable signals to the enabled state, and selecting a memory as the boot memory, and setting the corresponding selection signal to The state can be set, and the selection signal of the remaining memory is set to the disabled state. In an embodiment of the invention, the step of switching the memory includes setting the selection signal of the originally selected memory to the disabled state, and selecting one of the remaining § memories as the boot memory, and The corresponding selection signal is set to the enabled state. In the embodiment of the invention - when all the memory has been selected, and the system still fails to boot normally, including issuing - then the message.

Just use a single timer to judge the system: the device or the memory is wrong, and borrow (4) = = to decide whether to switch the memory, but to find out, and use another processor or memory to re- In the prior art, the error cannot be correctly judged. 13 1PD070011XW 23277twf.doc/i RDM is the machine in the machine, since the FRB timer and the suspension of the slave, the same, and the silk Choosing a substitute can be a risk. The better way is to combine the two timers and when you find the power-on error, ask the question of the occurrence of the correcting error of the original disc, and let the system choose the alternative. The processor or the counter is activated. The present invention is based on the above-described concept - a multi-processor and multi-memory system boot switching apparatus and method. In order to clarify the content of the present invention, the following specific examples are given as examples in which the present invention can be implemented. Figure 5 is a block diagram of a multiprocessor and multi-memory system in accordance with an embodiment of the present invention. Referring to FIG. 5, the multiprocessor and multi-memory system 500 of the present embodiment includes a baseboard management controller (baseboard).

Management Controller (BMC) 510, detection module 520, multi-work 530, input/output control (Super Input/Output, SI0) wafer 540, n processors CPU0, CPU1, ..., CPUn-1 and m read-only Memory ROMO, R〇M1, ..., R〇Mm-1. The towel, the read-only memory R〇M〇, R0M1.....ROMm-1 is, for example, a read-only memory for storing basic input/output system (BIOS) data. The substrate management controller 510 includes enable pins 512 to 514, > (measurement pins 515 to 517, selection pins 518, and timer 511. The enable pins 512, 513, and 514 are respectively coupled to the processor 〇卩1; 〇1; 〇? 1; 11-1 coupled, is adapted to provide a substrate management controller 510 to set an enable signal to enable or disable the processor CPU0, CPU1.....CPUn-Ι Among them, the enable signals of these enable pins are generally set to the enable state, that is, 1327711 IPD070011TW 23277twf.doc/n said that it is assumed that each processor CPUO, CPU1.....CPUn l can Normal operation, so the CPU0, CPU1.....CPUn-Ι are enabled first when the system is powered on. @Detection pins 515, 516, 517 pass through the detection module 520 and the processor CPU0, respectively. CPU1, CPUn-Ι are connected, and used to measure the working state of CPU0, CPIH, CPUn-Ι, and obtain a corresponding detection signal. The detection module 520 is used to detect each Whether the processor CPU0, CPU1.....CPUn-Ι is operating normally, and sends the detection signal of the second to the detection pins 515-517. The selection pins 518 are respectively coupled to the read-only memory ROMO, ROM1, ..., R〇Mm-1 through the multiplexer 530, and are adapted to provide their board controller 510 to set a selection signal for reading only. The body ROMO, ROM1, ..., R〇Mm-1 are switched. Among them, since the system 500 only needs to read the BI〇s data from a read-only memory, the boot operation can be performed, and therefore these are transmitted to the selected pin. In the read signal of the ROM-only memory ROMO ^ ROM1.....ROMm-1, for example, only the first set-only memory is enabled, and (10) the remaining memory is set to the disabled state. However, if it is turned on It is found that the read-only memory of this job is wrong, and the read-only memory _ needs to be switched _, then the preset read memory can be disabled and the other read-only memory is set to enable In addition, the rest of the memory remains in the disabled state of the original pattern, so that the function of the switching memory of the present invention can be achieved. Further, the substrate management controller 51 includes a timer 511. 'This timing 5 511 is for example an error recovery boot... also 15 1327711 IPD070011T W 23277twf.doc/n

Resilient Booting, FRB) timer. Since the power of the baseboard management controller 510 is independently supplied, the user can turn on the power of the baseboard management controller 510 before the system 500 is turned on, thereby setting the timeout of the timer 511, and in the system. At the same time that the power of the 500 is turned on, the timer 511 starts the countdown pause time. The input/output control chip 540 is respectively connected to the ROM/ROM1, ROM1, ..., R〇Mm-1 through the address/data line, and when the system 500 is actually powered on, it is based on these read-only The enable state of the memory, R〇M1.....ROMm·1, reads the BIOS system data from the enabled read-only memory. It is worth mentioning that the multi-processor and multi-memory system 5 of the embodiment further includes a warning device (not shown), and the warning device will be in the memory, R0, ROM1, ROM1, ... R〇Mm-l has been switched, and when the system 500 still fails to boot normally, a warning message is sent to inform the user to replace the read-only memory ROMO, ROM1, ..., R〇Mm-1. The present invention also includes developing a set of power-on switching methods based on the architecture of the multi-processor and multi-memory system 5, and the following is another embodiment of the present invention. Detailed steps between the signal and the capital. FIG. 6 is a flow chart showing a method for switching on and off of a multi-memory system according to an embodiment of the present invention. Please refer to FIG. 6. In this embodiment, it is assumed that all the processors can be normally operated; /, therefore, the enable signals on all enabled pins are set to the enabled state. In addition, a read-only memory can be selected as the boot memory, and the corresponding selection signal is set to the enabled state, and the remaining read-only memory is set to be the 1327711 IPD070011TW 23277twf.doc/n selection signal. Disabled state. After the above environment settings are completed, the following steps can be performed: First, the system 500 is powered on by the user, or restarted by the system 5 (step S610), and when the system 500 is powered on, The countdown time is started by the timer 511 (step S620). During the countdown period, the baseboard management controller 510 detects whether a timed disable signal transmitted by a general-purpose input/output pin (not shown) of the BIOS system is received to determine whether to cancel the reciprocal of the pause time (step S630). . If 'when the timed disable signal is received, it means the system can be turned on normally.' At this time, the timer 511 will be disabled, the countdown pause time will be stopped, and the current processor and read-only memory will be used to boot. Action (step S640). On the other hand, if the countdown disable signal is not received right, and the countdown of the pause time is completed, it will further compare and judge whether the detection signals received by the respective detection pins (for example, the measurement pin 515) are corresponding to each other. The enable signal for the enable pin (eg, enable pin 512) matches (step § 65〇). If it is determined that the detection signal does not match the corresponding enable signal, the substrate management controller 510 can set the enable signal on the enable pin to the disabled state to disable the corresponding processor (steps). S68〇); conversely, if it is determined that the detection signal matches the corresponding enable signal, the operating state of the processor is consistent with the preset, and thus no action is required on the processor. It is worth noting that if all the detection signals and enable signals are compared and it is found that the two match, then it can be determined that the operating states of all processors ^ 17 1327711 IPD070011TW 23277twf.doc/n are consistent with the preset, this That is, the money processor can normally say that the film that cannot be turned on by the system is operated by β & therefore, it can be adjusted and sent to the read-only memory =====. At this time, the body is restored (step S690). Among them, the selection signal of the switch to the other memory is set to the forbidden heart 2 ^ The selected one is selected as the start-up note 2: then the remaining memory is enabled . Its setting for red selection signal

After the execution of the process of step S680, the crying memory is switched, _ to step S61Q, and the processor and memory of the new step S_ are executed to start a new undershoot: "and switch to cry and 々愔·I# Seto, machine action, so repeat the execution of the inspection office;: select the two groups of memory memory 'the most power-on action, 10,000-the processing of the ==== μ is the (four) domain intercept New Zealand is working normally, and the representative is doing the job.

The switch is also useless. At this point, a warning message can be sent to inform the user to replace the damaged processor or memory. In order to more clearly describe the actual operation of the above method, the following is an example. In this embodiment, it is assumed that the enable signal of the enable pin 512 is set to 1, and if the test module 52 〇 (four) measures the processor cpu 〇, after the working state, the rider operates positively, and the gamma signal sent by the money is also 1 . Therefore, in the case of two-phase comparison, it can be determined that the operating state of the processor CPU() is consistent with the preset without the CPU cpu being disabled; however, if the detection module 520 is detecting the processor CPU After the working state, it is judged that it cannot operate normally, so the detection signal sent becomes 0. This means that 18 1327711 EPD070011TW 23277twf.doc/n The reason why the processor cpuos caused the system to fail to boot up is that the enable signal will be changed to G, and the H CPUG will be processed. In addition, if the processor CPU 〇, _, ..., CPUnq is found after the comparison, the operation white is normal. This means that the problem of the system boot error is that it is recorded, and the memory can be switched at this time. Among them, if the originally set power-on counter is RQM0, then Chengcheng can be powered on by RQM1. From the above, it can be seen that by the power-on switching method of the present invention, the cause of the problem can be found and the remedial action is performed, and the system can be normally started. Finally, referring to FIG. 7 and FIG. 8 , the comparison table of the present invention and the prior art is based on a dual processor (CpU〇 and CPU1) and dual read-only memory (R). The results obtained by the present invention and the conventional techniques are respectively performed on the systems of 〇M〇 and R〇M1). Among them, the part of the prior art in Fig. 7 assumes that the ROM pause time is greater than the FRB pause time; and the part of the prior art in Fig. 8 assumes that the R〇M pause time 丨 and the FRB pause time. In addition, some of the parts marked in the figure are working properly, and the part marked with X means that the operation is abnormal or inoperable. Comparing the results on both sides, it can be found that the use of conventional techniques will still cause many failures in judgment, which will cause the system to never start up normally; relatively, the results of this case can correctly determine the cause of the error, and When two processors or two memories are found to be abnormal, a warning signal is displayed to inform the user to replace, which is obviously more reliable than the prior art. In summary, the multi-processor and multi-memory system boot switching apparatus and method of the present invention have at least the following advantages: 19 1327711 IPD070011TW 23277twf.doc/n Avoiding the 4th judgment system whether a boot error occurs, and avoiding the use of the cutter The error caused by the two timing devices is enough to guide the system to choose to operate properly - rational ^^^^ brother' and do this. R towel handling money miscellaneous execution of the motor 2 / knife through the hard feet and enable the needle enough to occur in the boot error 忤.p〇n_ °. Connected, and crying, and I will find that the error occurred in a forest disorder, I use other processing (four) machine, to achieve normal start-up is to be able to judge the wrong generation of the memory of the inferior (four) Lai Switch to another one for the data. "Let the nuclear can read the correct start-up limit at the next (10) (4) brain as above, but it is not used to get rid of the essence of the invention, the genus, the general knowledge, the 408 and the dry Within the circumference, when a little change and retouching can be made, the scope of the X-protected area is defined by the scope of the patent application attached to the attached [simplified description of the figure] ^ s7F4f know the double processing 11 secret use delete ^ The process of performing (4) is the architecture diagram of the dual BIOS ROM system. The system is shown as the operation flow diagram of the conventional dual BIOS ROM system. 20 1327711 IPD070011TW 23277twf.doc/n Figure 5 is a block diagram of a multiprocessor and multi-memory system according to an embodiment of the invention. Figure 6 is a multiprocessor according to an embodiment of the invention. And a multi-recording-memory system switching method of the booting system. Figure 7 is a comparison table of the present invention and the prior art. Figure 8 is a comparison table of the present invention and the prior art. DESCRIPTION OF SYMBOLS ^ 100: Dual processor system 110, 120: Processor 130: Board Management Controller 131, 132: Enable Pin 133: Error Recovery Power On Timer 140: General Purpose Output Pin 300: BIOS ROM System 310. Input Output Control Chip 311: Select Pins • 312: Read Only Memory Timer 320, 330: Read-only memory • 340: Inverter 350: General-purpose input/output pin 500: Multiprocessor and multi-memory system 510: Baseboard management controller 511: Timers 512, 513, 514: Enable pin 21 1327711 IPD070011TW 23277twf.doc/n 515, 516, 517: detection pin 518: selection pin 520: detection module 530: multiplexer 540: input and output control chip CPU0 'CPU1.....CPUn-1: processor ROMO , ROM1, ..., R〇Mm-1: read-only memory S210 to S280: steps S410 to S470 of the conventional dual processor system using BMC: steps S610 of the conventional dual BIOS ROM system operation ~S690: Each step of the power-on switching method of the multiprocessor and multi-record system of the present invention-embodiment ^ 22

Claims (1)

IPD070011TW 23277twf.d〇c/i X. Application for patents: 1. Multi-processor and multi-memory system boot switching device, configured in the processing of multiple materials and multiple memory systems, including: In the evening, the processing pins are respectively connected to the processors, and each of the pins is adapted to set a enable signal to enable or disable the processors; "Xizheng (8) Sakizaki's foot, respectively, to the processing 11, each of the one-pin is suitable for detecting the state of the corresponding processor material, and obtaining a detection signal; a selection of stitches, Missing these records (4), suitable for setting a selection signal to switch the memory; and a 60-hour benefit, including setting the timeout (Time_〇ut), suitable for when the system is powered on' Starting to count down the pause time, wherein when the countdown is completed, it is determined that each of the processor enable pins ^ The enable signal and each of the processes are consistent with the detection of the detected pin. If the enable signal does not match the detection signal, the processor enables the pin to disable the processor. If all the enable signals and the detection signals match, the memory is switched through the memory selection pins. Two hearts ^ = The multi-processor and multi-memory spears mentioned in the first item are both switched on and off, and include: the alarm is set to be suitable for the memory, such as after the change, still not normal 23 1327711 IPD070011TW 23277twf . doc/n Sends a warning message when you turn it on. 3. The multi-processor and multi-memory switching device as described in claim 1 wherein the memories are read only for the Basic Input/Output System (BIOS). (Read Only Memory, ROM) 〇4. The multi-processor and multi-memory system boot switching device of claim 1, wherein the power-on switching device comprises: In the Baseboard Management Control (BMC) device. 5. The power-on switching device of the multiprocessor and multi-memory system of claim 1, wherein the timer comprises a Fault Resilient Booting (FRB) timer. 6. The power-on switching device of the multi-processor and multi-memory system of claim 1, wherein the enabling signals of the processor-enabled pins are all preset to an enabled state. 7. If you apply for the multi-processor and multi-memory system boot device as described in the section headed by the hometown section, the memory selection pins need to talk about some selection signals, including pre-setting the memory. u rent, T - for the enablement of L 'and the military § ** recall is set to disable state. 8. The multi-processor and switching device of claim 7, wherein when the memory needs to be switched, the setting of the body is set to enable green. : You... The body is set to the disabled state. ~, 'And eight more memory 9_ a multi-processor and multi-memory system, including: 24 1327711 IPD0700HTW 23277twf.doc / n system switching method, in the judgment of the disable signal step, including: Receiving the timer, if the timer disable signal is received, the booting operation is performed by the target processor and the memory. Then sigh somewhere. 22. As stated in the second paragraph of the patent application scope ^ The power-on switching method of the system, in which the temporary sleep = and eve a self is removed (" thinking is included in the basic input output system normal ^ ^ countdown party, the basic input output system cancels the pause time The operation of the multi-processor system according to claim 20, wherein the towel is processed and the steps of switching the memory are further included. If this is not the case, restart the system, and perform the booting operation with the switched processors and the memory. 24. Booting the multiprocessor and multi-memory system as described in claim 20 The switching method, wherein before the system is powered on, the method further comprises: setting all of the enabling signals to an enabled state. 25. The power-on switching method of the multi-processor and multi-memory system according to claim 20, wherein before the system is powered on, the method further comprises: selecting one of the memories as a boot memory, And the corresponding selection signal is set to the enabled state, and the selection signals of the remaining memories are set to the disabled state. 26. The method of switching between the plurality of processors and the multi-memory system of claim 25, wherein the step of switching the memory comprises: setting the selected signal of the memory that is originally selected to be disabled 28 2827711 IPD070011TW 23277twf.doc/n state; and select one of the remaining memories as the boot memory, and set the corresponding selection signal to the enable state. 27. The method for switching the multiprocessor and multi-memory system according to claim 26, wherein the memory is selected, and the system still fails to boot normally, including issuing a warning message . 29