TW200837632A - Boot-switching apparatus and method for multiprocessor and multi-memory system - Google Patents

Abstract

A boot-switching apparatus and method for a multiprocessor and multi-memory system are provided. The apparatus and the method are used in a system having a plurality of processors and a plurality of memories. When booting a system, a single timer is used for counting down a time-out and it is determined whether a disabling signal sent by a Basic Input/Output System (BIOS) is received when counting down. If the disabling signal is not received and the time-out is up, whether the processors can operate normally is detected so as to obtain a plurality of detecting signals. Next, each of the detecting signals and its corresponding enabling signal is determined whether they are matched. If not matched, the corresponding processor is disabled. If all of them are matched, the memory is switched. Accordingly, the situation of misjudgment in the prior art can be resolved and the system can be led to select normal processor and memory for executing booting.

Description

Γ o 200837632 χλ / v/vr xx TW 23277twf.doc/n IX. Description of the invention: [Technical field of the invention] The present invention relates to a booting device and method, and in particular to: the machine timer performs multiprocessing [Prior Art] for switching between devices and multiple memories. In the past 4 years, P has been advancing with the advancement of the technology, and the speed of the processor has also multiplied. In order to achieve leadership status, processor manufacturers Intel and AMD are not working to develop higher frequencies. Processor. B. Today's processing (four) clock cycle has evolved from (10) megahertz (Liz) to 1: megahertz (GHz) or more. However, as the processor clock cycle increases, the complexity of the hardware also increases, and the processor Weishang is in the pursuit of speed 'also means that the speed of the processor still has its limits: Restricted development, other methods are needed at this time. According to this, the multiprocessor architecture has evolved into the latest generation of processor technology, which uses multiple processors in series to achieve multiplex processing. The ideal realm. This multi-processing! When the system is powered on, one of the processors must be selected as the boot (B〇〇tstrap) processor to execute the system boot process, and the rest of the processor is regarded as the application processor to do For the purpose of starting the processor. Among them, when the system is powered on, each processor will perform a built-in self-test function. If any processor has a boot error due to some factor, it will send a status flag to inform the system 5 200837632 xx / v/wx A TW 23277twf.doc/n This situation is handled by the system for subsequent processing. However, if the original boot processor has a boot error, it must use another application processor to replace its task in order to perform the boot function normally. In this case, the conventional practice is to use a false reply to boot

Fault Resilient Booting (FRB) technology, through the Basic Input/Output System (BIOS), Baseboard Management Controller (BMC) or other hard () physical open machine reply action. The following is an introduction to the conventional FRB technology by taking a system including two processors as an example. FIG. 1 is a block diagram of a conventional dual processor system using a BMC for FRB, and FIG. 2 is a flow chart of a conventional dual processor system using a BMC for FRB. Referring to FIG. 1 , in the dual processor system 1 , the processor 11 and the processor 120 are respectively connected to the enable pin 131 and the enable pin 132 of the BMC 130 , wherein the processor 110 is used as a boot. The processor used. In addition, a FRB timer 133 is built in the BMC 130 and is connected to a general purpose input/output (GPI0) pin 140 of the BIOS system. Referring to FIG. 1 and FIG. 2 simultaneously, before the system 100 is powered on, the function of executing the frb by the processor (step S2i〇) is set in the BMC 130, including setting a pause time (Time-out), and enabling the BMC 130. The pin 131 and the enable pin 132 are set to be enabled so that the processor 11 and the process 120 are enabled after being turned on. Whenever the system i〇Q is powered on or reset (step S22〇), the BMC130's FRB timer 133 will be started and the countdown pause will be started. 6 23277twfdoc/n 200837632

Between Vf ί W X Λ. fW^ (step S230) ', it is also judged whether or not the timer disable signal is received (step S240). When the BI0S system successfully performs the power on self test (Power On Self Test, POST), the BMC 130 can be disabled by the general input/output pin 140 to disable the FDB timer 133. At this time, the processor 11 and the processor 120 of the system 1 can continue the normal booting process (step S25). However, if the processor 110 for booting fails when booting, the system 100 cannot be powered on normally, and the FRB timer 133 is not disabled by the BIOS, so when determining the pause time of the FRB timer 133 When the countdown ends (step S260), the BMC 130 turns off the function of the processor 11A by setting the enable pin 131 to 0 (step S270), and restarts the system 100, instead of replacing it by the processor 12〇. The device 110 is turned on (step S280). The above principle is also applied to the double BI〇S read-only memory (Read

Only Memory, ROM) technology, dual BIOS ROM technology as the name suggests is to configure two BIOS ROM on the motherboard to store the BIOS system data, using a dual BI 〇 SR 〇Μ system can avoid upgrading BI Ο S, Because the BIOS file does not match the motherboard, the BIOS file is modified, or the upgrade process is interrupted, the BIOS upgrade fails and the system fails to boot. FIG. 3 is a block diagram of a conventional dual Blss R〇M system, and FIG. 4 is a flow chart showing the operation of a conventional dual BIOS ROM system. Referring first to Figure 3, the BIOS ROM system 300 includes an input/output control (Super 1/0, SIO) die 310, which is transmitted through the address / 7 200837632TW, TW 23277twf.doc/n

The data (Address/Data) line is connected to the read-only memory 320 and the read-only memory 330, and is connected to the read-only memory 320 and the read-only memory 33 by a selection pin 311, wherein It is assumed that the read-only memory 320 is used as the main boot, and the read-only memory 33 is reserved. At this time, the signal sent by the selected pin 311 is 1, and the read-only memory 320 is enabled. After the converter 340 is converted, it is sent to the read-only memory 33 and disabled. In addition, the SIO chip 310 is provided with a R 〇 M f) chronograph 312 for selectively reading Bi 〇 s from the read only memory 320 and the read only memory 330. Referring to FIG. 3 and FIG. 4 simultaneously, after the system 3 is turned on or restarted (step S410), the R〇M timer 312 is started to start the countdown pause time (step S420), and it is determined whether the timer is disabled. The signal can be signaled (step S430). If the BIOS system can normally execute P〇ST, the disable signal can be sent to the SI chip 310 to disable the ROM timer 312 by a common input/output pin 350. At this time, the signal for selecting the output of the pin 3H is not affected, and the drive is still operated by the read-only memory 32 (step S440). However, if the read-only memory 320 has an error during booting, the BIOS system cannot be turned on normally, and the *rX〇m ° ten-day Shoujie 312' cannot be disabled. When the pause time of the ROM timer 312 is judged to be countdown When the process is completed (step S450), the read-only memory is switched (step S460), and the signal sent by the selection pin 311 is set to 〇. At this time, the memory 320 is disabled and is changed to Can read only memory 33〇. After that, the system is restarted, and the boot-only memory 330 is turned on (S470). 200837632 ituu/uunTW 23277twfdoc/n 〇C) ff=说内4 knows 'multi-processing 11 system and double brain s R0M system Tian Yimu uses a 5 tenth state as a switching processor or BI0S R0M If the system is powered on, it may be because one party (for example, the processor) ::= becomes 'when it is not determined whether the error is another party (example: when the deviation is caused) The system restarts, and the result is biD〇sro= can t°, for example, 'assuming that the pause time of the processor is small θ 3 M pause _ 'If it is processed at the time of closing, it can work normally? When 开机M has a boot error, it will be counted down due to processing. 'The system will misjudge the processor and restart it. In this case, it will eventually lead to pure === processor or BI〇S ROM. Unable to successfully start (four) unified open [invention content] change ί ί ί and multi-memory (four) unified boot state, only the detection of the pin debt test processor boot only use the early one to determine the error Ten think too and choose a functioning processor and memory Line boot: or brother's invention provides a multi-processor and multi-memory system, error or cause 2: replace the wrong boot action. -u L, body and this normal execution error is caused by At the beginning of the countdown one pause time, and in the countdown 9 200837632 iruKjfuunrW 23277twfdoc / n = raw == whether an error occurred, and then - ^ The invention proposes a multi-M _. Change device, this device (four) configuration? ^^ memory The system booting and cutting system includes a plurality of processing algorithms and a plurality of memories, a plurality of stats, a "b stitch, a plurality of processor pins, and a eve; a body; a body and a pin and a Timing

Cj chat is divided into _ to the processing *, and two; shooting treatment benefits can have a consistent signal, the transfer _ to the & pin are set: 'and these processors Nine feet apply for compensation and get - _ test signal. The memory is selected as the memory of nq, which is suitable for setting up a lion signal, asking _. Section 11 + includes the pattern - a pause when paused, '* is suitable for the system to start up from the time of the pause time, the temporary generation of the ship is completed, the individual processor enable pins, the enable signal and the various processors If the signal of the _ pin is not the same as the detection signal, then the corresponding processing = the pin can handle the H ban; if the (4) enable signal matches the semaphore', then the memory is selected. The memory used for the stitch switching. In the consistent embodiment of the present invention, the multi-processor and multi-memory system booting device further includes a warning device adapted to be switched on all the memories and the system still cannot be turned on normally. At the time, a warning message is sent. x In one embodiment of the present invention, the memory is a memory input (Basic Input/Output System, BIOS), only read 200837632 iri^u /uui 1FW 23277twf.doc/n memory ( Read Only Memory, ROM). The above-mentioned power-on switching device includes a device configured in a Baseboard Management Control (BMC) device. In addition, the above timer includes a Fault Resilient Booting (FRB) timer. 〇

In an embodiment of the invention, the enabling signals of the processor enable pins described above are all preset to an enabled state. On the other hand, the selection signal of the memory selection pin includes presetting one of the memories into an enabled state, and the remaining memory is set to a disabled state, and when the ▲ needs to switch the memory, the Set another record to enable the evil, while the rest of the memory is set to disable. The present invention proposes a multi-processor and multi-recovery system, which includes two: at =, a plurality of memories, and a power-on switching device. This is turned on to replace multiple processor enable pins, multiple processors, stylus pins, epoch pole selection pins, and a timer. The foot is divided into _ to the processor, and each place: 1 to the moon 匕 pin has a - enable signal, to the processor to ^ ^: to f on the foot are also set to consume the processor, and this = " The processor side pin should be the working of the processor, and the pin is suitable for the debt measurement. The above is the above: Memory:: Served == Memory is selected in these records. In the embodiment of the present invention, the timing is as follows: in the embodiment of the present invention, the method further includes a measurement module disposed between the processing (4) measuring pin and the processor, and is adapted to the processor. Whether to operate positive # ' and send the corresponding test signal to the processor to test the pin. The present invention proposes a booting and switching method for a multiprocessor and a multi-memory system, which is applicable to a system including a plurality of processors and a plurality of memories.

L 200837632 ax / w 11 fW 23277twf.doc/n The device enables the treatment of the needle nucleus. If all the abilities are consistent, then the memory is used to select the stitch switching: 仏 = 仏 in the present invention - In an embodiment, a multiplexer is further included: it is disposed on the memory surface _ and is adapted to be connected to the corresponding memory. The method includes the following steps: First, when the system is powered on, it starts to count down a pause time. In the countdown, it is judged whether the timer is disabled or not. If the timer disable signal is not received and the countdown is completed, the detection is further detected. The processing person is functioning normally and obtains multiple corresponding detection signals. Then, it is determined whether each detection signal is consistent with the corresponding enable signal. If the detection signal does not match the corresponding enable signal, the enable signal is set to disable the sorrow to disable the corresponding treatment; If all the detection signals match the corresponding enable signals, adjust the selection signal sent to the memory to switch the memory for booting. In the consistent embodiment of the present invention, after the step of determining whether the timer disable signal is received, if the timer disable signal is received, the power-on operation is performed with the currently set processor and memory. In an embodiment of the present invention, the manner of canceling the reciprocal of the pause time includes: when the basic input/output system normally performs the power-on action, the reciprocal of the pause time is canceled by the basic input/output system of the 2008 ICDUVUUIITW 23277twf.doc/n. In an embodiment of the present invention, after the step of disabling the corresponding processor and switching the memory, the system further includes restarting the system and performing the booting operation with the switched processor and the memory. In an embodiment of the present invention, before the system is powered on, it is further included that all the enabling positions are set to be blank, and the memory is the boot memory, and the corresponding selection is selected. It can be evil, and the selection signal of the remaining memory is set to the disabled state. In an embodiment of the present invention, the step of switching the memory includes setting the selected job of the original = (4) to the disabled state, and selecting the selected one of the remaining brothers as the boot memory signal. Can state. The choice of ^ In the invention - the implementation of the money, after all the memory has been selected, and the system still can not boot normally, including issuing a warning message. o (4) Material - a timing (four) break (four) of the device or the L body 疋 发生 发生 发生 发生 发生 疋 发生 发生 发生 发生 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Other treatments 11 or remember (four) = lack = _ ruling skills, can not be expected to happen wrong: 2 Shuming's above sum (4) can be more clear money Wensi Temple [Implementation] 13 200837632 ir^/^iifW 23277twf.doc/n When the face error occurs, the FRB timer and the set-up can be used to select the substitute device, and the risk of the existence of the τ is better. The practice is to cry two timings

And when the boot error is found, it is judged that the processor is still ί ίί - two problems, in order to correctly clarify the cause of the error, so that the system can properly select the alternative processing n or memory to start. The present invention is a multi-processor and multi-memory system (start-up switching device and method) developed based on the upper profile. In order to make the content of the present invention clearer, the following is an example of the actual implementation of the present invention. Figure 5 is a block diagram of a multiprocessor and multi-record system according to an embodiment of the invention. Referring to FIG. 5, the multi-processor and multi-memory system 500 includes a baseboard management controller (BMC) 510, a detection module 520, a multiplex port 530, and input/output control. (sUper inpUt/〇utpUt, siq) wafer 54〇, n processor CPU0, CPU1.....CPUn-Ι and m read-only memory 11〇]\40,11〇]\41,." , &〇]^111-1. The read-only memory 110], R〇Ml.....ROM01-1 is, for example, a read-only memory for storing basic input/output system (BIOS) data. The substrate management controller 510 includes enable pins 512 to 514, detection pins 515 to 517, selection pins 518, and a timer 511. The enable pins 512, 513, and 514 are coupled to the processors CPU0, CPU1, and CPUn_1, respectively, and are adapted to provide the substrate management controller 510 with an enable signal to enable the processors CPU0, CPm, ..., CPUn-Ι or Disabled. Among them, the enable signals of these enable pins are generally set to the enable state, that is, 14 200837632 iJKJJU/uuiiiW 23277twf.doc/n said that it is assumed that each processor CPUO, CPU1, ..., cPUn 1 can Normal operation, so when the system is turned on, these processes are first cried CPU0, CPU1, ..., CPUn-Ι enabled. The detection pins 515, 516, and 517 are respectively connected to the processors CPU0, CPU1, and CPUn_1 through the detection module 520, and are used to detect the working states of the CPU0, CPU1, and CPUn-Ι, and obtain a corresponding correspondence. Detection signal. The detection module 520 is configured to detect whether each CPU (CPU0, CPU1, . . . CPUn-1 is operating normally, and send a corresponding detection signal to the detection pins 515-517. In addition, the selection pin 518 is coupled to the only (8) memory ROMO, ROM1, . . . , R〇Mm_l through the multiplexer 530, and is adapted to provide the substrate management controller 510 to set a selection signal for read-only The memory ROMO, ROM1, ..., R〇Mm-1 are switched. Among them, since the system 500 only needs to read the BI〇s data from a read-only memory, the boot operation can be performed, and therefore these are transmitted by the selected pins. In the selection signal of the read-only memory ROMO, ROM1.....R〇Mm-1, for example, only one read-only memory is set to the enabled state, and the remaining memory is set to the disabled state. If the default read-only memory is found to be wrong when booting, and you need to switch to another read-only memory, you can disable this preset only = memory and select another read-only memory. The body is set to enable the evil, in addition, the remaining memory remains in the previously disabled state. Therefore, the function of the switching memory of the present invention can be achieved. Further, the baseboard management controller 510 also includes a timer 511, which is, for example, an error recovery boot (Fault 15 200837632 iruu/υυιι TW 23277twf .doc/n

Resilient Booting, FRB) timer. Since the power supply of the substrate management controller 51 is independently supplied, the user can turn on the power of the substrate management control 510 by turning on the system, thereby setting the pause time of the timer 511 (Time_〇ut). While the power of the system 5 开启 is turned on, the timer 511 starts the countdown pause time. The input/output control chip 540 is connected to the read-only memory ROMO, ROM1.....R〇Mm_1 through the address/data line, respectively, and the & system system 50 is actually turned on according to these read-only memories. Memory R0M (/, 'R〇Ml.....ROM111-1 enabled state, read BIOS system data from the enabled read-only memory. "It is worth mentioning that this embodiment The multi-processor and multi-memory system 5〇〇遂 includes a warning device (not shown), and the warning device is switched in the memory ROMO, ROM1, ..., ROMm-1, and the j 500 is still unable to When the power is turned on normally, a warning message is sent to inform the use of the read only memory ROMO, R0M1.....R0Mm_l m. The present invention also includes the above multiprocessor and multi-memory system, 5〇〇曰The architecture develops a set of power-on switching methods. The following is another embodiment. The above-mentioned processing is a detailed step of signal and resource transfer between the various components in the multi-memory system. Figure 6 is in accordance with the thorn-solid A flow chart of the two processing states and the booting method of the multi-memory system. = Fig. 6' In this embodiment, it is assumed that all the processors can operate normally, which sets the enable signals on all enable pins to the enable state. Also, first select a read only memory to do It is the boot memory, and the selection signal should be set to the enable state, and the remaining read-only memory selections are set to the disabled state. In the above environment, the following steps can be performed: Take the 1* first, the system 500 is turned on by the user, or the system is newly started (step S61〇), and the system and the system are turned on the same day. Then, the timer 511 starts the countdown pause time (step S62〇). θ (When the countdown period, the baseboard management controller 51 will check whether the output pin is output by the BIOS system (the future output will be shown) The transmitted timed disable signal, whether the mosquitoes cancel the reciprocal of the pause time (step S630). Wherein, if the timed disable signal is received, the system _I is normally turned on, and the timer 511 is disabled. , stop the countdown pause time' and The currently set processor and the read-only memory are turned on (step S640). Conversely, if the juice is not received when the juice is not received, and the countdown of the pause time is completed, the side stitches are compared and placed on each side ( For example, it is detected whether the side signal of the pin 515) (4) matches the enable signal of each of the enable pins (for example, the enable pin 512) of the mouse (step S65 〇). + wherein, if the detection signal and the corresponding signal are judged If the enable signal does not match, the substrate management controller 510 can set the enable signal on the enable pin to the disabled state to disable the corresponding processor (step S68〇); otherwise, if the detection is determined If the signal matches the corresponding enable signal, it means that the operating state of the processor matches the preset, so there is no need to perform any action on the processor. It is worth noting that if all the detection signals and enable signals are compared and it is found that the two match, it can be determined that the operating states of all processors 17 200837632 lifUO/uuuTW 23277twf.doc/n are consistent with the presets. It is expected that the processing H can operate normally, so it can be inferred that the reason why the system cannot be turned on is from the read-only domain. At this point, you can adjust the selection signal sent to the read-only memory and switch to another memory (step). In this step, for example, the selected tfl number of the original selected body is set to the domain energy state, and then the selected memory is selected as the boot memory from the remaining memory, and the corresponding selection signal is set to enable. status. After the execution of the processor in step S680 is disabled or the memory switching in step S69 is performed, then the step _step is turned off, the system is restarted, and the processing is performed after the switching = processing and memory execution, so that the inspection is repeated. = and remember, and if necessary, can not handle ^ or switch memory, most: :: with: = a set of normal operating processors and read-only memory implementation. d ’ million--in the above steps _ finally found that all the processing or financial records (four) are not normal u can not be used, then you can send out - then a warning message to inform

The Cj user replaces the damaged processor or memory.

To: more clearly describe the actual operation of the above method, the following is clear. The embodiment assumes that the enable pin 512 is originally set to work; and the right @ test right group 520 is below the side processor CPUO 11 Γ 5 centimeters ^^, then the processor 0 can be determined. Consistent with the preset, without the processor 〇>!;0 disabled; however, the right detection module 520 touches the working state of the c... Therefore, the transmitted _ signal becomes 0. This represents 18

200837632 i^u/uunfW 23277twf.doc/n is the phase that can't be exposed, so it will be enabled, and the processor CPU will be able to. In addition, if it is found after the above-mentioned processors CPUG, CPU1, ..., CPUn], its operation is normal. This means that the memory is switched at this time. The default start-up problem is the job title, and the money is switched to the start-up ^ return. ★ With the power-on switching method of the present invention, the cause of the problem can be found. The system is normally turned on. Finally, the comparison between the present invention and the conventional technology shown in FIG. 7 and FIG. 8 can be applied. The comparison table is based on a dual processor (Cpu〇^ cpui-) and a dual On the system of read-only memory (R〇M〇 and r〇mi), the results obtained by the present invention and the prior art are performed. Among them, the part of the technique = Fig. 7 is the N state of the column R 〇 M pause _ greater than the frb pause time, and the part of the prior art of Fig. 8 assumes that the R 〇 M pause time is less than the FRB material time. In addition, the part of the figure ticked ^ is operating positive $, and the part playing X is abnormal or inoperable. Comparing the results on both sides, it can be found that the technique of knowing the system still causes a lot of judgments. This will cause the system to never start up normally; relatively, the results of this case can correctly correct the cause of the error, and In the case that two processors or _memory are found to be abnormal, prompting the warning minus &amp; to inform the makers is obviously more reliable than Xizhilin. In summary, the multi-processor and multi-memory system boot switching apparatus and method of the present invention have at least the following advantages: 19 200837632 lrj^v/vun TW 23277twf.doc/n 1·Using a single-timer system Whether or not a job error occurs can avoid the use of the error judgment caused by the two timers separately, and can guide the line to select a functioning processor or memory to perform the power-on action. 2. The knife is connected to the processor through the detection pin and the enable pin. However, in the case of a μ error, 'immediately find the processor that has the error' and disable it and use the other device (4) to boot. Achieve the purpose of normal startup. When the η ϋ detection processing state is running smoothly, the error can be judged to be generated by the body, and the memory that is turned on can be switched to another alternative body to enable the system to be enabled at the next startup. The correct boot data. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Retouching, $ The scope of protection of the invention is defined by the patent scope defined by the patent scope [Simple description of the drawing] 〇 9 9 shows the architecture diagram of frjb using BMC for the conventional dual processor system. 2 is a flow chart of a method for a conventional dual processor system to perform FRB using a BMC. FIG. 3 is a block diagram of a conventional dual BIOS ROM system. FIG. 4 is a flow chart showing the operation of a conventional dual BIOS ROM system. 20 23277twf.doc/n 200837632

/.Λ. V/9 V V A A JL W FIG. 5 is a block diagram of a multiprocessor and multi-resonant system according to an embodiment of the invention. FIG. 6 is a flow chart of a method for powering on and off of a multiprocessor and multi-memory system according to an embodiment of the invention. FIG. 7 is a comparison table of the present invention and the prior art. FIG. 8 is a comparison table of the present invention and the prior art. [Main component symbol description] ρ 100 : Dual processor system 110, 120 : Processor 130 : Baseboard management controller 131 , 132 : Enable pin 133 : Error recovery power-on timer 140 · General-purpose input/output pin 300 · BIOS ROM system 310: input/output control chip 311: selection pin CJ 312: read only memory timer 320, 330 · read only memory 340: inverter 350: general purpose input/output pin 500: multiprocessor and multi-memory System 510: Baseboard Management Controller 511: Timers 512, 513, 514: Enable Pins 200837632, rw 23277twf.doc/n 515, 516, 517: Detection Pin 518: Select Pin 520: Detection Module 530: Multiple Worker 540: input/output control chip CPU0, CPU1.....CPUn-1: processor ROMO, ROM1, ..., ROMm-1: read-only memory S210~S280: conventional dual processor system uses BMC for FRB Each of the steps 8410 to 8470 of the method: the conventional steps S610 to S690 of the system operation: each of the multi-processor and multi-symbol system startup switching methods according to an embodiment of the present invention Steps ~ _ Ο 22

Claims (1)

200837632 23277twf.doc/n JLX JL^\J / \J\J xx X. Patent application scope: L A multi-processor and multi-memory system boot switch, configured to include multiple processors and multiple memories One of the systems, including the night processing, is an enable pin, which is respectively connected to the processors, and each of the processor enable pins is adapted to set a uniform energy signal so that the processors can be enabled; The plurality of processor detection pins are respectively coupled to the processors, and each of the processing pins is adapted to detect a working state of the corresponding processor to obtain a detection signal; The memory selection pin is connected to the memory, and is adapted to set a selection signal to switch the memory; and a timer, including setting a pause time (Time_out), suitable for starting when the system is powered on Counting the timeout period, wherein when the countdown time is completed, it is determined whether the enable signal of each of the processor enable pins and the detection signal of each of the processor detection pins are U or not, if so Signal and If the detection signal does not match, the processor is disabled by the corresponding processor enable pin. When all the right signals and the test signal match, the memory is selected through the memory. . ^ 2 · The multi-processor and multi-memory system boot switching device described in claim 1 further includes: a police device, which is not suitable for the 23 23277 twf after the memory is switched. Doc/n 200837632 XX Vf / V \/ XX TW A warning message is issued when the power is turned on. 3. The power-on switching device of the multi-processor and multi-memory system according to claim 1, wherein the memory is a read-only memory for storing a basic input/output system (BIOS). Read Only Memory (ROM). 4. The power-on switching device of the multi-processor and multi-memory system of claim 1, wherein the power-on switching device is disposed in an O-Baseboard Management Control (BMC) device. 5. The power-on switching device of the multi-processor and multi-memory system of claim 1, wherein the timer comprises a Fault Resilient Booting (FRB) timer. ^6. The multi-processor and multi-memory system booting device of claim 1, wherein the enabling signals of the processing inspecting pins are pre-set to an enabled state. 1. 7. For the towel, please turn over the turn-on county of the multi-nucleus mentioned in item i. The memory selection pins include =, and the selection (4) includes pre-setting the memory. And the rest of the memory is set to disabled. ~b / 8. The multi-processor system boot switching device according to claim 7, wherein when the memory (four) is required to be switched, the memory is set to be 12 ~ Gan Shou 则 is set to disable state. 4 hearts, while the rest of the memory 9 · a multi-processor and multi-memory system, including 24 200837632 AjL j-xv / / w j. jl IW 23277twf.doc / n multiple processors; multiple memory; The switching device includes: a plurality of processor-enabled pins, each of the processor-enabled pins being adapted to be set up, and connected to the processors, capable of being capable of causing the signals to enable or disable Processors detect stitches, o Suitable for _ such as =: Set a selection signal 'two times = to = _ 'suitable for you y J timer' including setting - time-om, suitable for when the system is turned on, Starting to count down the pause time, wherein when the countdown is completed, it is determined whether the enable signal of each of the processor enable pins and each of the secrets!! The side pin_axis test signal matches, ^ If so If the chaotic number does not match the test signal, the processor is disabled by the corresponding processor enable pin. If all the enable signals and the detection signals match, then the choice is made through the note. The pins switch the memories. 10. The multi-processor and multi-memory system as described in claim 1 further includes: a warning device adapted to issue a warning message when the memory is still not turned on normally after the memory is switched. Multi-processor and multi-memory 25 described in 25 items ο 200837632 iruviKjyjii fW 23277twf doc/n ιι·If you apply for the patent range body system, it also includes: Call one: two two Γ placed in the memory selection pins and these Between the memories, it is suitable to transfer the face selection to the corresponding memory. The system is configured to detect the presence or absence of the processor between the processor detection pins and the processors; the detection signals are The processor detects the pin, the multi-processor and multi-memory system described in the first aspect of the patent range 13H, and further includes an input/output control chip, which is suitable for gesturing emotional connection, ton according to remarks, (4) tti miscellaneous The line and the enabling state of the body are selected to receive one of the basic wheel-in and turn-out systems by one of the memories. The two-machine_bee material as described in claim i. &amp; body system, wherein the memory is a memory of one and two memories. i. This is a multi-processor and multi-memory system as described in the second item, and the money switching device includes a configuration in the substrate management control device. 1 Lay and multi-memory systems, and juices include an error-return boot timer. π·^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ status. 18. The method as claimed in claim 1 , wherein the plurality of processors and the plurality of memories comprise a pre-set memory of the memory, wherein the surface selection signal package is set to an S recording state. . ', 1 enable state, and the rest of the memory, 18 of the multi-processor and multi-memory system, where when you need to switch 兮t The other of the Lj bodies is set to enable, including the separation of these memory energies. This version of the complaint, and the rest of the memory is set to ban 20 ·, the processing of the benefits and multi-memory system boot switching method, for the application of a processor and multiple memory, the following steps: When the countdown pause time is started, = is the timer disable signal; if the timer does not receive the timer disable signal and the countdown is completed, it detects whether the location is working properly and obtains the corresponding Sampling test signal; whether each of the detection signals is consistent with the corresponding consistent signal; if the detection signal does not match the corresponding enable signal, the enable signal is set to the disabled state, The processing of the H ban can be performed; and if all of the stimuli signals are consistent with the corresponding enable signals, the lobes are sent to the plurality of selection signals of the ticks to switch the memories. body. 21·Multi-processor and multi-memory as described in claim 20 of the patent scope 27 200837632 .........rW 23277twf.doc/n method==When judging whether to receive or not, the timer port right receives the timer disable signal , the current setting device and the memory to perform the p money action. ~ Department 22 · Multi-processor as described in the second paragraph of the patent application. = When the basic input wheel-out system performs the power-on action normally, the reading area μ input-output system cancels the reciprocal of the pause time. The method of multi-processor and multi-command _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ σ. Not restarting the system, restarting the system, and performing the booting action with the switches and the counters. Ο / 24· The method for switching the multi-processor and multi-memory system according to the second aspect of the application, wherein before the system is powered on, the method further comprises: setting all the enabling signals to enable status. 25) The method for switching the multiprocessor and multi-memory system according to claim 20, wherein before the system is powered on, the method further comprises: selecting one of the memories as a boot memory. And setting the corresponding selection signal to the enabled state, and the selection signals of the remaining memories are set to the disabled state. 26. The method of switching between the multiprocessor and the multi-memory system of claim 25, wherein the step of switching the memory comprises: setting the selected signal of the memory selected to be prohibited The energy state 28 200837632TW 23277twf.doc/n state; and select one of the remaining memories as the boot memory, and set the corresponding selection signal to the enable state. 27. The method for switching the multiprocessor and multi-memory system according to claim 26, wherein the memory is selected, and the system still fails to boot normally, including issuing a warning message . ί) 29