TWI326983B - Phase-locked loop having level-shift circuit - Google Patents

Description

1326983 • Nine, invention description: [Technical field of the invention] The present invention relates to a phase locked loop (PLL), particularly relating to a high frequency voltage shift using a Neil process (techn〇i〇gy) The circuit is interesting. [Prior Art] The picture of Ludi 1 is a conventional phase-locked loop 1 〇〇, which includes a Phase-Frequency Detector (PFD) 102, a charge pump 104, and a primary loop filter (i). 〇op fiiter)1〇6, and a Voltage Controlled Oscillator (VCO) 108. The adaptive filter 106 includes a resistor & and two m〇S capacitors Mi • and Μ2. The charge pump 104 and the loop filter 16 are consumed by a control terminal of the voltage controlled oscillator 108. The voltage at the control terminal is vcm. The voltage controlled oscillator 108 generates a clock signal CKvco and adjusts the frequency of the clock signal CKvco in accordance with the voltage φ Vcnt. The phase frequency detector 1 〇 2 detects a phase frequency difference between the clock signal CKvco and a reference clock signal CKref. If the frequency of the reference clock signal CKref is higher than the frequency of the clock signal CKvc〇, the up pulse of the phase frequency detector 1 〇2 outputs an up pulse, and the MOS capacitor and the Μ2 are charged; The DN end of the phase frequency detector 102 outputs a DN pulse, and discharges the M〇s capacitance Μ and Μ. The voltage vent of the control terminal changes the frequency of the clock CKvco with the charge and discharge of the MOS capacitors 1 and Μ: According to the above action, the phase locked loop 1〇〇

Client's Docket N〇.:VIT06-0060 TTss Docket No:0608-A40833-TW/Final /Glorious Tien 1326983=No. CKVG (4) Complex (4) _ pulse money CKref frequency π The same process of semiconductor components can be classified according to the transistor gate thickness High-voltage devices and low-voltage components (i〇w_voltage (4) are called two types. High-voltage components have a thick oxide layer (thick_〇xide), using a higher power supply. Low-voltage components have a thin oxide layer (thin_〇xide), use

The car's low power. In Fig. 1, the charge system 1G4 is also a high voltage component, and the power source used is a higher power supply VDDH. To save cost and wafer area, the capacitor used in the loop filter 1〇6 is a MOS capacitor (such as a MOS capacitor). Μι and %). In the rice-removing process, too thin a gate thickness will cause the MOS current to easily leak current.) Therefore, the voltage must be high voltage to realize the loop filter i〇6: (10) Capacitance. The MOS capacitor must operate in a specific interval to have a 疋1 valley. For example, in the high-voltage component of the 90 nm process, the voltage of the nm〇s capacitor must be greater than 0.8 volts (approximately greater than twice the threshold voltage) to have a fixed tantalum capacitance, so the control of Figure 1 is at 0.8 volts. (4) The voltage W1 of W must be large in the high-frequency phase-locked loop for energy consumption. The power supply used for the voltage-controlled oscillation is the upper limit of the voltage of the lower power supply terminal 値vent. The high-frequency clock signal is simultaneously reduced by 108. A low voltage component, Vddl, must be used. The low power supply will limit this. In the first smallest operating range, the voltage 値Vcnt at the control terminal of the figure will be limited to 'the voltage that controls the gain of the voltage.

Client’s Docket No.: VIT06-0060 TT's Docket No: 0608-A40833-TW/Final /Glorious Tien 1326983 (kvco) must be large to greatly adjust the frequency of the clock signal CKvc〇. Taking the 90 nm process as an example, Vddh is 25 volts and Vddl is j 2 volts. The voltage Vcnt has an operating range of 〇 8 to 〇 9 volts. In addition, since the voltage 値Vcnt of the input terminal of the voltage controlled oscillator 1〇8 is affected by the noise of the power supply VDDH, the low power supply Vddl used by the voltage controlled oscillator 108 is different from the high power supply vDDH, so the lock Phase loop 100 is more sensitive to power supply noise. [Summary of the Invention]

The invention provides a phase locked loop (PLL) with a voltage shift circuit, which includes a phase frequency detector (Phase)

Frequency Detector (PFD), a first charge pump, a loop filter, a voltage shifting circuit (ievel_shift circuit), and a voltage controlled oscillator (v〇ltage c〇ntr〇1 〇 Scillat〇r, vco). The capacitor in the circuit chopper is a M〇s capacitor and belongs to a high-voltage device for the purpose of avoiding leakage current. The voltage controlled oscillator is a low voltage component (l〇w-v〇itage device) for generating a high frequency clock signal while reducing energy consumption. The first charge pump and the gate of the M〇s capacitor are coupled to a first control terminal. The voltage shifting circuit and the voltage control oscillator are coupled to a second control terminal. The voltage displacement circuit generates a voltage drop between the first control terminal and the second control terminal. According to the clock signal, the phase frequency detector controls the first charge to charge and discharge the MOS capacitor of the loop filter to adjust the voltage 値' of the first control terminal to change the voltage 値 of the second control terminal. According to the voltage 该 of the second control terminal, the voltage control oscillator adjusts the CUenrs Docket No. of the clock signal: VIT06-0060 s Docket No: 0608-A40833-TW/Final /Glorious Tien 7 1326983 frequency size. The voltage shifting circuit of the phase locked loop includes a source follower. The source follower is an NMOS transistor and is a high voltage component. The voltage drop is the gate-to-source voltage drop of the NMOS transistor. The voltage shifting circuit may further include a unity-gain buffer. The input and output terminals of the unity gain buffer respectively connect the source of the NMOS transistor and the second control terminal. Further, the above voltage controlled oscillator may be a supply-regulated VCO. The power regulating voltage control oscillator uses the voltage 値 of the second control terminal as a power source, and adjusts the frequency of the clock signal according to the voltage 该 of the second control terminal. The phase locked loop may further include a second charge pump and a resistor. The two ends of the resistor are respectively connected to the output end of the unit gain amplifier and the second control end. The output end of the second charge pump is connected to the second control terminal. The second charge pump is a low voltage component. [Embodiment] Hereinafter, several embodiments of the present invention will be described with reference to the drawings. 2 is an embodiment of the present invention, the phase locked loop 200 with a voltage shift circuit includes a phase frequency detector 202, a first charge pump 204, a loop filter 206, a voltage shift circuit 208, and a voltage control. Oscillator 210. The capacitance of the loop filter 206 is the M0S capacitor and the MO. The loop filter 2〇6 is a high voltage component to prevent leakage current. The voltage controlled oscillator 210 is a low voltage component to produce a high frequency clock signal CKvco while avoiding excessive energy consumption. The first charge pump 2〇4

Clients Docket N〇.:VIT06-0060 1T^ Docket No:0608-A40833-TW/Final /Glorious Tien 1326983 The output end and the MOS capacitor called m2 are connected to a first control end, the first - The voltage at the control terminal is I. Taking the second figure as an example, the closed pole is coupled to the first control terminal via a resistor R], and the gate of the triple current M2 is directly connected to the first control terminal u. The electric waste displacement circuit is closely connected to the voltage control oscillator 21 to a second control end, and the second control end is the control end of the voltage control (4) 21Q, and the voltage 値 is the voltage displacement circuit 2〇 8 generating a voltage drop between the first control terminal and the second control port, so that the voltage and the heart position of the second control terminal are at a lower voltage level to expand the operation of the control terminal of the voltage controlled oscillator 210. voltage range. As shown in Fig. 2, the clock signal CKvc is input to the phase frequency detector 2〇2 after being divided by a reference clock signal CKref to determine whether the frequency of the clock signal CKvco needs to be adjusted. According to the signals up and DN output by the phase frequency detector 2〇2, the first charge pump 204 charges and discharges the MOS capacitors 与1 and M2 to adjust the voltage vcntl′ of the first control terminal to adjust the first The voltage of the second control terminal is vcnt2. The voltage controlled oscillator 210 adjusts the frequency of the clock signal CKvco according to the voltage 値Vcnt2 of the second control terminal. Voltage shift circuit 208 includes an NMOS transistor M3. The NM0S transistor M3 is a high voltage component that operates in a source follower type with a voltage drop Vgs3 between the gate and the source between the first control terminal and the second control terminal. Pressure drop. The voltage shift circuit 208 further includes a unity-gain buffer 212. The input and output terminals of the unity gain buffer 212 are respectively coupled to the source of the NM0S transistor M3.

Client's Docket N〇,: VIT06-0060 TT^ Docket No: 0608-A40833-TW/Final /GloriousTien 9 and the control terminal of the voltage controlled oscillator 210. The first charge pump 204 is a high voltage element, and the power supply Vddh. The voltage control oscillator 21's power is the same as the 90 nm process, ν_ is 25 volts, and the power supply VDDL. VSS3 is 0.6 volts. The voltage of the first control terminal is v, .2 volt, and the MOS capacitors m and m2 can have; the capacitance ': 〇.8 volts:' The voltage controls the control terminal of the vibrator 210, ::

It is around 0.3 to 0.9 volts. Since the voltage v蛊 (10) 2) knows that the pressure difference between you and cntlxing Vcm2 is 〇 6 = temple, the voltage of the first control terminal is 値^ 〇, to = special. Compared to the first! The voltage of the graph is in the range of V ridge. 8 = =), the recommended capacitance m々m2 in Figure 2 can higher the gate voltage to ensure that the brain capacitance Μ 1 "has a capacitor 値. Because the operating range of pVent2 with the m range of operation is greater than two reasons: (4) Controlling the gain of the oscillator 210 (Kvc〇) does not require a voltage like

: The gain of the oscillation S 1G8 is as large, and the jitter effect of the clock signal CK is also relatively improved. 3 is another embodiment of the present invention. The voltage controlled oscillator used in the phase locked loop 300 with a voltage shifting circuit is a supply-regulated VCO 312. The voltage value of the control terminal of the power regulation voltage control oscillator 302 (i.e., the voltage Vcnt2 of the second control terminal) is directly used as the power source of the power supply regulation voltage control oscillator 302 to adjust the frequency of the output signal CKvco. The other units and operations of the phase locked loop 3 are the same as those of the phase locked loop 200. 4 is another embodiment of the present invention, with phase lock of a voltage shift circuit

Client’s Docket No·:VIT06-0060 TT*s Docket No:0608-A40833-TW/Final /Glorious Tien

Loop 400 is a dual path phase locked loop. Φ 勹 』 ^ 1 40U Y includes a phase frequency detector 402, a first charge pump 4〇4, a loop filter (composed of MOS capacitor Μ*)' a voltage displacement circuit 4〇6, a 2 resistance I, A second charge pump 408, and a voltage controlled oscillator "b-, phase-locked loop 200, the phase-locked loop 4 〇〇 mainly has a resistor & 盥 first ~ charge pump 408. The voltage shift circuit 4 〇 6 A pressure drop v, = and a voltage drop across the electric (four) provide a dust fall of the first control terminal (VcnU) and the third control terminal (V(10)), wherein the second charge is completely low voltage Component 2 = the power source used is the same as the voltage control oscillator 41Q is the low power supply V 〇 DL. - The phase-locked loop of the present invention divides the voltage-displacement circuit between a high voltage component and a low voltage component to reduce the The voltage of the high voltage component provides the appropriate electrical signal to the low voltage component. Any phase locked loop including the voltage shifting circuit belongs to the present invention. The voltage shifting circuit is not limited to the above embodiment. The mentioned device that has the function of (4) can also be realized by the time: The phase-locked loop of the present invention can be fabricated in a nanometer process. The loop-connector of the phase-locked loop is a high-voltage component that "reduces leakage current. The voltage-controlled oscillator of the phase-locked loop is a low-voltage component for generating a high-frequency clock signal while reducing energy consumption. The above examples are intended to aid the understanding of the invention and are not intended to limit the scope of the invention. Any device or technology that meets the scope of the claims below is intended to be within the scope of the invention.

Client's Docket N〇.:VIT06-0060 TT's Docket No:0608-A40833-TW/Final /Gl〇ri〇us Tien 1326983 [Simplified Schematic] Figure 1 shows the traditional phase-locked loop; Figure 2 shows the present invention. An embodiment of a phase locked loop; and Fig. 3 is another embodiment of a phase locked loop of the present invention; and Fig. 4 is another embodiment of a phase locked loop of the present invention. [Main component symbol description] 100~ traditional phase-locked loop; 102~phase frequency detection is 104~electricity, 106~loop filter; 108~voltage controlled oscillator 200, 300, 400~ phase-locked loop of the present invention 202~ phase frequency detection descent, 204~ electric Ho, 206~ loop filter; 208~ voltage shift circuit; 210~ voltage controlled oscillator; 212~ unity gain buffer 302~ power regulating voltage controlled oscillator; 402 ~ phase frequency detector; 404 ~ first charge pump; 406 ~ voltage shift circuit; 408 ~ second charge pump; 410 ~ voltage controlled oscillator; CKref ~ reference clock signal; CKvco ~ clock signal;

Mi, M2, M4~MOS capacitor; M3~ NMOS transistor belonging to high voltage component;

Rl, R_2~ resistance,

a control terminal of the Vcnt~voltage controlled oscillator 108;

Vcnti~first control terminal; Vcnt2~second control terminal;

Client’s Docket No.:VIT06-0060 TT's Docket No:0608-A40833-TW/Final /Glorious_Tien 12 1326983

Vddh~ surface power supply; Vddl~ low power supply;

Vgs3 ~ NMOS transistor 1 ^ 3 gate to source voltage drop; UP, DN, UP1, DN1, UP2, DN2 ~ phase frequency detector output signal.

Client's Docket N〇.:VIT06-0060 TT's Docket No:0608-A40833-TW/Final /Glorious Tien 13

Claims (1)

1326983 Case No. 095144189 December 1, 1998 Revision of this amendment Ten, the scope of patent application: - a * - 1. A phase-locked loop with a voltage displacement circuit, including: .. a phase frequency detector for detection a phase signal difference between a pulse signal and a reference signal to generate an output signal; a first charge pump coupled to the phase frequency detector; a loop filter comprising a MOS capacitor, the MOS capacitor being a south voltage component, the MOS capacitor is connected to the first control terminal and the first control terminal; φ a voltage controlled oscillator is a low voltage component for use according to a second control terminal a voltage 値 adjusts the frequency of the clock signal; and a voltage shifting circuit, a resistor and a second charge pump, the voltage shifting circuit adjusts the potential of the first control terminal by a voltage drop and then is connected to the potential through the resistor An output terminal of the second electrical source and an output end of the second electrical component are coupled to the second control terminal; wherein the first charge pump is configured according to the output signal of the phase frequency detector The M The OS capacitor is charged and discharged to adjust the voltage of the first control terminal. 2. The phase-locked loop with a voltage displacement circuit according to claim 1, wherein the voltage displacement circuit comprises a source follower, the source follower is an NMOS transistor and is a high voltage The voltage drop is the voltage drop between the gate and the source of the NMOS transistor. 3. The phase-locked loop with a voltage displacement circuit according to claim 2, wherein the voltage shifting circuit further comprises a unity gain buffer, wherein the input and output terminals of the unity gain buffer are respectively coupled to the NMOS Power Client's Docket No: VIT06-0060 TT's Docket N〇: 0608-A40833TW-10142009 - No scribe version 14 1326983 One of the crystal source and the above resistor. 4. The phase locked loop with a voltage displacement circuit according to claim 1, wherein the first charge pump is a high voltage component. 5. The phase-locked circuit with a voltage-displacement circuit as described in claim 1 is manufactured by a nanometer process. 6. The phase-locked loop with a voltage-displacement circuit according to claim 1, wherein the voltage-controlled oscillator is a power-regulated voltage-controlled oscillator, and the voltage value of the second control terminal is directly used as The power supply regulates one of the voltage control oscillator power signals to adjust the frequency of the clock signal. 7. The phase locked loop with a voltage displacement circuit according to claim 1, wherein the second charge pump is a low voltage component. Client’s Docket No.:VIT06-0060 TT’s Docket N〇:0608-A40833TW-10142009-No underlined version 15