1326906 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種記憶元件，特別係有關於一種具有高密度記憶 元件之罩幕式唯讀記憶體的製造方法與構造，可增加處理資料的位 元數提高記憶體之可處理之資料量。 【先前技術】 非揮發性記憶體所儲存之資訊即使切斷電源資料也可保持不受 損失。按照所儲存資料之可否抹除又可分為罩幕式唯讀記憶體 (Mask ROM)、包括電氣式可程式化唯讀記憶體(EpR〇M)、電氣 式可抹除程式化唯讀記憶體（EEPR0M)、快間記憶趙（Flash Memory)。其中快閃記憶體已被廣泛使用於例如記憶卡、個人數位 助理(PDA)、隨身碟、及MP3播放器等高容量資料儲存。因此這樣 的應用需要採用高密度而低成本記憶.鱧，即較小的單元尺寸與較低 之製造成本》 反或閘（NOR)型堆疊閘極快閃記憶體單元典型上具有一位元 線接點、一源極區、一浮動閘極、及一控制閘極，且控制閘極係直 接位於浮動閘極上方’如此的單元之相對尺寸使得它們無法被使用 於非常高密度資料儲存應用中。 在具有一序列串聯連接在位元線與源極線間之反及閘(nand) 型堆疊閘極快閃記憶體單元陣列中，可以得到較小之單元尺寸。請 參考第la圖’第1圖係顯示習知之反及閘(NAND)型堆疊閘極快閃 記憶體單元陣列示意圖。 當習知之乓及閘(NAND)型堆疊閘極快閃記憶單元欲進行寫入 化動作時’係於控制閉極職與汲極腕上施加高電壓電子即 從矽基底101之源極l〇8a穿過串聯之通道與源沒極區產生熱電子而 進入淨動閘極103a。因此浮動閘極驗儲存有負電荷，堆養閉極 5 '5 快閃記憶單元的臨界電壓上昇β 請參考第lb圖，第lb圖係顯示習知之反及型堆疊 閘極快閃記憶單元之抹除示意圖。當習知之反及閘（NAND)型堆疊 閘極快閃記憶體欲進行抹除動作時，係於控制閘極1〇31)上施加負$ 壓或零電壓，树基底1〇1之祕隐施加高電壓，電子即從浮動 閘極103a穿過閘極氧化層回到之汲極1〇8a。堆疊閘極快閃記憶單 疋的5¾界電壓因此下降。 藉由改變堆疊閘極快閃記憶單元的臨界電壓，欲讀取資料時， 如第lc圖所不將選定之字元線接地或零電麼，可以由堆叠閘極快閃 S己憶單元下方之通道係在導通狀態或非導通狀態而判斷為邏 輯” Γ或邏輯” 〇”。 反及閘(NAND)躲疊祕快耽憶體單元健f要—浮動間 極及-控綱極’ S此，該雙·單元之製程相對複雜使得它們無 法使用單閘極的邏輯製程技術來生產。 【發明内容】 有鑑於此’本發明之目的在於提供一種單閘極邏輯製程相容的 南密度記憶元件，且在具有相同密集度之電晶體的情況下可 增加處理㈣的位元數及提高網記憶趙之可處理的資料容量。 根據上述目的，本發明提供—種高密度記憶元件之製造方法， 包括下列步驟：提供-半導縣底，其中該半轉基底上形成有— 閉極介電層、一導電層及一第一圖案化光阻層；，以該第-圖案化 光阻為罩幕侧該導電層轉成—·:去除該第—圖案化光阻； -第一圖案化光阻層具有—開口，該開口露出部分之該閘極表面及_ 該閘極其中-側之半導體基底表面：⑽第二圓案化光阻層為罩 幕，對露出表面之_極其巾—側之半導縣底進行離子植入 形成源沒極延伸區及一可自由選擇有無之口袋摻雜；去除該第二圖 案化光阻層，並進行熱氧化處理及沉積多層介電層於該問極側壁， 將該多層介電層_勤形成—由下而上依序為氧化層/電荷捕陷 詹/介電層之複合介電層間隙壁；以職及閘極關之複合介電層間 隙壁為罩幕，對半導體基紐行離子獻，以在半導體基底上形成 一源汲極摻雜區並絲露出表面之氧化層；及於露出表面之間極及 源汲極區之表面上形成一金屬半導體化合物。 根據上述目的’本發明再提供一種記憶元件之操作方式，包括： 一半導體基底；複數個電晶體，形成於該半導體基底上，其中每個 電晶體包含：-_介電層，形成於該半導體基底上；—閘極形 成於該閘極介電層上；一間隙壁，形成於該閘極之側壁；一可開關 之通道’位於該閘極介電層之下；一自由選擇有無之源汲極延伸區， 形成於該半導體基底内，並位於該閘極其中一側之間隙壁之下且 該源汲極延伸區與通道摻雜電性相反；一自由選擇有無之口袋摻 雜，形成於該半導體基底内，並位於該源汲極延伸區之下，且該口 衣捧雜與源沒極延伸區推雜電性相反；一滅沒極區，形成於該半導 體基底内，並與該通道或源汲極延伸區之外側相連，且該源汲極區 與源汲極延伸區摻雜電性相同；其中閘極介電層之厚度為20 A.至 200A ’鵁間隙壁之底部寬度為200 A至2000A。 該複數個電晶體經由該通道、源汲極區及可自由選擇有無之該 源汲極延伸區相連接而形成串聯通道；一第一源汲極區形成於該串 聯通道之一端；以及一第二源汲極區形成於該串聯通道之另一端。 欲璜取任一電晶體之第一記憶單元包括下列步郵：選擇一欲讀取之 電晶體；於該電晶體之閘極上施加一閘極讀取電壓；於該串聯通道 的其他電晶趙之閘極上施加一閘極強制導通電壓；於該第二源汲極 端施加一第一電壓，且於該第一源汲極端接地或施加一較該第一電 壓接近零電位之第二電壓，當該第一源汲極端與該第二源汲極端間 具有-導通電流，即該第-記憶料之讀取值為i;及當該第一源 及極端與該第二源汲極端間僅具有—小_導通電流之漏電流，即 該第一記憶單元之讀取值為0。 认5貝取任-電晶體之第二記憶單元更包括下列步驟：選擇一欲 磧取之電晶體；於該電晶趙之閘極上施加一閘極讀取電壓；於該串 聯通道的其他電晶趙之閘極上施加一閘極強制導通電壓；於該第一 源汲極端施加-第三電壓’且_第二源祕端接地或施加一較該 第三電壓接近零f位之第四電壓，當該^祕端無第工源沒 極端間具有-導通電流，即該第二記憶單元之讀取值為i ;及當該 第-源汲極端與該第二源沒極端間僅具有一小於該導通電流之漏電 流時，即該第二記憶單元之讀取值為〇 ^ 欲抹除任一電晶體之第一記憶單元包括下列步驟：選擇一欲抹 除之電晶體；於該電晶體之閘極上施加—閘極抹除電壓；於該串聯 通這的其他電晶體之閘極上施加一閘極非抹除導通電壓；於該第一 源没極端施加一第一抹除電壓。 其中欲抹除任一電晶體之第二記憶元#更包括下列步驟：選擇 i抹除之電aa體，於該電晶趙之閘極上施加一閘極抹除電壓；於 該串聯通道的其他電晶體之閘極上施加一閘極雜除導通電壓；於 該第一源沒極端施加一第二抹除電虔。 I寫入至少一電晶體之第一記憶單元包括下列步鄉：選擇至少 一欲寫入之電晶體；於選擇之電晶體閘極上施加一閘極寫入電壓； 於該串聯通道的其他未選擇之電晶體閘極上施加一閘極非寫入強制 導通電壓；於該第一源汲極端施加一第一寫入電壓；於該第二源汲 極端施加一第二寫入電壓。 欲寫入至少一電晶體之第二記憶單元更包括下列步驟：選擇至少 一欲寫入之電晶體；於選擇之電晶體閘極上施加一閘極寫入電壓，· 於該串聯通道的其他未選擇之電晶體閘極上施加一閘極非寫入強制 一第三電壓；於該第二源汲極端 導通電壓；於沒極端施加 施加一第四電壓。 【實施方式】 第一貫施例. 2a 2j圖’第2a~2j圖係本發明之高密度記憶元件之 第-貫施例之製造流程及操作方式示意圖。 考第以圖’於半導體基底2〇1上依序形成閘極介電層 、導電層203及第-圖案化光阻層2〇4。其 ^是蝴；嶋冑請增⑽A i ===； 疋乳化層或〶介電係數材料，氧化層例如是二氧切，高介電係數 材料之介電係數為4至100 ’例如是五氧化二組(Ta2〇5)、氧化紹 (A1203)、氧化锆(Zr02)、氧化給_2)、氧化亂伽⑼氧化 纪(Y203)其中之一；導電層2〇3之厚度大約是_至25〇〇A，材質 例如是多晶i夕層。 參考第2b ® ’以第-圖案化光阻層2〇4為罩幕钱刻導電層 203 ’使導電層203形成複數個閘極2〇3a，然後去賴案化光阻層 204。 曰 請參考第2c圖接著以第二圖案化光阻層207及閘極2〇3a為罩 幕’對半導體基底201進行摻雜步驟，以在閘極2〇3a側邊之半導體 基底201上形成一源沒極延伸區208 (source/drain extension) » 請參考第2d圖，將第二圓案化光阻層207移除後，將露出表面 之閘極介電層202去除’而留下閘極203a下方之閘極介電層2〇2a， 於半導遨基底έ〇1及閘極203a之表面上順應形成一氧化層2〇5a與 電荷捕陷層205b’氧化層205a厚度為20至200A，材質例如是二氧 化矽；電荷捕陷層205b為高介電係數材料，介電係數為介於3至 100之間，材料為五氧化二鉅(Ta205)、氧化鋁（Ai2〇3)、氧化鍅 (ZrCL)氧化給（Hf02)、氧化釓(Gd2〇3)、氧化|乙(γ2〇3)其中之 一。接著，繼續在電荷捕陷層2〇5b的表面上順應形成一介電層2〇6, 介電層206例如是氧化層，如第2e圖所示。 請參考第2f圖，對介電層206進行非等向性钱刻，以在閘極 203a之側壁形成一間隙壁施。其中，非等向性姓刻的方法例如是 反應性離子姓刻(reactive ion etching，WE)或電漿蝕刻（piasma etching)。 以閘極203a及間隙壁206a為罩幕，對半導體基底進行離子植 入步驟，以在半導體基底2〇1形成如第2g圖所示之源汲極2〇如。 其中，植入之離子例如是含有砷、磷或硼離子或其中兩者以上之組 合。因為間隙壁206a有遮蔽的效果，因此在離子植入的步驟中，閘 極形成一側的半導體基底2〇1上之源汲極與閘極下方通道間會有一 源没極延伸區208 ;而另一側的閘極下方通道與半導體基底2〇1上 之源汲極208a之間並無源汲極延伸區。 清參考第2h圖，將露出表面之氧化層2〇5a去除，然後對閘極 203a與半導體基底201進行自行對準矽化步驟，以在閘極2〇3a'源 沒極區208a之表面上形成金屬石夕化物209，以利後續之源沒極及閘 極導通之用；其中，金屬矽化物209例如是二矽化鈦(TiSi2)或二矽 化姑(CoSi〗)或梦化錄(NiSi)。 請參考第2i圖’該圖例說明本發明之後段金屬連線製程，其中 先沉積一層絕緣物，材質包含有二氧化矽、氮氧化物或該兩者之多 層組合；接著，繼續在絕緣層210中形成一接觸窗(Contact)及金屬 插塞(Meta Plug)211，接著在絕緣層210之上形成第一層金屬連線 212。 ' 請參考第2j圖’該圖例說明本發明之複數個電晶體的通道經由 該源汲極區或該源汲極延伸區相連接而形成一串聯通道，由左至右 具有的四個位元，圖中藉由寫入間隙壁下方之電荷捕陷層獅之熱 電子，可控制心寫入之資料被定義成為或“1” ， 第2j圖中串聯通道上的箭頭是指在施加讀取偏屋時的通道載 子流動方向’其讀取任-電晶體之記憶單元包括下列步驟：選擇一 欲讀取之電晶體；於該電晶體之，2G3a上施加—閘極讀取電壓； 於該串聯通道上的其他電㈣之·施加關導通電壓；於 該第-源沒極區施施加-汲極讀取糕’且於該第二源及極區 209b施加接地電壓；該第-源汲極區廳與該第二源沒極區獅 間具有導通之通道載子電流時’即該左側位元記憶元件之讀出值為 1;該第一源汲極區209a與該第二源汲極區2〇%間僅具有一小於該 導通電流之漏電流時，則讀出值為〇 ; Λ 欲抹除任一電晶體之記憶單元包括下列步驟：選擇一欲抹除之 電as體，於該電晶體之閘極203a上施加一閘極抹除電壓；於該串'聯 通道的其他電晶體之閘極203a上施加一閘極非抹除導通電壓；於該 第一源没極209a施加一第一抹除電壓。 欲寫入至少一電晶體之記憶單元包括卞列步驟：選擇至少一欲 寫入之電晶體，於選擇之電晶體閘極2〇3a上施加一閘極寫入電壓. 於該串聯通道的其他未選擇之電晶體閘極203a上施加一閘極非寫 入強制導通電壓；於該第一源汲極209a施加一第一寫入電壓；於該 第二源汲極209b施加一第二寫入電壓。 第二實施例： 請參考第3a-3i圖’第3a-3i圖係本發明之高密度記憶元件之第 二實施例之製造流程及操作方式示意圖。 請參考第3a'圖’於半導體基底301上依序形成閘極介電層3〇2、 導電層303及第一圖案化光阻層304。其中’半導體基底3〇1例如是 矽基底；閘極介電層302之厚度為20 A至200A，材質例如是氣化層 1326906 或高介電係數材料，氧化層例如是二氧化石夕，高介電係數材料之介電 係數為4至1〇〇，例如是五氧化二紐(Ta2〇5)、氧化銘㈤2〇3)、氧 化錯(Zr02)'氧化給(Hf〇2)、氧化此(Gd203)、氧化紀(Y203)其中 之一；導電層203之厚度大約是800至2500Α，材質例如是多晶矽層。 請參考第3b圖，以第一圖案化光阻層304為罩幕蝕刻導電層 303,使導電層3〇3形成複數個閘極3〇3a’然後去除圖案化光阻層3〇4。 請參考第3c圖接著以第二圖案化光阻層307及閘極303a為罩幕，對 半導體基底301進行摻雜步驟’以在閘極3〇3a側邊之半導體基底3〇1 上形成一源汲極延伸區 308 (source/drain extension)» 請參考第3d圖，將第二圖案化光阻層307移除後，將露出表面 之閘極介電層302去除，而留下閘極3〇3a下方之閘極介電層3〇2a， 於半導體基底301及閘極303a之表面上順應形成一氧化層3〇5a與電 荷捕陷層305b，氧化層305a厚度為20至200A ,材質例如是二氧化 矽；電荷捕陷層305b為高介電係數材料，介電係數為介於3至1〇〇 之間’材料為五氧化二组(Ta2〇5)、氧化鋁(A1203)、氧化錯(Zr02)、 氧化铪(Hf02)、氧化釓(Gd203)、氧化釔(Y203)其中之一。接著， 繼續在電荷捕陷層305b的表面上順應形成一介電層3〇6，介電層3〇6 例如是氧化層’在複數個閘極之間的間距較小或小於兩個介電層3〇6 側壁厚度時，該介電層將充填兩閘極之間隙，如第3e圖所示。 請參考第3f圖’對介電層306進行非等向性蝕刻，以在閘極3〇3a最 外端之側壁形成一間隙壁306a，並露出兩外端閘極的基底，其中， 非專向性姓刻的方法例如是反應性離子钱刻（reactive i〇n etching，j^je) 或電漿姓刻(plasma etching>，。 以閘極303a及間隙壁3〇6a為罩幕，對半導體基底進行離子植入 步驟，以在半導奴基底301形成如第3g圖所示之源汲極區308a及 308b»其中’植入之離子例如是含有砷鱗或硼離子或其中兩者以上 之組合。因為間隙壁3〇6a及在閘極間隙充填之絕緣層有遮蔽的效 12 果’因此在離子植入的步驟中，有些閘極形成半導體基底301上與問 極下方通道的一側會有一源汲極延伸區308 ;而有些閘極下方通道的 另一側並無源汲極延伸區。 . 4參考第3h ® ’將露出表面之氧化層驗去除，然後對閘極 303a，半導體基底3〇1進行自行對準魏步驟，以在閘極施、源 /及極區308a之表面上形成金屬石夕化物，以利後續之源/沒極及閘 極導通之用；其中，金屬石夕化物3〇9例如是二石夕化欽(TiSi2)或二石夕化 鈷(CoSh)或矽化鎳(NiSi)。 • 請參考第3i圖，其中串聯通道上的箭頭39。是指在寫入時的通 道載子流動方向，該圖例說明本發明之後段金屬連線製程，其中先沉 ， 層絕緣物’㈣包含有二氧切、氮氧化物或該兩者之多層組 合’接著’繼續在絕緣層310巾形成-接觸窗(Contact)及金屬插塞 (Me'Plug)311，接著在絕緣層310之上形成第-層金属連線312。 本實把例之操作方式與前述第—實施例姻，如第_卜由上述 内谷可知，利用本發明所提供之高密度記憶元件及製造方法可藉由 間隙壁下之電荷翻層縣記‘·，電晶體與t晶體_距離不會被 • 拉長’可增加記憶趙單位面積下之記憶元件的密度，進而可達到降低 製造成本的目的。 第二貫施例: ' 一明參考第4a~4j圖’第4a-4j圖係本發明之高密度記憶元件之第 程及操作方式示意圖。 .請參考第4a圖’於半導趙基底401上依序形成閘極介電層402、 導電層403及第-圓案化光阻層4〇4。其中，半導體基底4〇1例如是 ;問極介電層舰之厚度為2G A至職，材質例如是氧化層 ^南"電係數材料，氧化層例如是二氧化石夕，高介電係數材料之介電 二為3至1〇〇 ,例如是五氧化二组(Ta2〇5)、氧化链(μ⑽）、氧化 13 錯(Zr02)、氧化給(HfD2)、氧化此(Gd2〇3)、氧化纪⑺⑼其中之 -，導電層403之厚度為_至2500八，材質例如是多晶石夕層。 請參考第4b冑，以第-圖案化光阻層4〇4為罩幕細導電層 403,使導電層403形成複數個閘極她，然後去除圖案化光阻層. «•月參考第4c @ ’將路出表面之間極介電層402去除，而留下閘 極偷下方之閘極介電層4〇2a，於半導趙基底4〇1及間極碰之 表面上順應形成-氧化層觀與電荷捕陷層·，氧化層.厚 度為20至200A，材質例如是二氧化石夕；電荷捕陷層獅為高介電 係數材料，介電係數為介於3至⑽之間，材料為五氧化二組 (Ta205)、氧化鋁(A1203)、氧化錯(Zr〇2)、氧化铪(Ηί〇2)、氧化釓 (Gd2〇3)、氧化釔(Υ203)其中之…接著，繼續在電荷捕陷層働 的表面上順應形成-介電層4〇6，介電層406例如是氧化層，如第4d 圖所示。 請參考第4e圖，對介電層406進行非等向性姓刻，以在閘極· 之側壁形成-_壁406a。其中，非等向舰_方關如是反應 性離子蝕刻（reactive i〇n etching，RiE)或電漿蝕刻⑼紐“此㈣。 以閘極403a及間隙壁406a為罩幕，對半導體基底進行離子植入步 驟，以在半導趙基底401形成如第4f ®所示之源汲極408a及獅。 其中’植人之離子例如是含有_、贼卿子或其巾兩者以上之組合。 請參考第4g圖’將露出表面之氧化層_去除，然後對間極 403a與半導體基底401進行自行對準石夕化步驟，以在閘極4〇3a、源 汲極區408a之表面上形成金屬矽化物4〇9，以利後續之源/汲極及閘 極導通之用；其中’金屬石夕化物409例如是二石夕化鈦(11别2)或二石夕化 鈷(CoSi2)或矽化鎳(NiSi)。 請參考第4h圊，該圖例說明本發明之後段金屬連線製程，其中 先沉積-層絕緣物410，材質包含有二氧化梦、氣氧化物或該兩者之 多層組合；接著’繼續在絕緣層41〇巾形成一接觸窗(c〇ntact)及金屬 1326906 插塞(Meta Plug)411，接著在絕緣層41〇之上形成第一層金屬連線 412 〇 ㈤參考第4i圖’該圖例制本發明之複數個電晶體的通道經由 • 該驗極區相連接轉成—㈣通道，由左至右具有的a個位元，圖 • +藉由寫入間隙壁下方之電荷捕陷層之熱電子，可控制欲寫入 之資料被定義成為“0”或“丨”， 第41圖中串聯通道上的箭頭490是指在寫入時的通道載子流動 方向，欲寫入至少-電晶體之第一記憶單元包括下列步驟：選擇至少 —欲寫人之電晶體；於選擇之電晶體_她上施加寫入電 壓；於該_騎道的其他未選擇之f關閘極上施加__閘極非寫入強 制導通電壓’於該第-源沒極4〇9a施加一第一寫入電壓；於該第二 • 源沒極409b施加一第二寫入電壓。 . 本發明之讀取任一電晶趙之左側第-記憶單元包括下列步驟：選 擇-欲讀取之電晶體；於該電晶體之閘極術上施加—閘極讀取電 壓；於該_聯通道上的其他電晶趙之_施加強制導通電壓； 於該第二源極區409b施加-第-電壓，且於該第一源沒極區碰 接地電壓或施加-較該第-電壓接近零電位之第二電壓；該第一源汲 籲 極區她與該第二源汲極區働間具有導通之通道載子電流時，.即 該左側第-記憶單元之讀出值為i ;該第一源汲極區衡與該第二 源沒極區409b間僅具有-小於該導通電流之漏電流，即該第一記憶 單元之讀出值為0。 " 欲抹除任一電晶體之第一記憶單元包括下列步驟：選擇一欲抹除 之電晶體；於該電晶艘之閘極上施加-閘極抹除電屋；於該串 如通道的其他f：晶體之閉極上施加一閘極非抹除導通電壓；於該第一 源>及極409a施加'一第一抹除電磨。 請參考第4j圊，其中串聯通道上的箭頭491是指在寫入時的通 道載子流動方向，欲寫入至少一電晶體之第二記憶單元更包括下列步 15 1326906 驟：選擇至少一欲寫入之電晶體；於選擇之電晶趙閘極4〇3a上施加 一閘極寫入電壓；於該串聯通道的其他未選擇之電晶體閘極上施加一 閘極非寫入強制導通電壓；於該第一源汲極409a施加一第三電壓； 於該第二源汲極409b施加一第四電壓。 本發明之讀取任一電晶趙之右側第二記憶單元包括下列步驟： 選擇一欲讀取之電晶體；於該電晶體之閘極4〇3a上施加一閘極讀取 電壓；於該串聯通道上的其他電晶體之閘極施加一閘極強制導通電 壓，於該第一源汲極區409a施加一第三電壓，且於該第二源汲極區 4〇9b接地或施加一較該第三電壓接近零電位之第四電壓，該第一源 汲極區409a與該第二源汲極間4〇9b具有導通之通道載子電流時，即 該右側第二記憶單元之讀出值為丨；，該第一源汲極區4〇9a與該第 二源汲極409b間僅具有一小於該導通電流之漏電流時，即該右側第 一》己憶單元之讀出值為〇，因此一個MOS電晶趙可被寫入兩筆資料， 可增加被寫入之資料量；因此，與習知技藝相比較，同樣設計準則範 圍内可被形成的電晶體數目不會減少，但寫入之資料量倍增。 其中欲抹除任一電晶體之第二記憶元件更包括下列步驟：選擇一 欲抹除之電晶體；於該電晶體之閘極4〇3a上施加一閘極抹除電壓； 於該串聯通道的其他電晶體之閘極上施加一閘極非抹除導通電壓;於 該第一源没極409b施加一第二抹除電麼。 第四實施例： 請參考第5a-5j圓’第5a__5j圖係本發明之高密度記憶元件之第 四實施例之製造流程及操作方式示意圖。 請參考第5a圊，於半導趙基底5〇1上依序形成閘極介電層5〇2、導 電層503及第-崮案化光阻層5〇4。其中，半導趙基底5〇1例如是矽 基底；閘極介電層502之厚度為2〇 a至2〇〇A，材質例如是氧化層或 高介電係數材料’氧化層例如是二氧化石夕，高介電係數材料之介電係 16 1326906 數為3至loo，例如是五氧化二艇(Ta2〇5)、氧化紹(ai2〇3)、氧化錯 (Zr02)、氧化铪(HfQ2)、氧化釓(Gd2〇3)、氧化釔（γ2〇3)其中之— 導電層503之厚度為800至2500Α，材質例如是多晶矽層。 叫參考第5b目’以第-圖案化光阻層5G4為罩幕ϋ刻導電層 503,使導電層咖形成複數個閘極5()3a，然後去除圖案化光阻層5〇4。 請參考第5c圖接著以第二圖案化光阻層5〇7及閘極5咖為罩 幕’對+導趙基底501進行摻雜步驟，以在閘極5〇3a側邊之半導體 基底501上形成一源/及極延伸區508 (soufce/^ainextension)。 凊參考第5d圖及5e圖’將第二圖案化光阻層5〇7移除後，將露 出表面之閘極介電層502去除，而留下閘極5〇3a下方之閘極介電層 502a’於半導縣底5()1賴極5()3a之表面上順應形成—氧化層5脱 與電荷捕陷層505b，氧化層505a厚度為20至200A ,材質例如是二 氧化珍；電荷捕陷層5〇5b為高介電係數材料，介電係數為介於4至 1〇〇之間，材料為五氧化二钽(Ta2〇5)、氧化鋁（A12〇3)、氧化锆 (Zr02)、氧化給(Hf〇2)、氧化釓(Gd203)、氧化釔(Y203)其中之一。 接著，繼續在電荷捕陷層505b的表面上順應形成一介電層506，介 電層506例如是氧化層，在複數個閘極之間的間距較小或小於兩個介 電層5G6側壁厚度時’該介電層將充填兩閘極之間隙，如第5d圖所 示。 請參考第5f圖’對介電層506進行非等向性蝕刻，以在閘極503a 最外端之側壁形成一間隙壁5〇6a ’並露出兩外端閘極的基底，其中， 非等向性/钱刻的方法例如是反應性離子姓刻(reactive i〇n，沿丘） 或電装姓刻(plasma etching)。 請參考第5g圖，以閘極5〇3a及間隙壁5〇6a為罩幕，對半導體基 底進行離子植入步驟，以在半導體基底5〇1形成如第5f圖所示之源 /及極區508a及508b。其中，植入之離子例如是含有珅、磷或蝴離子 或其中兩者以上之組合。因為間隙壁5〇6a及在閘極間隙充填之介電 17 1326906 層有遮蔽的效果，因此在離子植入的步驟中，有些閘極形成半導體棊 底501上與閘極下方通道的一側會有一源汲極延伸區5〇8 ;而有些閘 極下方通道的另一側並無源汲極延伸區。 • 請參考第5h圖，將露出表面之氧化層505a去除，然後對半導體 基底501進行自行對準矽化步驟，以在閘極5〇3a、源汲極區508a之 表面上形成金屬矽化物509，以利後續之源/汲極及閘極導通之用； 其中’金屬石夕化物509例如是二石夕化欽(TiSi2)或二矽化結(c〇Si2)或矽 化鎳(NiSi)。 請參考第5i圖及5j圖’其中串聯通道上的箭頭590及591是分 別指在第5i圖及5j圖寫入時的通道載子流動方向，該圖例說明本發 明之後段金屬連線製程，其中先沉積一層絕緣物，材質包含有二氧化 - 矽、氮氧化物或該兩者之多層組合；接著，繼續在絕緣層510中形成 一接觸窗(Contact)及金屬插塞(MetaPlug)5u，接著在絕緣層51〇之 上形成第一層金屬連線512。 本實施例之操作方式與前述第三實施例相同，如第4i圖例及第 4j圖例。由上述内容可知，利用本發明所提供之高密度記憶元件及 製造方法，可藉由間隙壁下之電荷捕陷層做為記憶區，電晶體與電晶 • 體間的距離不會被拉長，可增加記憶體單位面積下之記憶元件的密 度，有效提高單位時間内之資料處理量，進而可達到降低製造成本的 目的。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發 明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作更 動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 為使本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文 18 1326906 特舉四較佳實施例，並配合所附圖式，作詳細說明如下： 第1a~1C圖係顯示習知之NAND型堆疊閘極快閃記憶體之部分製造 流程》 第2a-2j圖係顯示本發明之高密度記憶元件之製造方法之第一實施 例。 、 第3a—3i圖係顯示本發明之高密度記憶元件之製造方法之第二實施 例。 第4a-4j圖係顯示本發明之高密度記憶元件之製造方法之第三實施 例。 第5a-5j圖係顯示本發明之高密度記憶元件之製造方法之第四實施 例a 【主要元件符號說明】 101〜半導體基底； 103a〜浮動閘極； l〇3b〜控制閘極； 108a〜第一源汲極； 108b〜第二源汲極； 201〜半導體基底； 202〜介電層； 203〜導電層； 203a〜閘極； 204~第一圖案化光阻潛； 202a~閘極介電層； 205a〜氧化層；' 205b〜電荷補陷層； 206〜介電層； 1326906 206a〜介電層間隙壁； 207〜第二圖案化光阻層； 208〜源汲極延伸摻雜區； 208a〜源汲極區； 209〜金屬矽化物； 209a~第一源汲極金屬矽化物； 209b〜第二源汲極金屬矽化物； 210〜絕緣層； 211〜接觸窗； 212〜第一金屬導電層； 301〜半導體基底； 302~介電層； 302a〜閘極介電層； 303〜導電層； 303a〜閘極； 304〜第一圖案化光阻層； 305a〜氧化層； 305b~電荷補陷層； 306~介電層； 3063~介電層間隙壁； 307〜第二圖案化光阻層； 308〜源汲極延伸摻雜區； 308a〜第一源汲極區； 308b〜第二源汲極區； 309~金屬矽化物\ 309a~第一源汲極金屬矽化物； 309b〜第二源汲極金屬矽化物； 20 1326906 310〜絕緣層； 311〜接觸窗； 312〜第一金屬導電層； 401〜半導體基底； 402'•介電層； 402a〜閘極介電層； 403〜導電層； 403a〜閘極； 404〜第一圖案化光阻層； 405a~氧化層； 405b〜電荷捕陷層； 406- 介電層； 406a〜介電層間隙壁； 407- 第二圖案化光阻層； 408a〜第一源汲極區； 408b〜第二源汲極區； 409〜金屬矽化物； 409a〜第一源汲極金屬矽化物； 409b〜第二源汲極金屬矽化物； 410〜絕緣層； 411〜接觸窗； 412〜第一金屬導電層； 501〜半導體基底； 502~介電層； 502a〜閘極介電雇； 503〜導電層； 503a〜閘極；1326906 IX. Description of the Invention: [Technical Field] The present invention relates to a memory element, and more particularly to a method and a structure for manufacturing a mask-type read-only memory having a high-density memory element, which can increase processing data. The number of bits increases the amount of data that can be processed by the memory. [Prior Art] Information stored in non-volatile memory can be kept intact even if the power supply data is cut off. According to whether the stored data can be erased, it can be divided into mask-type read-only memory (Mask ROM), including electrical programmable read-only memory (EpR〇M), and electrically erasable stylized read-only memory. Body (EEPR0M), Flash Memory (Flash Memory). Among them, flash memory has been widely used for high-capacity data storage such as memory cards, personal digital assistants (PDAs), flash drives, and MP3 players. Therefore, such applications require high-density and low-cost memory. That is, smaller cell size and lower manufacturing cost. The reverse or gate (NOR) type stacked gate flash memory cell typically has one bit line. a contact, a source region, a floating gate, and a control gate, and the control gate is directly above the floating gate. The relative size of such cells is such that they cannot be used in very high density data storage applications. . A smaller cell size can be obtained in a nand-type stacked gate flash memory cell array having a series connected in series between the bit line and the source line. Please refer to FIG. 1A for a schematic diagram showing a conventional NAND type stacked gate flash memory cell array. When the conventional NAND and NAND type stacked gate flash memory cells are to be written, 'the high voltage electrons are applied to the control closed-end and the bungee wrists from the source of the substrate 101. 8a passes through the series-connected channel and the source-poor region to generate hot electrons and enters the net-moving gate 103a. Therefore, the floating gate is stored with a negative charge, and the threshold voltage rise of the 5'5 flash memory cell is closed. Please refer to Figure lb. Figure lb shows the conventional inverted gate flash memory unit. Wipe off the schematic. When the conventional NAND type stacked gate flash memory is to be erased, a negative voltage or zero voltage is applied to the control gate 1〇31), and the secret of the tree substrate 1〇1 is hidden. When a high voltage is applied, electrons pass from the floating gate 103a through the gate oxide layer back to the drain 1〇8a. The 53⁄4 boundary voltage of the stacked gate flash memory single 因此 is thus reduced. By changing the threshold voltage of the stacked gate flash memory cell, when the data is to be read, if the selected word line is not grounded or zeroed as shown in the figure lc, it can be flashed by the stack gate. The channel is judged to be logical "Γ or logic" 〇" in the on state or the non-conduction state. The NAND (hidden occlusion) 耽 秘 耽 体 体 体 体 浮动 浮动 浮动 浮动 浮动 浮动 浮动 浮动 浮动 浮动 浮动 浮动 浮动 浮动Therefore, the process of the dual unit is relatively complicated so that they cannot be produced by a single gate logic process technology. [Invention] In view of the above, the present invention aims to provide a single gate logic process compatible south density memory. The component, and in the case of a transistor having the same density, can increase the number of bits of the processing (4) and increase the data capacity that can be processed by the network memory. According to the above object, the present invention provides a method for manufacturing a high-density memory element. The method includes the following steps: providing a semi-conducting bottom, wherein the semi-rotating substrate is formed with a closed-electrode dielectric layer, a conductive layer and a first patterned photoresist layer; and the first-patterned photoresist is Mask side The conductive layer is transformed into: - removing the first patterned photoresist; the first patterned photoresist layer has an opening exposing a portion of the gate surface and a semiconductor substrate surface on the side of the gate: (10) The second rounded photoresist layer is a mask, and ion implantation is performed on the bottom surface of the exposed surface of the exposed surface to form a source-polar extension region and a pocket doping freely selectable; The second patterned photoresist layer is subjected to thermal oxidation treatment and depositing a plurality of dielectric layers on the sidewall of the interrogation layer, and the multilayer dielectric layer is formed into a layer of oxide/charge trapping from bottom to top. a composite dielectric spacer of the dielectric layer; the interlayer of the composite dielectric layer of the gate and the gate is used as a mask, and the semiconductor base is ion-distributed to form a source-deposited region on the semiconductor substrate and Forming an oxide layer on the surface; and forming a metal semiconductor compound on the surface between the exposed surface and the source drain region. According to the above object, the present invention further provides a memory device operation method comprising: a semiconductor substrate; a transistor formed in a semiconductor substrate, wherein each of the transistors comprises: a dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a spacer formed on a sidewall of the gate; a switchable channel 'below the gate dielectric layer; a source selective drain extension region formed in the semiconductor substrate and located under the spacer on one side of the gate and the source The pole extension region is opposite to the channel doping electrical property; a freely selected pocket doping is formed in the semiconductor substrate and is located below the source drain extension region, and the mouthpiece holds the source and the source extension region The dopant is opposite in polarity; a depolarization region is formed in the semiconductor substrate and is connected to the outer side of the channel or source drain extension region, and the source drain region and the source drain region are doped with the same electrical conductivity Wherein the gate dielectric layer has a thickness of 20 A. to 200 A' and the bottom of the spacer has a width of 200 A to 2000 A. The plurality of transistors are connected to the source drain region via the channel, the source drain region and the source drain extension region; a first source drain region is formed at one end of the series channel; and a first A two-source drain region is formed at the other end of the series channel. The first memory unit for extracting any of the transistors includes the following steps: selecting a transistor to be read; applying a gate read voltage to the gate of the transistor; and other electro-crystals in the series channel Applying a gate forcing voltage to the gate; applying a first voltage to the second source terminal, and grounding the first source terminal or applying a second voltage that is closer to zero potential than the first voltage The first source 汲 terminal and the second source 汲 terminal have a conduction current, that is, the read value of the first memory material is i; and when the first source and the extreme and the second source 汲 terminal have only — The leakage current of the small _ conduction current, that is, the read value of the first memory unit is zero. The second memory unit of the transistor further comprises the steps of: selecting a transistor to be extracted; applying a gate read voltage to the gate of the transistor; and other gates in the series channel a gate forced-on voltage is applied to the gate of Zhao; a third voltage is applied to the first source 汲 terminal and the second source is grounded or a fourth voltage is applied which is closer to zero f-bit than the third voltage, When the terminal has no source, there is no conduction current between the extremes, that is, the read value of the second memory unit is i; and when the first source and the source have only one less than the second source When the current is leaked, that is, the read value of the second memory unit is 〇^ The first memory unit to erase any transistor includes the following steps: selecting a transistor to be erased; A gate erase voltage is applied to the gate; a gate non-erasing turn-on voltage is applied to the gate of the other transistor connected in series; and a first erase voltage is not applied to the first source. The second memory element #1 to erase any of the transistors further includes the following steps: selecting the erased aa body, and applying a gate erase voltage to the gate of the transistor; the other of the series channels A gate is applied to the gate of the transistor to remove the turn-on voltage; a second eraser is not applied to the first source. Iwriting the first memory unit of the at least one transistor comprises the steps of: selecting at least one transistor to be written; applying a gate write voltage to the selected transistor gate; and not selecting other of the series channels A gate non-write forced turn-on voltage is applied to the gate of the transistor; a first write voltage is applied to the first source drain terminal; and a second write voltage is applied to the second source drain terminal. The second memory unit to be written into the at least one transistor further comprises the steps of: selecting at least one transistor to be written; applying a gate write voltage to the selected transistor gate, and the other of the series channels Applying a gate non-writing on the selected transistor gate forces a third voltage; turning on the voltage at the second source terminal; applying a fourth voltage without applying an extreme. [Embodiment] The first embodiment is a schematic diagram of the manufacturing process and operation mode of the first embodiment of the high-density memory device of the present invention. The gate dielectric layer, the conductive layer 203, and the first patterned photoresist layer 2〇4 are sequentially formed on the semiconductor substrate 2〇1. It is a butterfly; 嶋胄 please increase (10) A i ===; 疋 emulsified layer or 〒 dielectric coefficient material, the oxide layer is, for example, dioxotomy, the high dielectric constant material has a dielectric constant of 4 to 100 ′, for example, five Oxidation two groups (Ta2〇5), Oxidation (A1203), Zirconia (Zr02), Oxidation to _2), Oxidation gamma (9) Oxidation (Y203); The thickness of the conductive layer 2〇3 is approximately _ To 25 〇〇A, the material is, for example, a polycrystalline layer. Referring to the 2b ® ' with the first patterned photoresist layer 2 〇 4 as the mask etched conductive layer 203 ', the conductive layer 203 is formed into a plurality of gates 2 〇 3a, and then the photoresist layer 204 is removed. Referring to FIG. 2c, the second patterned photoresist layer 207 and the gate 2〇3a are used as a mask to perform a doping step on the semiconductor substrate 201 to form on the semiconductor substrate 201 on the side of the gate 2〇3a. Source/drain extension 208 (source/drain extension). Referring to FIG. 2d, after removing the second rounded photoresist layer 207, the exposed gate dielectric layer 202 is removed. a gate dielectric layer 2〇2a under the pole 203a, and an oxide layer 2〇5a and a charge trapping layer 205b' oxide layer 205a are formed on the surface of the semiconductor substrate 1 and the gate 203a to have a thickness of 20 to 200A, the material is, for example, cerium oxide; the charge trapping layer 205b is a high dielectric constant material, the dielectric constant is between 3 and 100, and the material is bismuth pentoxide (Ta205), aluminum oxide (Ai2 〇 3) Niobium oxide (ZrCL) is oxidized to one of (Hf02), yttrium oxide (Gd2〇3), and oxidation|B (γ2〇3). Next, a dielectric layer 2〇6 is formed on the surface of the charge trapping layer 2〇5b, and the dielectric layer 206 is, for example, an oxide layer, as shown in FIG. 2e. Referring to Figure 2f, the dielectric layer 206 is anisotropically patterned to form a spacer on the sidewall of the gate 203a. Among them, the method of anisotropic surname is, for example, reactive ion etching (WE) or piasma etching. The semiconductor substrate is subjected to an ion implantation step using the gate electrode 203a and the spacer 206a as a mask to form a source drain 2 as shown in Fig. 2g on the semiconductor substrate 2?. The implanted ions are, for example, arsenic, phosphorus or boron ions or a combination of two or more thereof. Because the spacer 206a has a shielding effect, in the step of ion implantation, there is a source-polar extension region 208 between the source drain on the semiconductor substrate 2〇1 on the gate formation side and the channel under the gate; There is a passive drain extension between the gate under the gate on the other side and the source drain 208a on the semiconductor substrate 2〇1. Referring to FIG. 2h, the oxide layer 2〇5a of the exposed surface is removed, and then the gate 203a and the semiconductor substrate 201 are self-aligned to form a surface on the surface of the gate 2〇3a' source and the non-polar region 208a. The metal cerium 209 is used for the subsequent source immersion and gate conduction; wherein the metal bismuth 209 is, for example, titanium dihalide (TiSi2) or bismuth (CoSi) or NiSi. Please refer to FIG. 2i'. This illustration illustrates the metal wiring process of the subsequent stage of the present invention, in which a layer of insulating material is first deposited, the material comprising cerium oxide, oxynitride or a combination of the two; and then continuing in the insulating layer 210 A contact and a metal plug 211 are formed in the middle, and then a first metal wiring 212 is formed on the insulating layer 210. 'Please refer to FIG. 2j'. This illustration illustrates that the channels of the plurality of transistors of the present invention are connected via the source drain region or the source drain region to form a series channel, four bits from left to right. In the figure, by writing the thermal electrons of the trapping layer of the lion under the spacer, the data that can control the heart writing is defined as "1", and the arrow on the serial channel in the 2j figure refers to the application of reading. The channel carrier flow direction in the partial housing's reading the memory unit of the any-crystal includes the following steps: selecting a transistor to be read; applying a gate reading voltage on the 2G3a of the transistor; The other electric (4) on the series channel applies a turn-on voltage; applying a drain-drain in the first source region and applying a ground voltage to the second source and region 209b; the first source When the bungee zone hall and the second source oligo zone lion have a conduction channel carrier current, the read value of the left bit memory element is 1; the first source drain region 209a and the second source When there is only one leakage current less than the on-current between the 2%% of the drain region, the value is read.记忆 记忆 记忆 抹 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲A gate non-erasing turn-on voltage is applied to the gate 203a of the other transistor; a first erase voltage is applied to the first source drain 209a. The memory cell to be written into the at least one transistor includes a step of selecting at least one transistor to be written, applying a gate write voltage to the selected transistor gate 2〇3a. Others in the series channel A gate non-write forced turn-on voltage is applied to the unselected transistor gate 203a; a first write voltage is applied to the first source drain 209a; and a second write is applied to the second source drain 209b. Voltage. Second Embodiment: Referring to Figures 3a-3i, Figures 3a-3i are schematic views showing the manufacturing flow and operation of the second embodiment of the high-density memory device of the present invention. Referring to FIG. 3a', a gate dielectric layer 3'2, a conductive layer 303, and a first patterned photoresist layer 304 are sequentially formed on the semiconductor substrate 301. Wherein the semiconductor substrate 3〇1 is, for example, a germanium substrate; the gate dielectric layer 302 has a thickness of 20 A to 200 A, and the material is, for example, a gasification layer 1326906 or a high dielectric constant material, and the oxide layer is, for example, a dioxide dioxide, high. The dielectric constant material has a dielectric constant of 4 to 1 〇〇, for example, bismuth oxide (Ta2 〇 5), oxidized (5) 2 〇 3), oxidized (Zr02) oxidized (Hf 〇 2), oxidized (Gd203), one of the oxidation groups (Y203); the thickness of the conductive layer 203 is about 800 to 2500 Å, and the material is, for example, a polycrystalline germanium layer. Referring to FIG. 3b, the conductive layer 303 is etched by using the first patterned photoresist layer 304 as a mask, and the conductive layer 3〇3 is formed into a plurality of gates 3〇3a' and then the patterned photoresist layer 3〇4 is removed. Referring to FIG. 3c, the second patterned photoresist layer 307 and the gate 303a are used as a mask, and the semiconductor substrate 301 is doped to form a semiconductor substrate 3〇1 on the side of the gate 3〇3a. Source/drain extension 308 (source/drain extension). Referring to FIG. 3d, after removing the second patterned photoresist layer 307, the gate dielectric layer 302 of the exposed surface is removed, leaving the gate 3 The gate dielectric layer 3〇2a under the 〇3a is formed on the surface of the semiconductor substrate 301 and the gate 303a to form an oxide layer 3〇5a and a charge trapping layer 305b. The oxide layer 305a has a thickness of 20 to 200 Å. Is cerium oxide; the charge trapping layer 305b is a high-k material, and the dielectric constant is between 3 and 1 ' 'material is pentoxide group (Ta2〇5), aluminum oxide (A1203), oxidation One of the wrong (Zr02), yttrium oxide (Hf02), yttrium oxide (Gd203), and yttrium oxide (Y203). Then, a dielectric layer 3〇6 is formed on the surface of the charge trapping layer 305b, and the dielectric layer 3〇6 is, for example, an oxide layer. The spacing between the plurality of gates is smaller or smaller than two dielectrics. When the thickness of the sidewalls of the layer 3〇6, the dielectric layer will fill the gap between the two gates as shown in Fig. 3e. Please refer to FIG. 3f' for anisotropic etching of the dielectric layer 306 to form a spacer 306a on the sidewall of the outermost end of the gate 3〇3a, and expose the substrate of the two outer gates, wherein The method of engraving the sexual surname is, for example, reactive ion etching (j^je) or plasma etching (plasma etching), with the gate 303a and the spacer 3〇6a as a mask, The semiconductor substrate is subjected to an ion implantation step to form source bungee regions 308a and 308b as shown in FIG. 3g in the semiconductor substrate 301, wherein the implanted ions are, for example, containing arsenic scale or boron ions or more. The combination is because the spacers 3〇6a and the insulating layer filled in the gate gap have the effect of shielding. Therefore, in the step of ion implantation, some of the gates form the side of the semiconductor substrate 301 and the channel below the gate. There will be a source drain extension 308; and some of the gates below the other side of the gate and a passive drain extension. 4 Reference 3h ® 'will remove the oxide layer of the exposed surface, then the gate 303a, semiconductor The substrate 3〇1 is self-aligned with the Wei step to apply at the gate. And a metal lithium compound is formed on the surface of the polar region 308a to facilitate subsequent source/depolarization and gate conduction; wherein the metal lithium compound 3〇9 is, for example, a two-stone Xihuaqin (TiSi2) or two Cobalt (CoSh) or nickel (NiSi). • Refer to Figure 3i, where the arrow 39 on the serial channel refers to the flow direction of the channel carrier at the time of writing. This illustration illustrates the metal behind the invention. Wiring process, in which the first layer, the layer insulator '(4) contains dioxo prior, oxynitride or a combination of the two 'then' continues to form in the insulating layer 310 - contact and metal plug ( Me'Plug) 311, and then forming a first-layer metal wiring 312 over the insulating layer 310. The operation mode of the present embodiment is in accordance with the foregoing first embodiment, as described in the above-mentioned inner valley, using the present invention The high-density memory element and the manufacturing method provided by the memory layer can be increased by the charge under the gap wall, and the distance between the transistor and the t-crystal can not be increased. Density, in turn, can achieve the goal of reducing manufacturing costs. : 'I bright reference to the 4a~4j diagram' 4a-4j diagram is a schematic diagram of the first process and operation mode of the high-density memory element of the present invention. Please refer to the figure 4a' to sequentially form a gate on the semi-guided Zhao substrate 401 The dielectric layer 402, the conductive layer 403 and the first-circularized photoresist layer 4〇4, wherein the semiconductor substrate 4〇1 is, for example, the thickness of the dielectric layer is 2G A, and the material is, for example, oxidized. Layer ^ South " electric coefficient material, the oxide layer is, for example, a dioxide dioxide, and the dielectric material of the high dielectric constant material is 3 to 1 〇〇, for example, a pentoxide group (Ta2 〇 5), an oxidized chain (μ (10) ), oxidized 13 (Zr02), oxidized (HfD2), oxidized (Gd2〇3), oxidized (7) (9), wherein the conductive layer 403 has a thickness of _ to 2,500, and the material is, for example, a polycrystalline layer. Referring to FIG. 4b, the first patterned photoresist layer 4〇4 is used as the mask fine conductive layer 403, the conductive layer 403 is formed into a plurality of gates, and then the patterned photoresist layer is removed. «•月参考第4c @ 'Removal of the dielectric layer 402 between the exit surfaces, leaving the gate dielectric layer 4〇2a under the gate, conforming to the surface of the semi-conducting Zhao 4〇1 and the inter-pole touch- Oxide layer and charge trap layer ·, oxide layer. Thickness is 20 to 200A, the material is, for example, silica dioxide; charge trap layer lion is high dielectric constant material, dielectric constant is between 3 and (10) The material is a group of pentoxide (Ta205), alumina (A1203), oxidized (Zr〇2), cerium oxide (Ηί〇2), cerium oxide (Gd2〇3), cerium oxide (Υ203), etc. Continuing to form a dielectric layer 4〇6 on the surface of the charge trap layer germanium, the dielectric layer 406 is, for example, an oxide layer, as shown in Fig. 4d. Referring to FIG. 4e, the dielectric layer 406 is anisotropically patterned to form a --wall 406a on the sidewall of the gate. Among them, the non-isotropic ship _ Fang Guan is reactive ion etching (RiE) or plasma etching (9) New "this (4). With the gate 403a and the spacer 406a as a mask, the semiconductor substrate is ionized The implantation step is to form a source bungee 408a and a lion as shown in 4f® on the semi-conductive base 401. The 'planted ion' is, for example, a combination of _, thief, or a towel thereof. Referring to FIG. 4g, the oxide layer of the exposed surface is removed, and then the interpole 403a and the semiconductor substrate 401 are self-aligned to form a metal on the surface of the gate 4〇3a and the source drain region 408a. Telluride 4〇9 for the subsequent source/drain and gate conduction; wherein 'metal lithium 409 is, for example, bismuth titanium (11 other 2) or bismuth cobalt (CoSi2) or Nickel telluride (NiSi). Please refer to the 4th 圊, which illustrates the metal wiring process of the subsequent stage of the present invention, in which a layer-layer insulator 410 is first deposited, and the material comprises a dioxide dioxide, a gas oxide or a combination of the two. Then, 'continue to form a contact window (c〇ntact) and metal 132 in the insulating layer 41 6906 Meta Plug 411, and then forming a first metal wiring 412 on the insulating layer 41A. (5) Referring to FIG. 4i', the channel of the plurality of transistors of the present invention is made through the pattern. The phase connection is converted into a (four) channel, a bit from left to right, and the data to be written is defined as "0" by writing the hot electrons of the charge trapping layer below the spacer. Or "丨", the arrow 490 on the series channel in Fig. 41 refers to the flow direction of the channel carrier at the time of writing, and the first memory unit to be written to at least the transistor includes the following steps: selecting at least - writing a human crystal; a write voltage is applied to the selected transistor _; a __gate non-write forced turn-on voltage is applied to the other unselected gates of the _way, and the first source is not A first write voltage is applied to the pole 4〇9a; a second write voltage is applied to the second source drain 409b. The left first memory unit of the present invention for reading any of the electro-crystals includes the following steps: Select - the transistor to be read; apply on the gate of the transistor - gate read a voltage is applied to the other electro-optical cells on the _-channel; a forced-on voltage is applied to the second source region 409b, and a ground voltage is applied to the first source region and the ground voltage is applied a second voltage of the first voltage adjacent to the zero potential; the first source 汲 极 区 她 与 与 与 与 与 与 与 与 左侧 左侧 左侧 左侧 左侧 左侧 左侧 左侧 左侧 左侧 左侧The value is i; the first source drain region balance and the second source gate region 409b have only - less than the leakage current of the on current, that is, the read value of the first memory unit is 0. " The first memory unit of any one of the transistors includes the following steps: selecting a transistor to be erased; applying a gate on the gate of the transistor to erase the house; and the other f: crystals in the string Applying a gate non-erasing on-voltage on the closed-pole; applying a first eraser to the first source > 409a. Please refer to the 4th page, wherein the arrow 491 on the serial channel refers to the flow direction of the channel carrier at the time of writing, and the second memory unit to be written into at least one transistor further includes the following steps: 15 1326906: Select at least one desire Writing a transistor; applying a gate write voltage to the selected gate transistor 4〇3a; applying a gate non-write forced turn-on voltage to other unselected transistor gates of the series channel; Applying a third voltage to the first source drain 409a; applying a fourth voltage to the second source drain 409b. The second memory unit of the right side of the present invention includes the following steps: selecting a transistor to be read; applying a gate read voltage to the gate 4〇3a of the transistor; The gate of the other transistor on the series channel applies a gate forced turn-on voltage, applies a third voltage to the first source drain region 409a, and grounds or applies a comparison to the second source drain region 4〇9b. The third voltage is close to the fourth voltage of the zero potential, and the channel source current of the first source drain region 409a and the second source drain region 4〇9b is turned on, that is, the readout of the second memory unit on the right side The value is 丨; when the first source drain region 4〇9a and the second source drain 409b have a leakage current smaller than the on current, that is, the read value of the right first memory unit is 〇, therefore, a MOS enamel can be written into two pieces of data, which can increase the amount of data to be written; therefore, compared with the prior art, the number of transistors that can be formed within the same design criteria is not reduced. However, the amount of data written has doubled. The second memory element for erasing any of the transistors further comprises the steps of: selecting a transistor to be erased; applying a gate erase voltage to the gate 4〇3a of the transistor; A gate non-erasing turn-on voltage is applied to the gate of the other transistor; a second erase is applied to the first source gate 409b. Fourth Embodiment: Please refer to the fifth embodiment of the fifth embodiment of the high-density memory device of the present invention with reference to the fifth section 5a__5j. Referring to FIG. 5a, a gate dielectric layer 5〇2, a conductive layer 503, and a first-deposited photoresist layer 5〇4 are sequentially formed on the semiconductor substrate 5〇1. Wherein, the semi-conductive substrate 5〇1 is, for example, a germanium substrate; the gate dielectric layer 502 has a thickness of 2〇a to 2〇〇A, and the material is, for example, an oxide layer or a high-k material “oxidation layer such as dioxide. Shi Xi, the dielectric system of high dielectric constant material 16 1326906 number is 3 to loo, for example, two boats (Ta2〇5), oxidized (ai2〇3), oxidized (Zr02), yttrium oxide (HfQ2) ), yttrium oxide (Gd2〇3), yttrium oxide (γ2〇3), wherein the conductive layer 503 has a thickness of 800 to 2500 Å, and the material is, for example, a polycrystalline germanium layer. Referring to FIG. 5b, the conductive layer 503 is etched with the first patterned photoresist layer 5G4 as a mask, and the conductive layer is formed into a plurality of gates 5() 3a, and then the patterned photoresist layer 5〇4 is removed. Referring to FIG. 5c, the second patterned photoresist layer 5〇7 and the gate 5 are used as a mask to perform a doping step on the +guide substrate 501 to the semiconductor substrate 501 on the side of the gate 5〇3a. A source/and-pole extension 508 (soufce/^ainextension) is formed thereon. Referring to FIGS. 5d and 5e, after removing the second patterned photoresist layer 5〇7, the exposed gate dielectric layer 502 is removed, leaving the gate dielectric under the gate 5〇3a. The layer 502a' conforms to the formation of the oxide layer 5 and the charge trapping layer 505b on the surface of the bottom 5 () 1 Lai 5 () 3a of the semi-conducting county. The oxide layer 505a has a thickness of 20 to 200 A, and the material is, for example, arsenic. The charge trapping layer 5〇5b is a high dielectric constant material with a dielectric constant between 4 and 1 ,, and the material is tantalum pentoxide (Ta2〇5), aluminum oxide (A12〇3), and oxidation. One of zirconium (ZrO2), oxidized (Hf〇2), cerium oxide (Gd203), and cerium oxide (Y203). Then, a dielectric layer 506 is formed on the surface of the charge trapping layer 505b. The dielectric layer 506 is, for example, an oxide layer. The spacing between the plurality of gates is smaller or smaller than the thickness of the sidewalls of the two dielectric layers 5G6. When the dielectric layer will fill the gap between the two gates, as shown in Figure 5d. Referring to FIG. 5f, the dielectric layer 506 is anisotropically etched to form a spacer 5〇6a′ on the sidewall of the outermost end of the gate 503a and expose the substrate of the two outer gates. The method of directional/money engraving is, for example, reactive ion 姓 (reactive i〇n, along the mound) or plasma etching. Referring to FIG. 5g, the semiconductor substrate is subjected to an ion implantation step using the gate 5〇3a and the spacer 5〇6a as a mask to form a source/pole as shown in FIG. 5f on the semiconductor substrate 5〇1. Areas 508a and 508b. The implanted ions are, for example, containing ruthenium, phosphorus or a butterfly ion or a combination of two or more thereof. Because the spacer 5〇6a and the dielectric 17 1326906 layer filled in the gate gap have a shielding effect, in the step of ion implantation, some gates form a side of the semiconductor substrate 501 and the channel below the gate. There is a source drain extension 5〇8; and some gates have the other side of the channel and a passive drain extension. • Referring to FIG. 5h, the oxide layer 505a of the exposed surface is removed, and then the semiconductor substrate 501 is self-aligned and deuterated to form a metal germanide 509 on the surface of the gate 5〇3a and the source drain region 508a. For the subsequent source/drainage and gate conduction; wherein the 'metal lithium 509 is, for example, TiSi2 or bismuth (c〇Si2) or nickel hydride (NiSi). Please refer to FIG. 5i and FIG. 5j' where the arrows 590 and 591 on the series channel refer to the flow direction of the channel carrier when the 5i and 5j images are written respectively, and the illustration illustrates the metal wiring process in the subsequent stage of the present invention. Firstly, a layer of insulator is deposited, and the material comprises cerium oxide, cerium oxide or a combination of the two; then, a contact and a metal plug (MetaPlug) 5u are continuously formed in the insulating layer 510. A first layer of metal wiring 512 is then formed over the insulating layer 51A. The operation mode of this embodiment is the same as that of the third embodiment described above, such as the 4ith diagram and the 4thth diagram. It can be seen from the above that with the high-density memory element and the manufacturing method provided by the present invention, the charge trapping layer under the spacer can be used as the memory area, and the distance between the transistor and the electro-crystal body is not elongated. The density of the memory element under the unit area of the memory can be increased, and the data processing amount per unit time can be effectively improved, thereby achieving the purpose of reducing the manufacturing cost. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following description of the preferred embodiments of the present invention 1a~1C shows a part of the manufacturing process of the conventional NAND type stacked gate flash memory. The 2a-2j figure shows the first embodiment of the manufacturing method of the high density memory element of the present invention. Fig. 3a-3i shows a second embodiment of the method of manufacturing the high density memory element of the present invention. Fig. 4a-4j shows a third embodiment of the method of manufacturing the high density memory element of the present invention. 5A-5j are diagrams showing a fourth embodiment of the manufacturing method of the high-density memory element of the present invention. A. [Main element symbol description] 101~semiconductor substrate; 103a~ floating gate; l〇3b~ control gate; 108a~ First source drain; 108b~ second source drain; 201~ semiconductor substrate; 202~ dielectric layer; 203~ conductive layer; 203a~ gate; 204~ first patterned photoresist potential; 202a~ gate dielectric Electrical layer; 205a~ oxide layer; '205b~ charge trapping layer; 206~ dielectric layer; 1326906 206a~ dielectric layer spacer; 207~ second patterned photoresist layer; 208~ source drain extension doping region 208a~ source drain region; 209~ metal germanide; 209a~ first source drain metal halide; 209b~ second source drain metal halide; 210~ insulating layer; 211~ contact window; Metal conductive layer; 301~semiconductor substrate; 302~dielectric layer; 302a~gate dielectric layer; 303~conductive layer; 303a~gate; 304~first patterned photoresist layer; 305a~oxide layer; 305b~ Charge compensation layer; 306~ dielectric layer; 3063~ dielectric layer spacer; 307~ second patterned light 308~ source drain extension doped region; 308a~first source drain region; 308b~second source drain region; 309~metal germanide\309a~first source drain metal halide; 309b~ Two-source drain metal halide; 20 1326906 310~insulating layer; 311~contact window; 312~first metal conductive layer; 401~semiconductor substrate; 402'•dielectric layer; 402a~gate dielectric layer; Conductive layer; 403a~gate; 404~first patterned photoresist layer; 405a~oxide layer; 405b~ charge trapping layer; 406-dielectric layer; 406a~dielectric layer spacer; 407-second patterning Photoresist layer; 408a~first source drain region; 408b~second source drain region; 409~metal germanide; 409a~first source drain metal telluride; 409b~second source drain metal telluride; 410~insulating layer; 411~contact window; 412~first metal conductive layer; 501~semiconductor substrate; 502~dielectric layer; 502a~gate dielectric employee; 503~conductive layer; 503a~gate;