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九、發明說明 【發明所屬之技術領域】 本發明係關於振盪器（Oscillator)的技術領域，尤指— 種具有自校準功能的高精度振盪器。 【先前技術】IX. Description of the Invention [Technical Field] The present invention relates to the technical field of an oscillator, and more particularly to a high-precision oscillator having a self-calibration function. [Prior Art]
10 15 習知的振盪電路係在封裝振盪器的積體電路外，以夕卜 加的電阻及電容來調整振盪電路的振盪頻率。利用外加的 電阻及電容的方式，雖然可以獲得較佳準確度的振盛頻 率’但由外加的電阻及電容會增加積體電路封裝的腳位 (PAD)、振盪電路的面積、及電阻及電容成本，而使得整個 振盪電路的成本大為提高。 為解決外加電阻及電容所產生成本提高的問題，另一 種習知技術係將電阻及電容與振盪器實作（implement)在同 一個晶片（die)内。然而此種方法將受到半導體製程的影 響’同-晶圓(wafer)上不同地方的晶片(die)會産生不同的 =盪=’並且《頻轉易隨溫度變化，造成振盈器裝 =困因此可知，習知振堡器裝置及振鳩置 丰方法仍存有諸多之缺失而有予以改進之必要。 【發明内容】 度振：明係3供一種具有自校準功能的高精 解決同一曰曰圓上不同地方的晶片會産生不同 20 1326524 ^ 俨州？日修正免^] ='二頻率的問題，並且可避免振盛頻ίΤϊϊϋΐ化 本發明之另一目的係在提供—種具有自校準功能的高 精度振盪器，俾以有效提高振盪器之精確度。 5 料本發明之—特色’本發明係提出-種具有自校準 功能的高精度振盈器，其具有一校準模式及一工作模式。 該高精度振i器包括一頻率镇測裝置、一邏輯控制裝置、 • 一第—資料匯流排、一第一切換器及一數位控制振盪裝 置該頻率偵測裝置之第一輸入端接收一頻率參考訊號， 10其第二輸入端接收一㉟頻訊I，該冑率偵測裝i比較該頻 率參考頻率訊號及該除頻訊號之頻率，用以產生一指示訊 號，其中，該指示訊號具有一第一狀態及一第二狀態；該 邏輯控制裝置具有N位元之輸出埠，並連接至該頻率偵測裝 置，邊邏輯控制裝置依據該指示訊號以設定該輸出埠之一 15位元值，該第一資料匯流排輕接於該N位元輸出埠；該第一 切換器耦接於一第一資料匯流排，用以對該第一資料匯流 > 排訊號進行傳輸或阻隔；該數位控制振盪裝置耦接於該第 一切換器，經由該第一切換器及該第一資料匯流排而耦接 於該N位元輸出埠，該數位控制振盪裝置依據該N位元之輸 20 出埠之值，以產生一時序訊號；其中，當該高精度振盪器 處於校準模式時，該第一切換器為開啟狀態，用以傳輸該 第一資料匯流排訊號，該數位控制振盪裝置依據該N位元之 輸出埠之值’以產生該時序訊號，該頻率偵測裝置比較該 頻率參考頻率訊號及該除頻訊號之頻率，以產生該指示訊 1326524 ；· /, 货·邱7日替換頁 號’該邏輯控制裝置依序依據該指示訊號以分別設定該輸 出埠之第（N-1 )位元至第〇位元之值。 【實施方式】 5 圖1係本發明之具有自校準功能的高精度振盪器的方10 15 The conventional oscillation circuit is used to adjust the oscillation frequency of the oscillation circuit in addition to the integrated circuit of the package oscillator. With the addition of resistors and capacitors, although the vibration frequency of better accuracy can be obtained, the added resistors and capacitors increase the pin position (PAD) of the integrated circuit package, the area of the oscillating circuit, and the resistance and capacitance. The cost makes the cost of the entire oscillating circuit greatly increased. In order to solve the problem of increased cost of applying resistors and capacitors, another conventional technique is to implement resistors and capacitors in the same die as the oscillator. However, this method will be affected by the semiconductor process. 'Different places on the wafer will produce different sag =' and the frequency will change with temperature, causing the vibration device to be trapped. Therefore, it can be seen that there are still many shortcomings in the conventional vibration device and the vibrating method, and it is necessary to improve it. [Summary of the Invention] Vibration: Ming 3 for a high-precision function with self-calibration to solve the difference in the same circle on the wafer will produce a different 20 1326524 ^ Cangzhou? The Japanese correction eliminates the problem of ^] = 'two frequencies, and can avoid the vibration frequency. Another object of the present invention is to provide a high-precision oscillator with self-calibration function to effectively improve the accuracy of the oscillator. . 5 - The present invention is characterized by a high-precision vibrator having a self-calibration function having a calibration mode and an operation mode. The high-precision oscillator includes a frequency measuring device, a logic control device, a first data bus, a first switch, and a digital control oscillator. The first input of the frequency detecting device receives a frequency. The reference signal 10, the second input terminal receives a 35 frequency I, the frequency detection device i compares the frequency reference frequency signal and the frequency of the frequency-divided signal to generate an indication signal, wherein the indication signal has a first state and a second state; the logic control device has an N-bit output port and is connected to the frequency detecting device, and the logic control device sets the 15-bit value of the output port according to the indication signal The first data bus is connected to the N-bit output port; the first switch is coupled to a first data bus for transmitting or blocking the first data stream > The digitally controlled oscillating device is coupled to the first switch, and is coupled to the N-bit output port via the first switch and the first data bus, and the digitally controlled oscillating device transmits 20 according to the N-bit Out a value to generate a timing signal; wherein, when the high-precision oscillator is in the calibration mode, the first switch is in an on state for transmitting the first data bus signal, and the digital control oscillator is based on the N bit The value of the output of the element is 'to generate the timing signal, the frequency detecting means compares the frequency reference frequency signal and the frequency of the frequency-divided signal to generate the indication 1326524; ·,, goods, Qiu 7th replacement page number The logic control device sequentially sets the value of the (N-1)th to the third bit of the output port according to the indication signal. [Embodiment] FIG. 1 is a diagram of a high-precision oscillator with self-calibration function of the present invention.
塊圖’其中，該南精度振盈器具有一校準模式及一工作模 式’該校準模式係用以校準該振蓋器之輸出訊號CLKOUT Φ 的頻率。該振盪器包括一頻率偵測裝置110、一邏輯控制裝 置115、一第一資料匯流排12〇、一第一切換器125、一數^ 10控制振盪裝置130、一除頻裝置135、一第二切換器165、一 舌己憶體裝置145、一第二資料匯流排15〇、一第三切換器 140、一第四切換器16〇、及一工作模式選擇裝置η。。 «亥頻率偵測裝置11 〇之第一輸入端丨丨丨接收一頻率參考 Λ號REF_CLK，其第二輸入端112接收一除頻訊號仙―心。 15該頻率偵測裝置11G比較該頻率參考訊號REF_CLK的頻率 及該除頻訊號clk 一 dlv之頻率，以產生一指示訊號 Indicator ’其中，該指示訊號Indicat〇r具有一第一狀態（〇) 及一第二狀態（1) ’該第一狀態（〇)用以指示該除頻訊號 elk一div之頻率小於該頻率參考訊號REF 一 clk的頻率，該第 20二狀態（1)用以指*該除頻訊號clk_div之頻率沒有小於該頻 率參考訊號REF_CLK的頻率。 該邏輯控制裝置115具有N位元之輸出埠1151以輸出N 位元控制字組，並連接至該頻率偵測裝置110。該邏輯控制 裝置丨15依據該指示訊號Indicator以設定該輸出埠n5i之一 1326524The block diagram 'where the south precision vibrator has a calibration mode and a mode of operation' is used to calibrate the frequency of the output signal CLKOUT Φ of the capper. The oscillator includes a frequency detecting device 110, a logic control device 115, a first data bus 12, a first switch 125, a digital control oscillator 130, a frequency dividing device 135, and a first The second switch 165, the tongue and the body device 145, a second data bus 15 〇, a third switch 140, a fourth switch 16A, and an operating mode selection device η. . The first input terminal of the "Hui frequency detecting device 11" receives a frequency reference signal REF_CLK, and the second input terminal 112 receives a frequency-dividing signal. The frequency detecting device 11G compares the frequency of the frequency reference signal REF_CLK and the frequency of the frequency dividing signal clk_dlv to generate an indication signal Indicator, wherein the indication signal Indicat〇r has a first state (〇) and a second state (1) 'the first state (〇) is used to indicate that the frequency of the frequency-divided signal elk-div is less than the frequency of the frequency reference signal REF-clk, and the 20th state (1) is used to refer to * The frequency of the frequency division signal clk_div is not less than the frequency of the frequency reference signal REF_CLK. The logic control device 115 has an N-bit output 埠 1151 to output an N-bit control block and is coupled to the frequency detecting device 110. The logic control device 依据15 sets the output 埠n5i according to the indication signal Indicator 1326524
' 9%cpnJ 位元值。當該指示訊號Indicator為第一狀態（〇)時，表示該 除頻訊號elk 一 div之頻率小於該頻率參考訊號rEF_CLk的頻 率，而設定該N位元控制字組之第丨位元為〇。當該指示訊號 Indicator為第二狀態（丨）時，表示該除頻訊號clk_div之頻率 5 沒有小於該頻率參考訊號REF_CLK的頻率時，設定該N位 元控制子組之第i位元為i。其中，丨為〇〜(N1)的整數。 當該高精度振盪器處於校準模式時，該邏輯控制裝置 g 115輸出一低電位（0)2Ready訊號◊當該高精度振盪器處於 工作模式式時’該邏輯控制裝置U5輸出一為電位（1)之 10 Ready訊號。 該第一資料匯流排120耦接於該n位元輸出埠1151，用 以傳輸第一資料匯流排訊號至該數位控制振盪裝置丨3〇或 記憶體裝置145。 該第一切換器125耦接於該第一資料匯流排12〇,用以 15將該第一資料匯流排120至該該數位控制振盪裝置130的訊 號進行傳輸或阻隔。 I 該數位控制振盪裝置130耦接於該第一切換器125，經 由該第一切換器125及該第一資料匯流排12〇而耦接於該N 位元輸出埠1151。該數位控制振盪裝置13〇依據該N位元之 20控制字組之值，以產生一時序訊號clock。 泫除頻裝置135耦接於該數位控制振盪裝置13〇，以將 該時序訊號clock除頻，俾產生該除頻訊號ci、div。 當該尚精度振盪器處於校準模式時，該第一切換器125 為開啟狀態’用以傳輸該第—資料匯流排12〇訊號。該數位 1326524 .--- — 控制振盪裝置130依據該N位元控制字組之值，以產生該時 序訊號clock。該頻率偵測裝置11〇比較該頻率參考訊號 REF—CLK及該除頻訊號clk_div之頻率以產生該指示訊號 Indicator，該邏輯控制裝置115依據該指示訊號indicator而 5 分別設定該控制字組之第（N-1)位元至第0位元之值。 當該高精度振盪器處於工作模式時，該第一切換器125 為關閉狀態’用以阻隔該第一資料匯流排120訊號傳輸至該 數位控制振盪裝置130。 ® 該第一切換器165耦接於該第一資料匯流排12〇，用以 10 傳輸或阻隔該第一資料匯流排120之訊號至該記憶體裝置 145 ’該記憶體裝置145耦接於該第二切換器165。 當該咼精度振盈器處於校準模式時’該第二切換器165 為開啟狀態，依序將該控制字組之第（N-ι )位元至第〇位 元之值分別寫入該記憶體裝置145中。當該高精度振盪器處 15 於工作模式時，該第二切換器165為關閉狀態，以阻隔該第 一資料匯流排120訊號寫入該記憶體裝置145中。 ® 該第二資料匯流排丨5〇耦接於該數位控制振盪裝置13〇 及戎έ己憶體裝置145之間。該第三切換器14〇耦接於該記憶 體裝置145，用以傳輸或阻隔該記憶體裝置145之輸出訊號 20 至該數位控制振盪裝置13〇。 當該高精度振盪器處於校準模式時，該第三切換器14〇 為關閉狀態，以阻隔該記憶體裝置145之輸出訊號經由第二 貢料匯流排150而傳送至該數位控制振盪裝置13〇。當該高 精度振盪器處於工作模式時，該第三切換器14〇為開啟狀 9 1326524' 9% cpnJ bit value. When the indicator signal indicator is in the first state (〇), it indicates that the frequency of the frequency division signal elk div is less than the frequency of the frequency reference signal rEF_CLk, and the third bit of the N-bit control block is set to 〇. When the indicator signal indicator is in the second state (丨), indicating that the frequency 5 of the frequency-divided signal clk_div is not less than the frequency of the frequency reference signal REF_CLK, the i-th bit of the N-bit control sub-group is set to i. Where 丨 is an integer of 〇~(N1). When the high-precision oscillator is in the calibration mode, the logic control device g 115 outputs a low-potential (0) 2 Ready signal. When the high-precision oscillator is in the operating mode, the logic control device U5 outputs a potential (1). ) 10 Ready signals. The first data bus 120 is coupled to the n-bit output port 1151 for transmitting the first data bus signal to the digital control oscillating device 〇3 or the memory device 145. The first switch 125 is coupled to the first data bus 12 〇 for transmitting or blocking the signal of the first data bus 120 to the digital control oscillating device 130. The digitally controlled oscillating device 130 is coupled to the first switch 125 and coupled to the N-bit output 埠 1151 via the first switch 125 and the first data bus 12 。. The digitally controlled oscillating device 13 controls the value of the block according to the N bits to generate a timing signal clock. The frequency dividing device 135 is coupled to the digitally controlled oscillating device 13A to divide the timing signal clock to generate the frequency dividing signals ci and div. When the precision oscillator is in the calibration mode, the first switch 125 is in an on state to transmit the first data bus 12 signal. The digit 1326524 .--- control looping device 130 controls the value of the block according to the N-bit to generate the timing signal clock. The frequency detecting device 11 compares the frequencies of the frequency reference signal REF_CLK and the frequency dividing signal clk_div to generate the indication signal Indicator, and the logic control device 115 respectively sets the control word group according to the indication signal indicator 5 (N-1) The value of the bit to the 0th bit. When the high precision oscillator is in the active mode, the first switch 125 is in a closed state </ RTI> to block the first data bus 120 signal from being transmitted to the digitally controlled oscillating device 130. The first switch 165 is coupled to the first data bus 12 for transmitting or blocking the signal of the first data bus 120 to the memory device 145. The memory device 145 is coupled to the The second switch 165. When the 咼 precision vibrator is in the calibration mode, the second switch 165 is turned on, and the values of the (N-i)th to the ninth bits of the control block are sequentially written into the memory. In the body device 145. When the high precision oscillator is in the operating mode, the second switch 165 is in an off state to block the first data bus 120 signal from being written into the memory device 145. The second data bus 丨5〇 is coupled between the digitally controlled oscillating device 13〇 and the 戎έ 忆 装置 device 145. The third switch 14 is coupled to the memory device 145 for transmitting or blocking the output signal 20 of the memory device 145 to the digitally controlled oscillating device 13A. When the high-precision oscillator is in the calibration mode, the third switch 14 is turned off to block the output signal of the memory device 145 from being transmitted to the digitally controlled oscillating device 13 via the second tributary bus 150. . When the high-precision oscillator is in the operating mode, the third switch 14 is turned on. 9 1326524
態，以將該記憶體裝置145之輸出訊號經由第二資料匯流排 150而傳送至該數位控制振盪裝置130。 該工作模式選擇裝置170的第一輸入端連接至該邏輯 控制裝置115 ’以接收該邏輯控制裝置115輸出的Ready訊 5 號’該工作模式選擇裝置170的第二輸入端接收一模式選擇 訊號MODE。當該尚精度振盈器處於校準模式時，該邏輯控 制裝置115輸出的Ready訊號及該模式選擇訊號MODE均為 > 低電位（0) ’故該第四切換器160為關閉狀態。當該高精度振 盪器處於工作模式時’該邏輯控制裝置115輸出的尺以办訊 10 號或該模式選擇訊说MODE為高電位（1)時，該第四切換器 160則為開啟狀態。 該第四切換器160耦接於該數位控制振盪裝置13〇，用 以傳輸或阻隔該數位控制振盪裝置13〇之該時序訊號 clock。當該高精度振盪器處於校準模式時，該第四切換器 15 I60為關閉狀態，以阻隔該數位控制振盪裝置130所輸出之 該時序訊號clock傳送至該高精度振盪器之輸出訊號 CLKOUT。 當該高精度振盪器處於工作模式時，該第四切換器16〇 為開啟狀態，以傳輸該數位控制振盪裝置13〇所輸出之該時 序訊號clock傳送至該尚精度振盪器之輸出訊號。 當該高精度振盪器處於校準模式時，該邏輯控制裝置 115輸出低電位（〇)之11以办訊號， 為低電位（0)。此時，該第一切換 開啟狀態，第三切換器M〇及第它The output signal of the memory device 145 is transmitted to the digitally controlled oscillating device 130 via the second data bus 150. The first input end of the working mode selecting device 170 is connected to the logic control device 115' to receive the Ready signal No. 5 output by the logic control device 115. The second input end of the working mode selecting device 170 receives a mode selection signal MODE. . When the precision vibrator is in the calibration mode, the Ready signal output by the logic control device 115 and the mode selection signal MODE are both > low potential (0)', so the fourth switch 160 is in the off state. When the high-precision oscillator is in the operating mode, the fourth switch 160 is turned on when the logic control device 115 outputs the scale 10 or the mode selects the MODE to the high level (1). The fourth switch 160 is coupled to the digitally controlled oscillating device 13A for transmitting or blocking the timing signal clock of the digitally controlled oscillating device 13〇. When the high-precision oscillator is in the calibration mode, the fourth switch 15 I60 is in an off state, and the timing signal clock outputted by the digitally controlled oscillating device 130 is blocked from being transmitted to the output signal CLKOUT of the high-precision oscillator. When the high-precision oscillator is in the operating mode, the fourth switch 16 is turned on to transmit the output signal clock outputted by the digitally controlled oscillating device 13 to the output signal of the precision oscillator. When the high precision oscillator is in the calibration mode, the logic control unit 115 outputs a low potential (〇) of 11 for the signal to be low (0). At this time, the first switch is turned on, and the third switch M is turned on.
且一模式選擇訊號MODE 切換器125及第二切換器165為 ‘第四切換器160為關閉狀態。 1326524 • ' · · ?件4月ΐ日修正替換頁 > L___ ______ 當該高精度振盪器處於工作模式時，該邏輯控制裝置115輸 出高電位（1)之Ready訊號以及該模式選擇訊號MODE為高 電位（1)。此時，該第一切換器125及第二切換器165為關閉 狀態，第三切換器140及第四切換器160為開啟狀態。 5 圖2係本發明之具有自校準功能的高精度振盪器的校 準流程圖。其係用以設定一數位控制振盪裝置之N位元控制 字組，該數位控制振盪裝置依據該N位元控制字組以產生一 時序訊號。首先，於步驟S210，執行該振盪器之電路初始 ® 化，以將N位元控制字組之每一位元初始化為0。於步驟 10 S220，設定執行次數K為N-1。於步驟S230，設定該N位元 控制字組之第K位元為1。 於步驟S240，比較該數位控制振盪裝置產生的時序訊 號clock與一頻率參考訊號REF_CLK之頻率。當該時序訊號 clock頻率小於該頻率參考訊號REF_CLK之頻率時，執行步 15 驟S260，否則，執行步驟S250。 於步驟S260中，判定該時序訊號clock頻率小於該頻率 • 參考訊號REF—CLK之頻率時，設定該N位元控制字組之第K 位元為0。於步驟S250中，判定該時序訊號clock頻率非小於 該頻率參考訊號REF_CLK之頻率時，設定該N位元控制字 2〇 組之第（N-1 )位元為1。 於步驟S270中，將執行次數K減1。於步驟S280中，判 斷執行次數K是否小於0，若是，表示已經對N位元控制字 組設定完成，故執行步驟S290。若否，執行步驟S230。藉 此，重覆步驟S230至步驟S280,以依序設定該N位元控制字 1326524 « ------- I . I . , - --- 組之第N-2至第0位元。於步驟S29〇中，儲存該N位元控制字 組。 圖3係本發明之具有自校準功能的高精度振μ的頻 率調整示意圖。其中，該頻率參考訊號11£1?-(^]^的頻率為 5 6ΜΗΖ，範圍設定為（-30%)〜（+30%)，該Ν位元控制字 組為8位το，該數位控制振盪裝置13〇的頻率步階（Fre^en^ Step)為 0.028MHZ(=6MX60o/。/128)。亦即，只要調整該N位 &控制字組的位元數目，料調整該數位控制振盡裝置13〇 W 的頻率步階，而獲得高精度之振盪器。 10 由上述說明可知，本發明利用漸進方法，逐步求出該 N位元控制字組，利用本發明技術’只要調整該^^位元控制 字組位元數目，即可調整該數位控制振盪裝置13〇的頻率步 階，而獲得一高精度之振盪器，同時可解決同一晶圓上不 同地方的晶片會産生不同的振盪頻率的問題，並且可避免 15 振盪頻率容易隨溫度變化的問題。 上述實施例僅係為了方便說明而舉例而已，本發明所 籲主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 2〇 【圖式簡單說明】 圖1係本發明之具有自校準功能的高精度振盪器的方 塊圖。 圖2係本發明之具有自校準功能的高精度振以的流 程圖。 12 1326524 • ·，- w、-y·: 圖3係本發明之具有自校準功能的高精度振盪器的頻 率調整示意圖。 【主要元件符號說明】 頻率偵測裝置 110 邏輯控制裝置 115 第一資料匯流排 120 第一切換器 125 數位控制振盪裝置 130 除頻裝置 135 ► 第二切換器 165 記憶體裝置 145 10 第二資料匯流排 150 第三切換器 140 第四切換器 160 工作模式選擇裝置 170 第一輸入端 111 第二輸入端 112 13And a mode selection signal MODE switch 125 and a second switch 165 are "the fourth switch 160 is in a closed state. 1326524 • '···April 2017 Correction Replacement Page> L___ ______ When the high-precision oscillator is in the operation mode, the logic control device 115 outputs the Ready signal of the high potential (1) and the mode selection signal MODE is High potential (1). At this time, the first switch 125 and the second switch 165 are in a closed state, and the third switch 140 and the fourth switch 160 are in an open state. 5 Figure 2 is a calibration flow chart of the high precision oscillator with self-calibration function of the present invention. It is used to set a N-bit control block of a digitally controlled oscillating device, and the digital control oscillating device controls the block according to the N-bit to generate a timing signal. First, in step S210, the circuit initialization of the oscillator is performed to initialize each bit of the N-bit control block to zero. In step 10 S220, the number of execution times K is set to N-1. In step S230, the Kth bit of the N-bit control block is set to 1. In step S240, the frequency of the timing signal clock generated by the digitally controlled oscillating device and a frequency reference signal REF_CLK is compared. When the timing signal clock frequency is less than the frequency of the frequency reference signal REF_CLK, step S260 is performed; otherwise, step S250 is performed. In step S260, it is determined that the timing signal clock frequency is less than the frequency of the reference signal REF_CLK, and the Kth bit of the N-bit control block is set to zero. In step S250, when it is determined that the timing signal clock frequency is not less than the frequency of the frequency reference signal REF_CLK, the (N-1)th bit of the N-bit control word 2 group is set to 1. In step S270, the number of executions K is decremented by one. In step S280, it is judged whether or not the number of executions K is less than 0. If so, it indicates that the setting of the N-bit control block has been completed, and therefore step S290 is executed. If no, step S230 is performed. Thereby, step S230 to step S280 are repeated to sequentially set the N-bit control word 1326524 « ------- I . I . , - --- group N-2 to 0th bit . In step S29, the N-bit control word group is stored. Fig. 3 is a schematic diagram showing the frequency adjustment of the high-precision vibrating μ with the self-calibration function of the present invention. Wherein, the frequency reference signal 11 £1?-(^]^ has a frequency of 5 6 ΜΗΖ, the range is set to (-30%) 〜(+30%), and the Ν bit control block is 8 bits το, the digit The frequency step (Fre^en^Step) of the control oscillating device 13〇 is 0.028MHZ (=6MX60o/./128). That is, as long as the number of bits of the N-bit & control block is adjusted, the number is adjusted. The frequency step of the oscillating device 13 〇W is controlled to obtain a high-precision oscillator. 10 From the above description, the present invention uses a progressive method to gradually find the N-bit control block, using the technique of the present invention. The ^^ bit controls the number of word bits, and the frequency step of the digitally controlled oscillating device 13〇 can be adjusted to obtain a high-precision oscillator, and at the same time, the wafers in different places on the same wafer can be different. The problem of the oscillating frequency, and the problem that the oscillating frequency is easy to change with temperature can be avoided. The above embodiments are merely examples for convenience of description, and the scope of the claims claimed herein is based on the scope of the patent application. It is not limited to the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a high-precision oscillator with self-calibration function of the present invention. Figure 2 is a flow chart of the high-precision vibration with self-calibration function of the present invention. 12 1326524 • ·,- W, -y·: Figure 3 is a schematic diagram of the frequency adjustment of the high-precision oscillator with self-calibration function of the present invention. [Main component symbol description] Frequency detecting device 110 logic control device 115 First data bus 120 first switching Timer 125 digitally controlled oscillating device 130 frequency dividing device 135 ► second switch 165 memory device 145 10 second data bus 150 third switch 140 fourth switch 160 operating mode selection device 170 first input 111 second Input 112 13