1326512 因此，需要一種新穎的發明以解決上述之問題。 【發明内容】 因此，本發明的目的之一為提供一種靜電放電保護電路，其使 傳輸閘電路不直接耦接於延遲電路，以避免傳輪閘電路在ESD脈 衝進入時無法關閉。 本發明的目的之一為提供一種靜電放電保護電路，其利用特定 之金氧半導體電晶體以提供偏壓電聲給傳輸閘電路，以避免寄生 的NPN路徑。 本發明之較佳實施例揭露了一種靜電放電保護電路，包含·· 一 靜電放電保護元件、一傳輸閘電路、一第一 N型金氧半導體電晶 體、一第一 P型金氧半導體電晶體、一延遲電路、一第一反相= 籲輯電路以及-第二反相邏輯電路。靜電放電保護元件，耗接於一 連接墊。傳輪閘電路耦接於連接墊與一輸出端。第一 N型金氧半 導體電晶_接至傳輸閘電路以及—第二電壓準位，用以依據第 -電塵準倾供—第—偏壓予傳輸閘電路。第—p型金氧半導體 ^晶體^接至傳輸閘電路以及第—電壓準位，用以依據第一電 了提供第—偏壓予傳輸閘電路。延遲電路輕接至靜電放電 '、蒦元件肖以決疋傳輸間電路之開啟何㈣時間。第—反相邏 接於延遲電路、傳輸_路以及N縣氧半導體電晶 用以依據延遲電路之輸出而產生―第—控制訊號。第二反相 ===接於第—反相邏輯電路、p型金氧半導體電晶體以及傳 輸間電路，用以依據第—反相辦電路之輸出而產生—第二控制 ^虎，其中傳輸閘電路係依據第―、第二控制訊號而 地 啟或關閉。 輸閉電路可包含·· — N型金氧半導體電晶體，其閉極輕接 於第-N型金氧半導體電晶體之閘極，針第—n型金氧半導體 電晶體之源極與祕分_接於第二電壓準位與該第二N型金氧 半導體電Μ之P井(P_We丨丨)或基歸Gdy);—第二p型金氧半導 體電晶體，並聯於第二N型金氧半導體電晶體，且其_輕接於 第P型金氧半導體之閘極，其中第一p型金氧半導體電晶體之 源、極與;及極分她接於第-電鮮位與第二P型金氧半導體電晶 體之N井(N-Wen)。 • 根據以上之電路，不僅可以在ESD脈衝產生時，傳輸間電路 得以關閉較得内部電路和連接墊得以隔絕。亦可避免因為寄生 作用而產生不必要之導通路徑。. 【實施方式】 在說明書及後續㈣料利顧當巾使用了某些詞彙來指稱 特疋的70件。所屬領域中具有通素知_者應可理解，硬體製造商 可此會用不同的名詞來稱呼同—個元件。本說明書及後續的申請 專利範圍並不以名稱的差異來作為區分元件的方式 ，而是以元件 功此上的差異來作為區分的準則。在通篇說明書及後續的請求 I田中所提及的「包含」係為—㈤放式賴語，故應解釋成广包 ’ 3但不限疋於」。以外’「雛」-詞在此係包含任何直接及間接 .的電乳連接手段。因此’若文中描述—第—裝置雛於―第二裳 -置’則代表該第-衰置可直接電氣連接於該第二裝置 ，或透過其 他裝置或雜手段嶋哟祕接·.帛二裝置。 鲁 第3圖、·會示了根據本發明之較佳實施例的靜電放電保護電路 300。如第3圖所示，靜電放電保護電路3〇〇包含：一靜電放電保 護元件30^、-傳輸閘電路3〇3、一 N型金氧半導體電晶體3〇5、 - P型金氧半導體電晶體307、—延遲電路3G9、—第一反相邏輯 電路31卜-第二反相邏輯電路313。靜電放電保言蔓元件训雛 於-連接塾315,在此實施例中靜電保護元件則係由兩整流元件 317和319組成’而此兩整流元件317和319可由二極體或金氧半 •導體電晶體所組成。傳輸閘電路303.耦接於連接墊3丨5與一輸出 端32卜而在此實施例中輸出端321係耦接至一内部電路％〕，但 此輸出端321亦可補至其他電路。N型金氧半導體電晶體顺可 視為一半導體單元)搞接至.傳輸閘電路303.以及一第二電麼準位 VGND (即一電源線），用以提供一第一偏壓予傳輸閘電路邓p須 注意的是，傳輸閘電路303之結構僅用以舉例，並不受限於第3 圖所示之架構。 P型金氧半導體電晶體3〇7 (可視為另—半物單^)則柄接 13.26512 至傳輸閘電路303以及一第一電壓準仅Vcc‘（另一電源線），用以 依據第一電壓準位Vcc提供一第二偏壓予傳輸閘電路303。延遲電 . 路309耦接至靜電放電保護元件301，用以決定傳輸閘電路3〇3 .之開啟和關閉時間。在此實施例中，延遲電路309包含一電容325 以及一電阻327 ’並係利用電容325以及電阻327之值以決定傳輸 閘電路303之開啟和關閉時間’但並非用以限定本發明。電容325 及電阻327串連於節點C，此節點C上的訊號即可視為一靜電放 .電的彳貞測訊號。第一反相邏輯電路311輕接於延遲電路309、傳輸 閘電路303以及N型金氧半導體電晶體305，用以依據延遲電路 309之輸出（即偵測訊號）而產生广第—控制訊號。第二反相邏輯 電路3Π耦接於第一反相邏輯電路3n、p型金氧半導體電晶體兕7 以及傳輸閘電路303,用以依據第一反相邏輯電路3U之輸出而產 生一第二控制訊號CS2，其中傳輸閘電路3〇3係依據第一、第二控 制訊號CS〗、CS2而選擇性地開啟或關閉。 傳輸閘電路303係為“傳輸閘.（transmissi〇n gate)，並包含一 n 型金氧半導體電晶體329以及P型金氧半導體電晶體別，但並非 用以限定本發明。如第3 ，N型金t；半導體電晶體329之 閘極（可視為第—受控端）輕接於N型金氧半導體電晶體奶之 閘極且N型金乳半導體電晶體3〇5之源極與沒極分別輕接於第 二電壓準位N型金氧半導體電晶體329之P井〇>_则)或 基底(body)。P型金氧半導體電晶體331並聯於 晶體329,且1間搞# 乳+導體電 且其閘極（可視為第二受㈣）_於該p型金氧半導 職接2極’其中p型金氧半導體電晶體307之源極與祕分 稍接於第一電壓準位νΑρ型金氧半導體電晶體331之N井 (Well)。而且，在此實施例中，第一反相邏輯電路Mi以及第二 反相邏輯電路313係為反相器，但亦可利用其他邏輯電路達成相 同之功效。 底下將說明根據靜電放電保護電路3〇〇在正常操作情況、ps • (positive to Vss)模式、NS (negative to Vss)模式、pd (positive t01326512 Therefore, a novel invention is needed to solve the above problems. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an electrostatic discharge protection circuit that does not directly couple a transmission gate circuit to a delay circuit to prevent the transfer gate circuit from being turned off when an ESD pulse enters. It is an object of the present invention to provide an electrostatic discharge protection circuit that utilizes a particular MOS transistor to provide biased electrical sound to the transmission gate circuit to avoid parasitic NPN paths. A preferred embodiment of the present invention discloses an electrostatic discharge protection circuit including an electrostatic discharge protection component, a transmission gate circuit, a first N-type MOS transistor, and a first P-type MOS transistor. a delay circuit, a first inversion = an appeal circuit, and a second inverting logic circuit. The ESD protection component is consumed by a connection pad. The transmission wheel circuit is coupled to the connection pad and an output end. The first N-type MOS transistor is connected to the transmission gate circuit and the second voltage level for pre-biasing the first-electrode dust-to-transfer gate circuit. The first-p-type MOS transistor is connected to the transmission gate circuit and the first voltage level for providing the first bias to the transmission gate circuit according to the first power. The delay circuit is lightly connected to the electrostatic discharge ', and the 蒦 element is used to determine the opening time of the circuit between the transmissions. The first-inverting logic is coupled to the delay circuit, the transmission path, and the N-channel oxygen semiconductor transistor for generating a "first" control signal according to the output of the delay circuit. The second inversion=== is connected to the first-inverting logic circuit, the p-type MOS transistor, and the inter-transmission circuit for generating according to the output of the first-phase circuit, and the second control is transmitting The gate circuit is turned on or off according to the first and second control signals. The transmissive circuit may comprise an N-type MOS transistor, the closed-pole light is connected to the gate of the -N-type MOS transistor, and the source of the pin-n-type MOS transistor is secret a P-well (P_We丨丨) or a G-to-Gdy) connected to the second N-type MOS transistor; the second p-type MOS transistor, connected in parallel to the second N a MOS transistor, and is lightly connected to the gate of the P-type MOS, wherein the source and the pole of the first p-type MOS transistor; and the pole is connected to the first-electrode N well (N-Wen) with a second P-type MOS transistor. • According to the above circuit, not only can the inter-transmission circuit be turned off when the ESD pulse is generated, but the internal circuit and the connection pad can be isolated. It is also possible to avoid unnecessary conduction paths due to parasitic effects. [Embodiment] In the manual and the subsequent (4) materials, some words were used to refer to 70 pieces of special features. It should be understood by those skilled in the art that hardware manufacturers may refer to the same component by different nouns. This specification and subsequent applications The scope of patents does not use the difference in name as the way to distinguish between components, but the difference in component merits as a criterion for differentiation. In the general specification and subsequent requests, the "inclusion" mentioned in I Tianzhong is - (5) the Lai language, so it should be interpreted as a wide package '3 but not limited to". The term """ is used in this section to include any direct and indirect means of connection. Therefore, if the description in the text - the first device is in the "second skirt - set", it means that the first-fade can be directly electrically connected to the second device, or through other devices or miscellaneous means. Device. Lu 3 shows an electrostatic discharge protection circuit 300 in accordance with a preferred embodiment of the present invention. As shown in FIG. 3, the electrostatic discharge protection circuit 3 includes: an electrostatic discharge protection element 30^, a transmission gate circuit 3〇3, an N-type MOS transistor 3〇5, a P-type MOS semiconductor. The transistor 307, the delay circuit 3G9, the first inverting logic circuit 31, and the second inverting logic circuit 313. The electrostatic discharge protection element is taught in the connection port 315. In this embodiment, the electrostatic protection element is composed of two rectifying elements 317 and 319, and the two rectifying elements 317 and 319 can be diode or galvanic. The conductor is composed of a transistor. The transmission gate circuit 303 is coupled to the connection pad 3丨5 and an output terminal 32. In this embodiment, the output terminal 321 is coupled to an internal circuit %], but the output terminal 321 can be supplemented to other circuits. The N-type MOS transistor can be seen as a semiconductor unit) connected to the transmission gate circuit 303. and a second voltage level VGND (ie, a power line) for providing a first bias voltage to the transmission gate. It should be noted that the structure of the transfer gate circuit 303 is for example only and is not limited to the architecture shown in FIG. P-type MOS transistor 3〇7 (can be regarded as another-semi-object ^), the handle is connected to 13.26512 to the transmission gate circuit 303 and a first voltage is only Vcc' (another power line) for the first The voltage level Vcc provides a second bias to the transfer gate circuit 303. The delay circuit 309 is coupled to the ESD protection component 301 for determining the turn-on and turn-off times of the transfer gate circuit 3〇3. In this embodiment, delay circuit 309 includes a capacitor 325 and a resistor 327' and utilizes the values of capacitor 325 and resistor 327 to determine the turn-on and turn-off times of transmission gate circuit 303, but is not intended to limit the invention. The capacitor 325 and the resistor 327 are connected in series to the node C, and the signal on the node C can be regarded as an electrostatic discharge signal. The first inverting logic circuit 311 is connected to the delay circuit 309, the transmission gate circuit 303, and the N-type MOS transistor 305 for generating a wide-control signal according to the output of the delay circuit 309 (ie, the detection signal). The second inverting logic circuit 3 is coupled to the first inverting logic circuit 3n, the p-type MOS transistor 兕7, and the transmission gate circuit 303 for generating a second according to the output of the first inverting logic circuit 3U. The control signal CS2, wherein the transmission gate circuit 3〇3 is selectively turned on or off according to the first and second control signals CS, CS2. The transmission gate circuit 303 is a "transmissi〇n gate" and includes an n-type MOS transistor 329 and a P-type MOS transistor, but is not intended to limit the invention. N-type gold t; the gate of the semiconductor transistor 329 (which can be regarded as the first-controlled end) is lightly connected to the gate of the N-type MOS transistor milk and the source of the N-type gold-milk semiconductor transistor 3〇5 The P-type MOS transistor 331 is connected in parallel with the crystal 329, and the P-type MOS transistor 331 is connected in parallel with the second voltage level of the N-type MOS transistor 329. Engage #乳+ Conductor and its gate (can be regarded as the second (4)) _ in the p-type MOS semi-conducting 2 pole 'where the source and secret of the p-type MOS transistor 307 are slightly connected The first voltage level ν Α p type MOS transistor 331 N well (Well). Moreover, in this embodiment, the first inverting logic circuit Mi and the second inverting logic circuit 313 are inverters, but Other logic circuits can also be used to achieve the same effect. The following will explain the normal operation according to the electrostatic discharge protection circuit 3 , Ps • (positive to Vss) mode, NS (negative to Vss) mode, pd (positive t0
Vdd)模式、以&ND(negativet〇 vdd)模式下的運作情形。在正常 if况下（亦即未有ESD脈衝產生）’自第一反相邏輯電路川之輸 出點A輸出的第一控制訊號⑶之準位為高，而自第二反相邏輯 電路312之輸出點b輸出的第二控制訊號CS2之準位為低。因此 N型金氧半導體電晶體3〇5、p型金氧半導體電晶體、N型金 氧半導體電晶體329以及P型金氧半導體電晶體mi為導通之狀 • 態’具有較低之輸入阻抗。 當ESD脈衝進入時’若為ps模式’則第一反相邏輯電路川 之閘點C由於透過電容325耦合至ESD脈衝的關係，其準位為高， 因此輸出點A之電壓為低而輸出點b為高。因此N型金氧半導體 •電晶體305、P型金氧半導體電晶體3〇7、N型金氧半導體電晶體 329以及P型金氧半導體電晶體331為關閉之狀態，故ESD脈衝 並不會流入内部電路323。在此情況下.，ESD脈衝主要是由整流 元件319導出，亦可由其他外圍輔助電路所導出。·此外圍輔助電 故杳此不再贅述 路由於係為熟知此項技藝考所知悉， _tNS^T ’施件319料仙輸SD脈衝。㈣ 、工 整流几件317被導通以導出ESD脈衝。 而在ND模式下，整減元件3】_9被導通，第二電鮮位被拉至 與挪脈衝相近之賴，因為咖脈衝為負向電壓，相對地第一 電壓準位成為姉高之準位,__電路3ιι之_ C輕 接於相對高之準位’因此自輸出點A輸出的控制訊號q之準位 f低而自輸出點B輸出的控制訊號CS2之準位為高，因此N型金 氧半導體電晶體305、P型金氧半導體電晶體3〇7、N型金氧 體電晶體B以及P型金氧半導體電晶體％丨為關閉之狀態，故 ESD脈衝不會流入内部電路323·。在此情況下，esd脈衝主要是 由整流元件317導出，亦可由其他賴_電路所導出。此外圍 輔助電路由於係為熟知此項者所知悉，故在此不再資述。 根據上述電路結構，由於p型金氧半導體電晶體331未直接輕 接於延遲電路309，因此不會有無法_之情況，而且p型金氧半 導體電晶體307可防止寄^通道（譬如說是NpN寄生通道）之產 生。且此電路並未使用！X.共振電路，因此可避免潛在震蓋問題， 面積方面亦可由調整傳輸閘電路之閘極寬度來調整。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 12 13.26512 301靜電放電保護元件 303傳輸閘電路 -305 N型金氧半導體電晶體 307 P型金氧半導體電晶體 309延遲電路 311第一反相邏輯電路 313第二反相邏輯電路 籲315連接墊 317、319整流元件 321輸出端 323内部電路 325電容 327電阻 329 N型金氧半導體電晶體 • 331 P型金氧半導體電晶體Vdd) mode, operation in & ND (negativet〇 vdd) mode. In the normal case (ie, no ESD pulse is generated), the level of the first control signal (3) output from the output point A of the first inverting logic circuit is high, and the second inverting logic circuit 312 is The level of the second control signal CS2 outputted by the output point b is low. Therefore, the N-type MOS transistor 3〇5, the p-type MOS transistor, the N-type MOS transistor 329, and the P-type MOS transistor mi are turned on. The state has a low input impedance. . When the ESD pulse enters, 'if ps mode', the first inverting logic circuit C is connected to the ESD pulse due to the transmission capacitor 325, and its level is high, so the output point A is low and the output is low. Point b is high. Therefore, the N-type MOS semiconductor 305, the P-type MOS transistor 3〇7, the N-type MOS transistor 329, and the P-type MOS transistor 331 are in a closed state, so the ESD pulse does not occur. Flows into the internal circuit 323. In this case, the ESD pulse is mainly derived by the rectifying element 319 or may be derived by other peripheral auxiliary circuits. · This peripheral auxiliary electric power will not be described here. Since the road is known to the technical know-how, _tNS^T ’ 319 materials are used to input SD pulses. (d), work rectification several pieces 317 are turned on to derive ESD pulses. In the ND mode, the reduction component 3]_9 is turned on, and the second electric fresh bit is pulled to be close to the pulse, because the coffee pulse is a negative voltage, and the first voltage level is relatively high. Bit, __ circuit 3 ιι__ C is lightly connected to a relatively high level 'Therefore the level f of the control signal q outputted from the output point A is low and the level of the control signal CS2 outputted from the output point B is high, therefore The N-type MOS transistor 305, the P-type MOS transistor 3〇7, the N-type MOS transistor B, and the P-type MOS transistor %丨 are in a closed state, so the ESD pulse does not flow into the interior. Circuit 323·. In this case, the esd pulse is mainly derived by the rectifying element 317, and may also be derived by other circuits. In addition, since the peripheral auxiliary circuit is known to those skilled in the art, it will not be described here. According to the above circuit configuration, since the p-type MOS transistor 331 is not directly connected to the delay circuit 309, there is no possibility that the p-type MOS transistor 307 can prevent the channel (for example, Generation of NpN parasitic channels). And this circuit is not used! X. Resonance circuit, so that the potential cover problem can be avoided, and the area can also be adjusted by adjusting the gate width of the transmission gate circuit. The above description is only a preferred embodiment of the present invention, and the application of the invention 12 12265512 301 electrostatic discharge protection element 303 transmission gate circuit - 305 N-type MOS transistor 307 P-type MOS transistor 309 delay Circuit 311 first inverting logic circuit 313 second inverting logic circuit 315 connection pad 317, 319 rectifying element 321 output end 323 internal circuit 325 capacitance 327 resistance 329 N-type MOS transistor • 331 P-type MOS semiconductor Crystal