1323473 -玖、發明說明： 【發明所屬之技術領域】 本發明係提供一種被動元件之結構，尤指一種電容結 構0 【先前技術】 如業界所習知，被動元件（譬如電阻，電感，電容等等） 已經是電路中一個相當基礎的元#，而帛泛地使用於各種 積體電路之中，以電容為例，在射頻電路、遽波器、震烫 器之中’都可以看到電容的縱影。 一=來說，在積體電路中，電容大部分係以平板堆疊 的結構貫施；常見的平板堆疊之電容結構大致上包含複數 導電板並且’於複數個導電板中，每兩個相鄰的導電 板係分別對應不同的電性(亦即兩相鄰導電板之間且有— :位差），並且各導電板之間係以介電質層予以分隔。如此 -來，母兩個相鄰的導電板便可看作是一個平板電容單 :二：，對於整個電容結構來說，#等效的電容值便可 4於母一個平板電容單元的總和。 於美國專利第5583359號中，揭露了 __ 堆疊的電容姓槿/ "办 揭路了種梳型的平板 電容結構：體I:1圖’第1圖為其揭露的 體圖。如弟i圖所示，電 -式的架構’其與習知的堆疊結構的 二 電板交#而: 導電板係由兩個梳狀（手指狀）的導 成，而同一層導電板的兩個梳狀導電板便已彼 1323473 •此對應不同的電性’並且彼此之間亦利用介電層予以分 隔；理論上’由於兩個梳狀導電板之間具有不同的電性， 其彼此之間便已具有電容效應，因此，這樣的作法可以允 許於一個導電板中獲得所須的電容效應，對於整體電容架 構而言’可取得的電容效應更佳。 此外’在美國專利第5220483號、美國專利第6743671 號、以及美國專利第6784050號中’皆揭露了類似的電容 架構’故於此便不在贅述；然而，隨著科技的進步，並且 積體電路的集成度越來越高的狀況下，如何能‘更小的晶 片區域（chip area)之中取得更佳的電容效應（電容值），已經 成為目前一個重要的課題。而前述的電容架構，雖然已能 改善原始的堆疊架構的一些缺點，但於使用上仍差強人 意。 【發明内容】 因此本發明之主要目的之一在於提供一種改良式的 電谷結構，以解決習知技術中的問題。 根據本發明之一實施例，係揭露一種電容結構，該電 容結構包含有：至少一第一電容單元，該第一電容單元包 含有·一第一導電島柱；一第一介電層，環繞該第一導電 島柱；以及一第一導電側壁，環繞該第一介電層；其中該 第一導電側壁與該第一導電島柱之間係具有一電位差。/ 根據本發明之一實施例，另揭露一種積體電容 (Integrated Capacit〇r)，其包含有：一半導體基板； 第電谷層，位於该半導體基板之上，包含：一第一導電島 1323473 (Conductive Island), —第一介電壁（Dieiectric WaI1)，環繞該 導電島；以及一第一導電壁（Conductive Wall)，環繞該介電壁， 並包含複數個第一插塞（Via);以及至少一電源層（p〇wer1323473 - 发明, invention description: [Technical field of the invention] The present invention provides a passive component structure, especially a capacitor structure 0 [Prior Art] As is known in the art, passive components (such as resistors, inductors, capacitors, etc.) Etc.) is already a fairly basic element in the circuit, and is widely used in various integrated circuits. Taking capacitors as an example, capacitors can be seen in RF circuits, choppers, and shakers. Longitudinal. One = in terms of the integrated circuit, the majority of the capacitance is applied in a flat stacked structure; the common planar stacked capacitor structure generally comprises a plurality of conductive plates and 'in a plurality of conductive plates, each two adjacent The conductive plates respectively correspond to different electrical properties (that is, between two adjacent conductive plates and have: - a difference in position), and the conductive plates are separated by a dielectric layer. In this way, the two adjacent conductive plates of the mother can be regarded as a single plate capacitor single: two: for the entire capacitor structure, the equivalent capacitance value of # can be the sum of the mother and one plate capacitor unit. In U.S. Patent No. 5,583,359, the __-stacked capacitor surname 槿/ " is disclosed; the flat-plate capacitor structure of the comb type: body I:1Fig. 1 is a body diagram disclosed therein. As shown in the figure i, the electro-mechanical architecture 'is in contact with the conventional two-electrode stacking structure: the conductive plate is guided by two combs (finger-like), and the same layer of conductive plates Two comb-shaped conductive plates have been 13143347 • This corresponds to different electrical properties and is also separated from each other by a dielectric layer; theoretically, due to the different electrical properties between the two comb-shaped conductive plates, they are mutually There is already a capacitive effect between them, so this approach allows for the desired capacitive effect in a conductive plate, and the resulting capacitive effect is better for the overall capacitive architecture. In addition, 'a similar capacitor architecture is disclosed in U.S. Patent No. 5,204, 083, U.S. Patent No. 6,743, 671, and U.S. Patent No. 6,784,050, the disclosure of which is hereby incorporated by reference. With the increasing integration, how to achieve better capacitive effect (capacitance value) in a smaller chip area has become an important issue at present. The aforementioned capacitor architecture, although it has been able to improve some of the shortcomings of the original stack architecture, is still somewhat unsatisfactory in its use. SUMMARY OF THE INVENTION It is therefore one of the primary objects of the present invention to provide an improved electric valley structure to solve the problems in the prior art. According to an embodiment of the invention, a capacitor structure is disclosed. The capacitor structure includes: at least one first capacitor unit, the first capacitor unit includes a first conductive island pillar; and a first dielectric layer surrounding The first conductive island pillar; and a first conductive sidewall surrounding the first dielectric layer; wherein the first conductive sidewall and the first conductive island pillar have a potential difference. According to an embodiment of the present invention, an integrated capacitor includes: a semiconductor substrate; a second valley layer on the semiconductor substrate, comprising: a first conductive island 1323473 (Conductive Island), a first dielectric wall (Dieiectric WaI1) surrounding the conductive island; and a first conductive wall surrounding the dielectric wall and including a plurality of first plugs (Via); And at least one power layer (p〇wer
Layer)，位於該半導體基板之上，該電源層耦接該些第一插塞，用 來提供該導電壁一預設電位；其中該導電壁與該導電島間具有一電 位差。 本發明提出了另一種電容結構，以於更小的晶片區域 中取得更佳的電谷值，如此一來，本發明便可於有限的晶 片區域中，建置電路設計者所須的電容。 【實施方式】 以下參考圖式詳細說明本發明。 '•月參閱第2圖與第3圖。苐2圖為本發明電容結構3〇〇 之弟實施例的立體圖，而第3圖為本發明電容結構3 〇 〇 之第一實施例的俯視圖。如第2圖所示，電容結構3〇〇亦 類似於前述的堆疊結構，其具有複數個電容層31〇、32〇。 而母一個電容層310、320包含有複數個電容單元。在 此請注意，為了簡便起見，第2〜3圖僅繪示了複數個電容 單元330,然而，在實作上，電容結構3〇〇包含有更多的 電容單元330。 此外’在此請注意，於本實施例中，電容結構3〇〇係 為由半導體製程製作而成，因此，電容結構3〇〇另具有一 半導體基板以及一隔離層，其中該隔離層係位於該電容層 與該半導體基板之間，用來防止電容結構3〇〇與半導體基 1323473 板互相接觸而導致整體電容結構3〇〇無法正常運作。然 而，為了簡化起見，於第2、3圖 亦未繪不出則述的半 體基板以及隔離層；$而’此領域具有通常知識者岸可 理解半導體基板以及隔離層之結構與運作，故不另贊述於 此0 於本實施例中，每一個電容單元33〇皆包含有一金屬 島柱331以及-金屬側壁332’如第2圖所示，四方形的 金屬側壁312係位於金屬島柱331之外，並環繞金屬島柱 331 ° 請參閱第3圖，金屬側壁332與金屬島柱331之間具 有一介電層333，介電層333亦環繞金屬島柱331，以將 金屬側壁332與金屬島柱33 1分隔開來。然而，在此請注 意，為了清楚起見，第2圖僅繪示出了金屬島柱331與金 屬側壁332 ’而省略了介於其間的介電層333。 此外，爲了獲得電容效應，金屬侧壁332與金屬島柱 33 1係分別對應不同的電性，換句話說，金屬侧壁332與 金屬島柱33 1之間係具有一電位差。舉例來說，金屬側壁 3 32可對應正電位’而金屬島柱33丨則對應反向的負電位， 如此一來，金屬側壁332與金屬島柱33 1之間便會具有對 應的電容值。 在此請注意’兩相鄰電容層之間亦以一介電質將兩相 鄰電容層分隔開來；此外，如第2圖與第3圖所示，每一 個電容單元330包含有複數個插塞（via)334。於本實施例 中’插塞334係用來連接兩相鄰電容層310、320，因此， 插塞334連接到的兩端舍 响T具有相同的電性。 於本實施例中，含奎炎M 、 °月，閱第3圖，金屬島柱331係具有 一插塞334，而金屬伽辟^ 』332則於其四個角落上分別配置 有一插塞334。因此，於太眘 %本貫把例中，位於不同的電容層 3 10、3 2 0的金屬側带u 9在- 32係错由位於四角的插塞334連接 在一起，因此，不同雷突思， J電4層310、320的金屬側壁332係 具有相同的電性；另一方而 力 方面，位於不同電容層31〇、32〇 的金屬島柱331則藉由付#甘 J稽田位於其上的插塞3 34連接在一起， 因此，位於不同電容；s ：5In、 电令噌jlO' 320的金屬島柱331亦具有 相同的電性。 舉例來說，若金屬側壁332係對應正電位，而金屬島 柱331則對應負電位，那麼，於本實施例中，所有的金屬 側壁332皆對應正電位，並且所有的金屬島柱33 i皆對應 負電位。如前所述，每一個電容單元33〇皆可藉由其内部 的金屬島柱331與金屬侧壁332而產生一電容效應，因 此對於整體電容結構300來說，其整體的電容效應便對 應全部電容單元330所產生之電容效應的總和。 在此請注意’以現在的製程技術，大致上都已經利用 〇. 1 8微米以下的製程進行前述電容結構3〇〇的製作；這意 味著金屬側壁332與金屬島柱331之間的間隔（pitch)可以 做到相當小’如業界所習知，若金屬侧壁332與金屬島柱 33 1之間的間隔越小，可獲得的電容效應越大。因此，本 發明之電容結構300較佳地以0· 1 8微米以下的製程實作 之’以増強其可獲得的電容效應。 10 丄⑷4/3 此外，為了使金屬侧壁332(或/及金屬島柱33 1}具有 如刚述之預定電位，一般來說，電容結構3〇〇係另包含有 至少一電源層（Power Layer )，位於該半導體基板之上， 該電源層可透過複數個插塞，連接至金屬側壁332，如此 一來，金屬側壁332便可提供該導電壁一預設電位，使其 具有預設的電性。在此請注意，由於電源層的結構與操作 已為業界所熟知，揭露至此，此領域具有通常知識者應可 理解，故不另資述於此。 在此請參閱第4圖與第5圖。第4圖為本發明電容結 構400之第二貫施例的立體圖；而第5圖為本發明電容結 構400之第二實施例的俯視圖。相同地，電容結構亦 具有複數個電容層410、420。而每一個電容層41〇、420 包含有複數個電容單元43 0。在此請注意，為了簡便起見， 第4〜5圖僅繪示了複數個電容單元4 3 0，然而，電容結構 400實可包含更多的電容單元430。 在此請注意’為了簡化起見，於第4、5圖中亦未繚 示與電容結構400相關的半導體基板以及隔離層。然而， 此領域具有通常知識者應可理解半導體基板以及隔離層 之結構與運作’故不另贅述於此。 在此請注意，於本實施例中，每一個電容單元430與 前述的電容單元330具有相同的結構與運作；舉例來說， 電容單元43〇亦包含有一金屬島柱431、一金屬側壁432、 以及一介電層433 ’由於其結構與運作已於前面的揭露中 陳述，故不另贅述於此。 11 1323473 請參閱第4圖’相同地’於本實施例中，兩相鄰電容 層410、420之間亦以一介電質將兩相鄰電容層分隔開來； 此外，如第2圖與第3圖所示’每一個電容單元43〇包含 有複數個插塞（via)434。而插塞434係用來連接兩相鄰電 容層410、420，因此，插塞434連接到的兩端會具有相同 的電性。The layer is disposed on the semiconductor substrate, and the power layer is coupled to the first plugs to provide a predetermined potential of the conductive wall; wherein the conductive wall and the conductive island have a potential difference. The present invention proposes another capacitor structure to achieve a better electrical valley value in a smaller wafer area, so that the present invention can build the capacitance required by the circuit designer in a limited area of the wafer. [Embodiment] Hereinafter, the present invention will be described in detail with reference to the drawings. '•Monday refers to Figure 2 and Figure 3. FIG. 2 is a perspective view of the embodiment of the capacitor structure 3 为本 of the present invention, and FIG. 3 is a plan view of the first embodiment of the capacitor structure 3 〇 发明 of the present invention. As shown in Fig. 2, the capacitor structure 3〇〇 is also similar to the aforementioned stacked structure, and has a plurality of capacitor layers 31〇, 32〇. The parent capacitor layer 310, 320 includes a plurality of capacitor units. Note here that for the sake of simplicity, Figures 2 through 3 illustrate only a plurality of capacitor units 330. However, in practice, the capacitor structure 3A includes more capacitor units 330. In addition, in this embodiment, the capacitor structure 3 is fabricated by a semiconductor process. Therefore, the capacitor structure 3 further has a semiconductor substrate and an isolation layer, wherein the isolation layer is located. The capacitor layer and the semiconductor substrate are used to prevent the capacitor structure 3〇〇 from contacting the semiconductor substrate 1323473 board, and the overall capacitor structure 3〇〇 cannot operate normally. However, for the sake of simplicity, the half-substrate and the isolation layer described in FIGS. 2 and 3 are not depicted; and the structure and operation of the semiconductor substrate and the isolation layer are understood by those skilled in the art. Therefore, in this embodiment, each of the capacitor units 33A includes a metal island pillar 331 and a metal sidewall 332'. As shown in FIG. 2, the square metal sidewall 312 is located at the metal island. Outside the column 331 and surrounding the metal island column 331 °, referring to FIG. 3, a dielectric layer 333 is formed between the metal sidewall 332 and the metal island pillar 331, and the dielectric layer 333 also surrounds the metal island pillar 331 to extend the metal sidewall. The 332 is spaced apart from the metal island column 33 1 . However, please note here that for the sake of clarity, Figure 2 only depicts the metal island pillars 331 and the metal sidewalls 332' with the dielectric layer 333 interposed therebetween omitted. In addition, in order to obtain a capacitive effect, the metal sidewall 332 and the metal island pillar 33 1 respectively have different electrical properties, in other words, there is a potential difference between the metal sidewall 332 and the metal island pillar 33 1 . For example, the metal sidewalls 3 32 may correspond to a positive potential 'and the metal island pillars 33 对应 correspond to opposite negative potentials, such that the metal sidewalls 332 and the metal island pillars 33 1 have corresponding capacitance values. Please note that 'the two adjacent capacitor layers are also separated by two dielectric layers by a dielectric; further, as shown in Figures 2 and 3, each capacitor unit 330 contains a plurality of capacitors A via 334. In the present embodiment, the plug 334 is used to connect the two adjacent capacitor layers 310, 320, so that the two ends of the plug 334 are connected to the same T. In the present embodiment, the quino-M, the month, and the third figure, the metal island column 331 has a plug 334, and the metal gamma 332 has a plug 334 disposed on each of its four corners. . Therefore, in the example of the singularity, the metal sidebands u 9 located at different capacitance layers 3 10, 3 2 0 are connected by the plugs 334 located at the four corners, and therefore, different thunderstorms It is considered that the metal sidewalls 332 of the four layers 310 and 320 of the J electric layer have the same electrical properties; on the other hand, the metal island pillars 331 located at different capacitance layers 31〇, 32〇 are located by paying The plugs 3 34 are connected together, and therefore, the metal island pillars 331 located at different capacitances; s : 5In and 噌 jlO' 320 have the same electrical properties. For example, if the metal sidewall 332 corresponds to a positive potential and the metal island pillar 331 corresponds to a negative potential, then in this embodiment, all the metal sidewalls 332 correspond to a positive potential, and all the metal island pillars 33 i are Corresponds to a negative potential. As described above, each capacitor unit 33 can generate a capacitive effect by its internal metal island 331 and metal sidewall 332. Therefore, for the overall capacitor structure 300, the overall capacitance effect corresponds to all. The sum of the capacitive effects produced by the capacitive unit 330. Please note that in the current process technology, the fabrication of the above-mentioned capacitor structure 3〇〇 has been generally carried out using a process of 1 8 micron or less; this means the space between the metal sidewall 332 and the metal island pillar 331 ( The pitch can be made relatively small. As is well known in the art, the smaller the spacing between the metal sidewalls 332 and the metal island pillars 33 1 , the greater the capacitive effect that can be obtained. Therefore, the capacitor structure 300 of the present invention is preferably implemented in a process of 0. 18 microns or less to reinforce the capacitive effect that it can obtain. 10 丄 (4) 4 / 3 In addition, in order to make the metal sidewall 332 (or / and the metal island column 33 1 } have a predetermined potential as just described, in general, the capacitor structure 3 另 further includes at least one power layer (Power The layer is disposed on the semiconductor substrate, and the power layer is connected to the metal sidewall 332 through a plurality of plugs, so that the metal sidewall 332 can provide the conductive wall with a predetermined potential to have a preset Electrical. Please note that since the structure and operation of the power supply layer are well known in the industry, it should be understood by those of ordinary knowledge in this field, so it is not mentioned here. Please refer to Figure 4 here. Figure 5 is a perspective view of a second embodiment of the capacitor structure 400 of the present invention; and Figure 5 is a plan view of a second embodiment of the capacitor structure 400 of the present invention. Similarly, the capacitor structure also has a plurality of capacitors. Layers 410 and 420. Each of the capacitor layers 41A and 420 includes a plurality of capacitor units 43 0. Note that, for the sake of simplicity, Figures 4 to 5 only show a plurality of capacitor units 430. However, the capacitor structure 400 can actually contain more Capacitor unit 430. Please note here that for the sake of simplicity, the semiconductor substrate and isolation layer associated with capacitor structure 400 are not shown in Figures 4 and 5. However, those skilled in the art should understand the semiconductor. The structure and operation of the substrate and the isolation layer are not described here. Note that in the present embodiment, each capacitor unit 430 has the same structure and operation as the capacitor unit 330 described above; for example, a capacitor The unit 43A also includes a metal island 431, a metal sidewall 432, and a dielectric layer 433'. As its structure and operation have been set forth in the foregoing disclosure, it will not be further described herein. 11 1323473 See Figure 4 'Identically' in this embodiment, the two adjacent capacitor layers 410, 420 are also separated by a dielectric material between two adjacent capacitor layers; in addition, as shown in Figures 2 and 3' Each of the capacitor units 43A includes a plurality of vias 434. The plugs 434 are used to connect the two adjacent capacitor layers 410, 420, so that the ends of the plugs 434 are connected to have the same electrical properties. .
此外，請繼續參閱第5圖’金屬島柱4 3 1係具有一插 塞434，而金屬侧壁432則於其四個角落上分別配置有一 插塞434。 在此請注意，本實施例之電容結構4 0 〇與前述的電容 結構300的不同之處在於，電容層410、420的相對位置 與前述的電容層310、320有所不同。如第4圖與第5圖 片所示，於本實施例中，位於電容層41〇的金屬側壁432 係藉由位於四角的插塞434連接至電容層42〇的金屬島柱 431 ’而位於電容層420的金屬側壁432係藉由位於四角 的插塞434連接至電容層41〇的金屬島柱431。 因此，於本實施例中，兩相鄰電容層41〇、42〇的金 屬側壁432係具有不同的電性’而兩相鄰電容層、㈣ 的金屬島柱431亦具有不同的電性，'然而，對於相同電容 層而言’其内部的金屬島柱431與金屬側壁W係分別具 有不同的電性。 因此’對於每一個電容單元43〇來說，由於其内部的 金屬島柱431與金屬侧壁432仍可確保其分別對應不同的 電性，因此彼此之間亦可產生電容效應。而對於不同居的 12 1323473 •金屬側壁432來說，由於兩相鄰電容層410、420的金屬 側壁432係對應不同的電性’因此不同層的金屬側壁432 之間亦有電容效應；相同地，不同層的金屬島柱43 1之間 亦有電容效應。如此一來，便大大增加了整體電容結構400 所能獲得的電容效應。 舉例來說，若於電容層4 1 0中’其内部的金屬侧壁432 係對應正電位，而其内部的金屬島柱43 1則對應負電位， 那麼，於本實施例中，電容層420的金屬側壁432皆對應 負電位’並且電容層420的金屬島柱43 1皆對應正電位。 如前所述’每一個電容單元430皆可藉由其内部的金屬島 柱431與金屬侧壁432而產生一電容效應，而不同電容層 410、420的金屬侧壁432或金屬島柱431亦可產生另一電 容效應，因此’對於整體電容結構400來說，其整體的電 容效應不僅具有全部電容單元330所產生之電容效應的總 和’亦具有不同電容層410、420的金屬側壁432或金屬 島柱43 1所產生知電容效應的總和。 相同地’為了使金屬側壁432及金屬島柱431)具有如 前述之預定電位，一般來說，電容結構4〇〇係另包含有至 少一電源層（P〇wer Layer )’位於該半導體基板之上，該 電源層可透過複數個插塞，連接至金屬側壁432，如此一 來’金屬側壁432便可提供該導電壁一預設電位，使其具 有預设的電性。在此請注意，由於電源層的結構與操作已 為業界所熟知，揭露至此’此領域具有通常知識者應可理 解’故不另贅述於此。 13 1323473 . 此外，本發明之第二實施例之電容結構400較佳地以 • 〇.1 8微米以下的製程實作之，以降低電容結構中各元件的 間距（pitch)，以增強電容結構4〇〇整體可獲得的電容效應。 在此請注意，為了簡化起見，於前面的揭露之中，電 容結構300、400係包含兩個電容層，然而，在實際應用 上，電容結構實可根據設計者的需求，而相對應地具有更 夕或疋更少的電谷層；舉例來說，由於單一個電容單元 330、430便已具有相對應的電容效應，因此若單一個電容 層中，已經具有數量足以產生足夠電容值的電容單元，那 麼電容結構便只須一個電容層即可實施；另—方面，電容 結構亦可根據設計者的需束， 古 β J而水而具有更多電容層，以進而 得到更大的電容值，如此的相對應變化，亦屬本發明的範 此咕庄忍，本發明並未限制金屬島柱與金屬側壁的 =大亦並未限制插塞的位置與數量。雖 =揭路之中’金屬側壁係為—四方形的側壁1而，這樣 乃之實刼例，而非本發明的限制。 由於在實際的製程中，6 从 ψ 几全四方形的側壁並不容易實 作，因此，如第2〜5圖所示，么屈ώ ’、 金屬島柱在四角上可且有一 些誤差，而無須為完全的四方 了八有 可依照製作時的簡單程度 …更 系一卞而芰化，而不以四方形為限。 近-個插塞大小，然而，這様二*屬島柱的尺寸則接 容易f竹.m 樣的尺寸在實際的製程中亦不 谷易貫作，因此，亦可將金 、，屬島柱的尺寸加大，以方便實 14 1323473 作’在此請參閱第6圖，第6圖為本發明電容結構 第三實施例的立體圖。如第6圖所示，於電容結構_ 每一金屬島柱631的尺寸皆已加大為壁狀結構，以方 作，而其上亦建構有複數個插塞634，來確保其電性盘抓 計時的狀電性相符；#此的相對應變化，亦 2 明的精神❶ 咬牙不知 此外，在實際應用上，金屬侧壁亦可具有更多/更小 插塞；舉例來說，若金屬側壁具有更大的尺寸，如第：圖 所π I屬側壁632的尺寸亦較前述的實施例為大，因二 金層側壁632上亦可配置更多的插塞㈣。如此一來，金 屬侧壁與金屬島柱皆可藉由更多的插塞，來確保其電性斑 設料的狀電性相符，以確保彼此之間能夠確實的產^ 電容效應；如此的相對應變化，亦屬本發明的範疇。 在此請注意，雖然於前面的揭露之中，金屬島柱盘金 屬側壁皆由金屬所構成；然而，這樣的作法僅為本發明之 實施例，而非本發明的限制。於實際應用上，金屬島柱 與金屬側壁可由其他的導電材料製作之，如此的相對應變 化’亦屬本發明的範疇。 相較於習知技術，本發明提出了另一種電容結構，以 於更小的晶片區域中取得更佳的電容值，如此一來，本發 明便可於有限的晶片區域中，建置電路設計者所須的電 容。 以上雖以實施例說明本發明，但並不因此限定本發明 之範圍，只要不脫離本發明之要旨，該行業者可進行各種 15 1323473 .* 變形或變更。 , 【圖式簡單說明】 第1圖為一習知電容結構的立體圖。 第2圖為本發明電容結構之第一實施例的立體圖。 .- 第3圖為本發明電容結構之第一實施例的俯視圖。 . 第4圖為本發明電容結構之第二實施例的立體圖。 第5圖為本發明電容結構之第二實施例的俯視圖。 # 第6圖為本發明電容結構之第三實施例的立體圖。 圖式編號 100、300、400、600 電容結構 310 、 320 、 410 330 ' 430 ' 630 331 ' 431 ' 631 332 ' 432 > 632 φ 333 、 433 、 633 334 ' 434 ' 634 420、610、620 電容層 電容單元 金屬島柱 金屬側壁 介電層 插塞In addition, please continue to refer to Fig. 5, the metal island column 4 3 1 has a plug 434, and the metal sidewall 432 is respectively provided with a plug 434 at its four corners. It should be noted here that the capacitor structure 40 本 of the present embodiment is different from the capacitor structure 300 described above in that the relative positions of the capacitor layers 410 and 420 are different from those of the capacitor layers 310 and 320 described above. As shown in FIG. 4 and FIG. 5, in the present embodiment, the metal sidewall 432 located on the capacitor layer 41 is connected to the metal island pillar 431' of the capacitor layer 42 by a plug 434 located at four corners. The metal sidewalls 432 of the layer 420 are connected to the metal island pillars 431 of the capacitor layer 41 by plugs 434 located at the four corners. Therefore, in this embodiment, the metal sidewalls 432 of the two adjacent capacitor layers 41〇, 42〇 have different electrical characteristics, and the two adjacent capacitor layers and the metal island pillars 431 of (4) also have different electrical properties, However, for the same capacitive layer, the inner metal island 431 and the metal sidewall W have different electrical properties. Therefore, for each of the capacitor units 43A, since the metal island pillars 431 and the metal sidewalls 432 therein can ensure that they respectively correspond to different electrical properties, a capacitance effect can also be generated between them. For different residential 12 1323473 • metal sidewalls 432, since the metal sidewalls 432 of the two adjacent capacitor layers 410, 420 correspond to different electrical properties, there is also a capacitive effect between the metal sidewalls 432 of different layers; There is also a capacitive effect between the metal island pillars 43 1 of different layers. As a result, the capacitive effect that the overall capacitive structure 400 can achieve is greatly increased. For example, if the metal sidewall 432 in the capacitor layer 4 10 corresponds to a positive potential and the metal island column 43 1 in the capacitor layer corresponds to a negative potential, then in the embodiment, the capacitor layer 420 The metal sidewalls 432 all correspond to a negative potential 'and the metal islands 43 1 of the capacitor layer 420 all correspond to a positive potential. As described above, each capacitor unit 430 can generate a capacitive effect by its internal metal island 431 and metal sidewall 432, and the metal sidewall 432 or metal island 431 of the different capacitor layers 410, 420 are also Another capacitive effect can be created, so that for the overall capacitive structure 400, its overall capacitive effect not only has the sum of the capacitive effects produced by all of the capacitive units 330, but also has the metal sidewalls 432 or metal of the different capacitive layers 410, 420. The sum of the known capacitive effects produced by the island column 43 1 . Similarly, in order to have the metal sidewall 432 and the metal island pillar 431 have a predetermined potential as described above, generally, the capacitor structure 4 further includes at least one power layer (P〇wer Layer) located on the semiconductor substrate. The power layer can be connected to the metal sidewall 432 through a plurality of plugs, so that the metal sidewall 432 can provide the conductive wall with a predetermined potential to have a predetermined electrical property. Please note that since the structure and operation of the power supply layer are well known in the art, it should be understood that those skilled in the art should understand this and will not be further described herein. 13 1323473. Further, the capacitor structure 400 of the second embodiment of the present invention is preferably implemented in a process of less than 1.8 μm to reduce the pitch of each component in the capacitor structure to enhance the capacitance structure. 4〇〇 The overall capacitive effect available. Please note that for the sake of simplicity, in the foregoing disclosure, the capacitor structures 300, 400 comprise two capacitor layers. However, in practical applications, the capacitor structure can be adapted to the designer's needs. If there is a corresponding capacitive effect, for example, since a single capacitor unit 330, 430 already has a corresponding capacitive effect, if there is already a sufficient amount of capacitance in a single capacitor layer. Capacitor unit, then the capacitor structure can be implemented with only one capacitor layer; on the other hand, the capacitor structure can also have more capacitor layers according to the designer's needs, and then get a larger capacitance. The value, such a corresponding change, is also the invention of the present invention. The invention does not limit the size of the metal island column and the metal sidewall and does not limit the position and number of the plug. Although the metal side wall in the road is a square side wall 1, this is an example, not a limitation of the present invention. Since in the actual process, 6 is not easy to implement from the side walls of the square, as shown in Figures 2 to 5, the metal island column can have some errors at the four corners. There is no need to be a complete square. Eight can be made according to the simplicity of the production... more sturdy, not limited to the square. Near-the size of a plug, however, the size of the *2* island column is easy to connect. The size of the m-like sample is not easy to be used in the actual process. Therefore, gold, and the island column can also be used. The size is increased to facilitate the use of 14 1323473. Here, please refer to FIG. 6, which is a perspective view of a third embodiment of the capacitor structure of the present invention. As shown in Fig. 6, in the capacitor structure _ each metal island column 631 has been enlarged to a wall structure, and a plurality of plugs 634 are also constructed thereon to ensure the electric disk The timing of the timing is consistent; the corresponding change of this is also the spirit of 2, the teeth are not known. In addition, in practical applications, the metal sidewalls can also have more/smaller plugs; for example, if the metal The sidewall has a larger size. For example, the size of the sidewall 632 of the first embodiment is larger than that of the foregoing embodiment, and more plugs (four) may be disposed on the sidewall 632 of the gold layer. In this way, both the metal sidewall and the metal island column can ensure the electrical properties of the electrical spot material by using more plugs to ensure a positive capacitance effect between each other; Corresponding changes are also within the scope of the invention. It should be noted here that although in the foregoing disclosure, the metal island pillar metal sidewalls are composed of metal; however, such an approach is merely an embodiment of the invention and not a limitation of the invention. In practical applications, the metal island pillars and metal sidewalls may be made of other conductive materials, and such relative strain 'is also within the scope of the present invention. Compared with the prior art, the present invention proposes another capacitor structure to obtain a better capacitance value in a smaller wafer area, so that the present invention can construct a circuit design in a limited wafer area. The capacitance required. The present invention has been described above by way of examples, and the scope of the present invention is not limited thereto, and various modifications and changes may be made by those skilled in the art without departing from the scope of the invention. [Simplified description of the drawing] Fig. 1 is a perspective view of a conventional capacitor structure. Fig. 2 is a perspective view showing a first embodiment of the capacitor structure of the present invention. - Figure 3 is a plan view of a first embodiment of the capacitor structure of the present invention. Figure 4 is a perspective view of a second embodiment of the capacitor structure of the present invention. Figure 5 is a plan view of a second embodiment of the capacitor structure of the present invention. #图图图 is a perspective view of a third embodiment of the capacitor structure of the present invention. Schematic number 100, 300, 400, 600 Capacitor structure 310, 320, 410 330 ' 430 ' 630 331 ' 431 ' 631 332 ' 432 > 632 φ 333 , 433 , 633 334 ' 434 ' 634 420 , 610 , 620 Capacitance Layer capacitor unit metal island pillar metal sidewall dielectric layer plug