1321971 九、發明說明： 【發明所屬之技術領域】 更詳而言 質化表面 本發明係有關於一種線路層結構及其製法， 之，係有關於一種電路板之圖案化線路層呈 之結構及其製法。 = 【先前技術】 ^ 為因應電子產品之小型化輕量化及電子元件高集積 ••化之線路容量的使用需求，多層電路板之技術乃應運而 _生’·而多層電路板係採增層（Buildup)的方式製作，係於 一核心材料上以介電層及圖案化線路層交互地形成，且藉 由層間連接（interconnection)技術作電性連接，以連接各^ 之綠技。 s 電路板線路層製程技術中，線路層之信賴度取決於介 電層與圖案化線路層之間的抗撕強度（peel价如州為提 •高抗撕強度’於製程中之線路層必須進行表面粗化處理 # (surface roUghing treatment)，以改變圖案化線路層之表面 粗糙度二如此方可與後續之介電層或防焊層緊密結合。 目前在電路板多採用銅作為圖案化線路層材料，而形 成線路的:^料例如㈣之減成法，或為電鍍之加成 法’而-亥線路之鍍層結晶粒特性與粗化處理後表面粗經度 相關，右因特殊鍍銅條件，將使結晶顆粒的尺寸變異過大， 如此將嚴重影響粗化處理後表面粗糙度之均質化 (homogenized) ’谷易造成線路層與介電層剝離的 現象’進而降低信賴度。 19706 5 1321971 因此，如何設計一種線路層結構與其對應之製程方 法’以達到提高產品信賴度、降低不良率，_為相關領域 上所需迫切面對之課題。 【發明内容】 鑒於上述習知技術之缺點，本發明之目的係在提供一 種線路層結構及其製法，以提高圖案化線路層表面粗糖度 之均質化，具有較佳抗撕強度，避免發生線路層與介電層 剥離的現象，可克服不同電鍍產品因鍍銅條件差異所造^ .粗化處理後抗撕強度不佳的困難，提高產品之信賴度。 、又本發明之再一目的係在提供一種線路層結構及其 衣法可獲传表面具均質化粗化程度之線路層，使製程中 =粗化處理不需針對不同的電鍍條件或電鐘產線作調整， 卑以有效地提升製程效率與品質。 传以：L 它…本發明之線路層結構之製法， :減成法貫施之，其包括:提供-具有底銅層之承載声· =底銅層上依序形成第一電鍍銅層及第二電鑛銅層二 ;;〜電_層表面形成—阻層，且該阻層形成有至少一 之部份表面;移除於該阻層 声，電鍍銅層及其下之第—電鐘銅層與底銅 鍍鋼芦：底覆蓋之第二電鍍銅層及其下之第-電 ===該圖案化線路層表面復進行粗化處理 係較佳於嗲：’且該弟一電鍍鋼層之粗化表面的均質化 '、於該第-電鍍銅層之粗化表面；以及於該承載層及 19706 6 ^^1971 上形成一保護層’且於該保護層形成至少- 開孔以路出部份之該圖案化線路層。 本發明復提供另一線路層結構之製法 施之’其包括：提供一具有底銅層之 σ如貫 表面形成一阻層，且該阻層形成有至少=層 底銅層之部份表面；於該阻層開口區所露出該 ::…一電鍍銅層與第二電錢銅層；#除該阻層及並 伋盍之底銅層’使該ρ、第二電鐘銅層及其下之 :構成一圖案化線路層；該圖案化線路層粗 =具有粗化“，且該第二電鑛銅層之粗化表 貝Ά佳於該第一電鍍銅層之粗化表面；α及於該承載 2㈣案化線路層上形成一保護層，且於該保護層形成 y 一開孔以露出部份之該圖案化線路層。 本發明復提供-種線路層結構，係包括：一承載層. 以及一圖案化線路層，該圖案化線路層具有第一及第：電 鑛銅層’且該第-電鍍銅層係形成於該承載層上，該第二 電鍵銅層係形成於該第一電錢銅層上，其中，該圖案化線 路層復經過粗化處理而具有粗化表面，且該第二電鑛銅層 之粗化表面的均質化係較佳於該第—電鍍銅層之粗化表 面。 ' 構中該圖案化線路層之表面係經過粗化處 理，而具有粗化之表面。 上述之結構中，該承载層係為絕緣板、電路板、核心 板或多層電路板内部之介電層之其中一者。 7 19706 uziy/i 上述之結構復包括一保護層，係形成於該承载層及該 圖案化線路層上’該保護層可為介電層或防焊層，且該保 :護層具有至少-開孔以露出部份之該圖案化線路層，該露 f出之部份係為一接觸墊（丨and)或一電性連接墊（pad)。 因此’本發明之線路層結構及其製法，其圖案化線路 層具有第-及第二電鑛銅層，該圖案化線路層復經過粗化 處理而具有粗化表面，且該第二電錢銅層之粗化表面的均 質化係較佳於該第-電鍍銅層之粗化表面，其具有較佳抗 撕強度，旎避免發生線路層與介電層剝離的現象，俾以提 尚產tm之彳σ賴度，同時可克服不同電鐘產品之鐘銅條件差 異所造成粗化處理後抗撕強度不佳的困難，以有效地提升 製程品質與效率。 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 #瞭解本發明之其他優點與功效。 實施例 請參閱第1A至1H圖，係為本發明之線路層結構以減 成法實施之製法剖視圖。 如第1A圖所示，首先提供一具有底銅層i〇a之承載 層iO’該底銅層l〇a係為銅箔、無電鍍銅及其所組群組之 其中一者；該承載層10可為絕緣板、電路板、核心板或多 層電路板内部之介電層。 如第1B圖所示’於該底鋼層i〇a表面藉由該底銅層 8 19706 1321971 1〇3具有導電之特性’以於該底銅層10a表面形成一第一 電锻銅層11。 ,如第1C圖所不，接著於該第一電鍍銅層11之表面再 形成一第二電鍍銅層12。 如第1D圖所示’於該第二電鍍鋼層12的表面形成一 ^層13’且該阻層13形成有至少—開口區13〇以露出該 第一電鍍銅層12之部份表面。 •。如第1E圖所示，然後以蝕刻方式移除該阻層開口 區130路出之的第二電鍍銅層12及其下之第一電鍵銅層 11與底銅層術，以令為該阻層13所覆蓋之第二電鍛銅層 12及其下之第一電鍍銅層心底銅層…構成一圖案化 線路層H，該圖案化線路層14復包括有電性連接塾_) 或接觸墊（land)141。 如第1F圖所示，移除該阻層13以露出該圖案化線路 ；，且如第1G圖所示，該圖案化線路層14復經過粗化 而具有粗化之表面14_，且該第二電鍍銅層之 12粗化表面i4〇b的均質化俜軔祛於 粗化表面刚ae 匕Μ佳於該第-電鍵銅層Μ Γ圖所示，最後於該承載層1〇及圖案化線路層 14表面形成—保護層15，該保護層15可為介電層或防焊 層’且該保護層15形成有開孔15G以露出部份之圖荦化線 _ ’該露出之部份係為電性連接塾(叫或接觸墊 (land)141。 第二實施例 19706 1321971 °月參閱第2A至2G圖，係為本發明之線路層結構以加 成法實施之製法另一實施例。 如第2A圖所示，提供一具有底銅層1〇a之承載層1〇。 如第2B圖所示，於該底銅層i〇a表面形成一阻層 且該阻層13形成有至少一開口區以露出該底銅層l〇a 之部份表面。 _如第2C圖所示，於該阻層13開口區130所露出之底 鋼層10a表面形成第一電鍍銅層u。 —如第2D圖所示，於該阻層13開口區13〇所露出之的 第一電鍍銅層11表面形成第二電鍍銅層12。 如第2E圖所示，移除該阻層13及其所覆蓋之底銅層 Wa’使該第一電鍍銅層u、第二電鍍銅層12及底銅層 構成圖案化線路層14，且該圖案化線路層14復包括有電 性連接墊（pad)或接觸墊（land)141;且如第2F圖所示該 圖案化線路層14復經過粗化處理，而具有粗化之表面 — a’UOb，且該第二電鑛銅層之12粗化表面鳩的均質 化係較佳於該第一電鍍銅層u之粗化表面u〇a。 如第2G圖所示，於該承載層1〇及圖案化線路層μ 上形成一覆蓋保護層15,該保護層15可例如為介電層或 防焊層，且該保護層15形成有開孔15〇以露出部份之^玄一圖 案化線路層14，該露出之部份係為電性連接塾（⑽）或接觸 墊（land)141。 ’ 本發明復提供一種線路層結構 圖，係包括：一承載層1〇;以及一 ’請參考第1G或2F 圖案化線路層14，該1321971 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit layer structure and a method of fabricating the same, relating to a patterned circuit layer of a circuit board and a structure thereof System of law. = [Prior Art] ^ In response to the demand for the miniaturization and weight reduction of electronic products and the high capacity of electronic components, the technology of multi-layer circuit boards is expected to be used. The method of (Buildup) is formed on a core material by a dielectric layer and a patterned circuit layer, and is electrically connected by an interlayer connection technology to connect the green technologies. s circuit board circuit layer process technology, the reliability of the circuit layer depends on the tear strength between the dielectric layer and the patterned circuit layer (peel price such as the state for the high tear strength) in the process of the circuit layer must Surface roughening treatment # (surface roUghing treatment) to change the surface roughness of the patterned circuit layer 2 so as to be closely combined with the subsequent dielectric layer or solder resist layer. Currently, copper is used as a patterned circuit on the circuit board. The material of the layer is formed by the subtraction method of (4), or the addition method for electroplating. The characteristics of the coating crystal grain of the -H line are related to the surface longitude after the roughening treatment, and the right is due to the special copper plating condition. This will cause the size variation of the crystal particles to be too large, which will seriously affect the homogenization of the surface roughness after the roughening treatment, and the phenomenon that the valley layer and the dielectric layer are peeled off, thereby reducing the reliability. 19706 5 1321971 Therefore How to design a circuit layer structure and its corresponding process method to achieve product reliability and reduce non-performing rate, _ is an urgent problem in related fields. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the object of the present invention is to provide a circuit layer structure and a manufacturing method thereof for improving the homogenization of the rough sugar content on the surface of the patterned circuit layer, having better tear strength and avoiding the occurrence of lines. The phenomenon of peeling off the layer and the dielectric layer can overcome the difficulty of the poor corrosion resistance of the different plating products due to the difference in copper plating conditions, and improve the reliability of the product. Moreover, another object of the present invention is Providing a circuit layer structure and a clothing layer thereof can obtain a circuit layer having a degree of homogenization and coarsening of the surface, so that the process of the roughening process does not need to be adjusted for different plating conditions or electric clock production lines, and is effective Improve process efficiency and quality. Pass: L It... The method of fabricating the circuit layer structure of the present invention: the subtractive method is applied, which comprises: providing - bearing sound with a bottom copper layer · sequentially forming on the bottom copper layer a first electroplated copper layer and a second electro-copper layer 2; a layer formed on the surface of the layer, and the resist layer is formed with at least a portion of the surface; the layer is removed from the layer, and the copper layer is plated and The next - the electric clock copper layer and Copper-plated steel reed: the second electroplated copper layer covered by the bottom and the first electro-deposited === the roughening treatment of the surface of the patterned circuit layer is better than: 'and the thickness of the electroplated steel layer Homogenization of the surface, the roughened surface of the first electroplated copper layer; and forming a protective layer on the carrier layer and 19706 6 ^ 1971 and forming at least - opening to the protective layer The patterned circuit layer is provided. The invention provides a method for fabricating another circuit layer structure, which comprises: providing a σ-like surface having a bottom copper layer to form a resist layer, and the resist layer is formed with at least a layer a portion of the surface of the bottom copper layer; exposed in the open area of the resist layer:: an electroplated copper layer and a second electric copper layer; #excluding the resist layer and the bottom copper layer of the crucible a second electric clock copper layer and a lower layer thereof: forming a patterned circuit layer; the patterned circuit layer is thick=having roughening, and the roughened surface of the second electric ore copper layer is better than the first plating a roughened surface of the copper layer; a and a protective layer formed on the carrier 2 (4) circuit layer, and a y opening is formed in the protective layer to expose Portion of the patterned circuit layer. The present invention provides a circuit layer structure comprising: a carrier layer; and a patterned circuit layer having a first and a first: an electro-copper layer ' and the first electroplated copper layer is formed on The second electric bond copper layer is formed on the first electric copper layer on the carrier layer, wherein the patterned circuit layer is roughened to have a roughened surface, and the second electric copper layer is The homogenization of the roughened surface is preferably a roughened surface of the first electroplated copper layer. The surface of the patterned wiring layer is subjected to roughening treatment to have a roughened surface. In the above structure, the carrier layer is one of an insulating board, a circuit board, a core board or a dielectric layer inside the multilayer circuit board. 7 19706 uziy/i The above structure comprises a protective layer formed on the carrier layer and the patterned circuit layer. The protective layer may be a dielectric layer or a solder resist layer, and the protective layer has at least - The hole is opened to expose a portion of the patterned circuit layer, and the exposed portion is a contact pad or an electrical connection pad. Therefore, the circuit layer structure of the present invention and the method of manufacturing the same, the patterned circuit layer having the first and second electro-mineralized copper layers, the patterned circuit layer being roughened to have a roughened surface, and the second electric money The homogenization of the roughened surface of the copper layer is preferably performed on the roughened surface of the first electroplated copper layer, which has better tear strength, and avoids the phenomenon that the wiring layer and the dielectric layer are peeled off. The 彳 赖 赖 t of tm can overcome the difficulty of poor tear strength after roughening treatment caused by the difference of bell copper conditions of different electric clock products, so as to effectively improve the process quality and efficiency. [Embodiment] The embodiments of the present invention are described by way of specific examples, and those skilled in the art can easily understand the other advantages and effects of the present invention from the disclosure of the present specification. Embodiments Referring to Figures 1A to 1H, there is shown a cross-sectional view of a circuit board structure of the present invention which is implemented by a subtractive method. As shown in FIG. 1A, a carrier layer iO' having a bottom copper layer i〇a is first provided, wherein the bottom copper layer 10a is one of copper foil, electroless copper, and a group thereof; Layer 10 can be an insulating layer, a circuit board, a core board, or a dielectric layer within a multilayer circuit board. As shown in FIG. 1B, 'the surface of the bottom steel layer i〇a has a conductive property by the bottom copper layer 8 19706 1321971 1〇3' to form a first electric forged copper layer 11 on the surface of the bottom copper layer 10a. . As shown in FIG. 1C, a second electroplated copper layer 12 is further formed on the surface of the first electroplated copper layer 11. As shown in Fig. 1D, a layer 13' is formed on the surface of the second plated steel layer 12 and the resist layer 13 is formed with at least an opening region 13a to expose a portion of the surface of the first plated copper layer 12. •. As shown in FIG. 1E, the second electroplated copper layer 12 and the underlying first copper bond layer 11 and the underlying copper layer of the barrier opening region 130 are removed by etching to make the resistor The second electric forging copper layer 12 covered by the layer 13 and the first electroplated copper layer under the copper layer ... constitute a patterned circuit layer H, the patterned circuit layer 14 further comprising an electrical connection 塾 _ _ or contact Land 141. As shown in FIG. 1F, the resist layer 13 is removed to expose the patterned line; and as shown in FIG. 1G, the patterned circuit layer 14 is roughened to have a roughened surface 14_, and the first The homogenization of the roughened surface i4〇b of the second electroplated copper layer is as follows: the roughened surface is just ae 匕Μ better than the first-key copper layer Μ Γ, and finally the layer is patterned and patterned. The surface of the circuit layer 14 is formed as a protective layer 15, which may be a dielectric layer or a solder resist layer 'and the protective layer 15 is formed with an opening 15G to expose a portion of the patterned line _ 'the exposed portion It is an electrical connection 塾 (called or contact land 141. The second embodiment 19706 1321971 1971 refers to the 2A to 2G drawings, which is a method for the implementation of the circuit layer structure of the present invention by an additive method. As shown in FIG. 2A, a carrier layer 1 having a bottom copper layer 1A is provided. As shown in FIG. 2B, a resist layer is formed on the surface of the bottom copper layer i〇a and the resist layer 13 is formed. At least one opening region to expose a portion of the surface of the bottom copper layer 10a. _ As shown in FIG. 2C, the surface of the bottom steel layer 10a exposed in the open region 130 of the resist layer 13 Forming a first electroplated copper layer u. - As shown in Fig. 2D, a second electroplated copper layer 12 is formed on the surface of the first electroplated copper layer 11 exposed in the open region 13 of the resist layer 13. As shown in Fig. 2E Removing the resist layer 13 and the underlying copper layer Wa' thereof to form the first electroplated copper layer u, the second electroplated copper layer 12 and the bottom copper layer to form the patterned wiring layer 14, and the patterned circuit layer 14 Including an electrical connection pad or land 141; and as shown in FIG. 2F, the patterned circuit layer 14 is subjected to roughening treatment to have a roughened surface - a'UOb, and The homogenization of the roughened surface 鸠 of the second electrowinning copper layer is preferably performed on the roughened surface u〇a of the first electroplated copper layer u. As shown in Fig. 2G, the carrier layer is patterned and patterned. A cover protective layer 15 is formed on the circuit layer μ, and the protective layer 15 can be, for example, a dielectric layer or a solder resist layer, and the protective layer 15 is formed with an opening 15 露出 to expose a portion of the patterned circuit layer 14 The exposed portion is an electrical connection port ((10)) or a contact pad (land) 141. The present invention provides a circuit layer structure diagram including: a carrier layer 1〇 And a reference to the 1G or 2F patterned circuit layer 14, which
19706 10 1321971 案化線路層14具有第一電链 卜 又j增11及第二電鍍銅層12， 且該弟-錢銅層u係係形成於該承载層iQ表面 二電錢銅層12係形成於該第-電錄銅層u上，盆中：二 圖案化線路層14復經過粗化處理，而具有粗化之表面“ 14〇Μ桃，且該第二電錢鋼層之12粗化表面渴的均質 化係軚佳於該第-電鍍鋼層u之粗化表面i術。 上述之結構，復包括—底銅層1〇a ’係形成於該承載 層！〇與該第-電義層U之間，該底銅層^係為銅箱、 無電鍍銅及其所組群組之其中一者。 上述之結構復包括-保護層15，係形成於該承載芦 及該圖案化線路層14上，該保護層15可為介電層或曰防 焊層，且該保護層15具有至少—開孔⑼以露出部份之該 圖案化線路層14’該露出之部份係為—接觸她叫或: 電性連接墊（pad)。 因此’本發明之線路層結構及其製法中，得於形成線 _路之減成法或加成法中，其圖案化線路層14具有第 銅層η及第二電鍍鋼層12，該圖案化線路層14復經過粗又 化處理而具有粗化表面i術，i她，且該第二電鍍銅層u 之粗化表面140b的均質化係較佳於該第—電軸層^之 粗化表面14〇a，使該圖案化線路層Μ與形成於A表面之 保護層B有較佳的結合性以避免產生剝離，如此可提高產 品之信賴度；又由此發明方法亦可使製程中之粗化處理不 需針對不同的電鍍條件或f鍍產線作㈣，進 升製程效率與品p 19706 11 上述實施例僅為例示性說明本發明 效，而非用於限制本發明。任何孰習之原理及其功 力π、土北丄竹 ’‘，、白此項技藝之人士均可 在不延背本發明之精神及範疇下，f 與變化。因此，本發明之權利保護』=施例進行修飾 專利範®所列。 ’應如後述之申請 【圖式簡單說明】 〃第.1A至1H圖係顯示本發明之線路層結構及其製法之 籲弟一貫施例製法剖面示意圖；以及 第2A至2G圖係顯示本發明之線路層結構及其製法之 第二實施例製法剖面示意圖。 【主要元件符號說明】 10 承載層 1〇a 底鋼層 11 12 ·13 130,150 第一電鍍銅層 第二電鍍銅層 阻層 開孔 14 圖案化線路層 〇a 第電錢銅層之粗化表面 140b第一電鑛銅層之粗化表面 141 。卩份圖案化線路層 15 保護層 12 1970619706 10 1321971 The circuitized circuit layer 14 has a first electrical chain and a second electroplated copper layer 12, and the dian-money copper layer is formed on the surface of the carrier layer iQ Formed on the first electro-recording copper layer u, in the basin: the two patterned circuit layer 14 is subjected to roughening treatment, and has a roughened surface "14〇Μ peach, and the second electric money steel layer is 12 thick The surface homogenization system is better than the roughened surface of the first electroplated steel layer u. The above structure includes a bottom copper layer 1〇a ' formed on the bearing layer! Between the electrical layer U, the bottom copper layer is one of a copper box, an electroless copper, and a group thereof. The above structure includes a protective layer 15 formed on the bearing reed and the pattern. On the circuit layer 14, the protective layer 15 may be a dielectric layer or a solder resist layer, and the protective layer 15 has at least an opening (9) to expose a portion of the patterned circuit layer 14'. In order to contact her or: an electrical connection pad (pad). Therefore, the circuit layer structure of the present invention and its manufacturing method can be used to form a line-path subtraction method or addition method. The patterned circuit layer 14 has a second copper layer η and a second galvanized steel layer 12, and the patterned circuit layer 14 is roughened and reprocessed to have a roughened surface, i, and the second electroplated copper layer The homogenization of the roughened surface 140b is preferably performed on the roughened surface 14〇a of the first electric axis layer, so that the patterned circuit layer has a better bonding property with the protective layer B formed on the surface A. In order to avoid the occurrence of peeling, the reliability of the product can be improved; and the invention method can also make the roughening process in the process do not need to be made for different plating conditions or f plating production line (4), and the process efficiency and product p 19706 The above-mentioned embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention. Any of the principles of the abuse and its skill π, the native of the earth, and the skill of the white can be extended. In the spirit and scope of the present invention, f and changes. Therefore, the protection of the present invention is as follows: the application is modified as described in the Patent Model®. 'The application should be as described later [Simple description of the drawing] 〃第1A to 1H The figure shows the structure of the circuit layer of the present invention and the method of its production FIG. 2A to FIG. 2G are schematic cross-sectional views showing the structure of the circuit layer of the present invention and the second embodiment of the method for manufacturing the same. [Main component symbol description] 10 carrier layer 1〇a bottom steel layer 11 12 ·13 130,150 first electroplated copper layer second electroplated copper layer resistive opening 14 patterned circuit layer 〇a roughened surface of the first electric copper layer 140b roughened surface of the first electrowinning copper layer 141. 图案 patterned circuit layer 15 protective layer 12 19706