15391pif.doc 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種脈衝式正反器(f|ip_fl〇pS)。 【先前技術】 正反器及閂鎖器（latches)可用在半導體積體電路中， 當成資料儲存裝置使用。正反器可用來取樣(sample)—輸 入訊號’並且再根據一時脈訊號(clock signal)，將輸入訊 波轉換成一輸出訊號。閂鎖器與正反器的不同點是在其訊 號處理的部分’閂鎖器可連續取樣一輸入訊號’並且再根 據其可接收的時脈脈衝(d〇ckpulse)，將輸入訊號轉換成一 輸出訊號。 .圖1係繪示一個習知的脈衝式正反器的方塊圖。脈衝 式正反器100可包括一個閂鎖器u〇，其係架構成響應一 脈衝產生器120所產生的一第一時脈脈衝訊號〜φ及一第二 時脈脈衝訊號Φ，將輸入資料DIN，轉換成輸出資料 D〇UT °因為脈衝式正反器1〇〇可用與一主僕式 (paster-slave)正反器不同的單一閂鎖器，所以脈衝式正反 益100可具理想操作速度與功率消耗特性。其中，主僕式 正反器可由兩個閂鎖器，也就是一個主閂鎖器latch) 與一個僕閂鎖器（slave latch)所組成，且每一閂鎖器都可由 至少四個邏輯閘（gates)所組成。 °月參考圖2所示’脈衝式正反器100的脈衝產生器120 可包括二個互相串聯的反相器（inverters)122、124、以及 126。其中’第一反相器122接收一個時脈訊號cL〇CK， 15391pif.doc NAND閘128接收時脈訊號CL〇CK及第三反相器12 一個輸出城，並且輸出-㈣—時脈脈衝訊 ^相器m接收NAND閘128的輸出訊號，並且輸出一個 f-時脈脈衝訊號Φ ϋ，第―、第二、以及第三反相 器122、124、以及126的延遲時間，可決定第一及第二 脈脈衝訊號〜φ及φ的脈衝寬度。 、 然而，因為脈衝產生器可由多於四個的問極所組成， 所以相較於用在正反器的習知閂鎖器而言，脈衝產生器 120會佔用較大的晶片面積’並且消耗較高的功率。當^ 衝式正反器係用於高速操作和/或低功率消耗的電路時，這 種高功率消耗和/或佔用較大晶片面積的特性就會成為問 題0 【發明内容】 抑▲有鑑於此，本發明較佳實施例提供一種脈衝式正反 。器，該脈衝式正反器係包括一個脈衝產生器和/或一個閂鎖 器，且該閂鎖器係由較習知脈衝產生器更低個數的閘極所 組成。 根據本發明一較佳實施例，該脈衝式正反器係包括： -，問鎖器’響應—第—時脈脈衝訊號及—第二時脈脈衝 訊號，閂鎖—資料輸入訊號；以及一個脈衝產生器，用來 接收用於產生第一時脈脈衝訊號及第二時脈脈衝訊號的— 時脈訊號。 根據本發明一實施例，一脈衝產生器係包括：一個 NAND閘，用來接收一時脈訊號與一可變延遲電路的輪 15391pif.doc 出，並且輸出—第—時脈脈衝訊號；-個第-反相器，用 來接收NAND間的輸出，並且輸出一第二時脈脈衝訊號； -個可變延遲電路’用來接收時脈訊號與第—反相器的輸 出，並且將一輸出訊號，輸入至ΝΑΝΟ閘；一個第二反相 器，用來接收可變延遲電路的輸出；以及一個NM〇s電晶 體’其係祕在可變輯電路的輸丨與—躺雜(以〇_ voltage)之間，且其一閘極係連接至第二反相器的一輸出。 根據本發明另一實施例，一脈衝產生器係包括：一個 NAND閘，用來接收一時脈訊號與一可變延遲電路的輸 出，並且輸出一第一時脈脈衝訊號；一個第一反相器，用 來接收NAND閘的輸出，並且輸出—第二時脈脈衝訊號； 一個可變延遲電路，用來接收時脈訊號與第一反相器的輸 出，並且將一輸出訊號，輸入至NAND閘；一個第二反相 器’用來接收可變延遲電路的輸出；以及一個第— NM〇s 電晶體，其一汲極(drain)係連接至可變延遲電路的輸出， 其一閘極(gate)係接收一時脈訊號；以及一個第二nm〇S 電晶體，其一汲極係連接至第一 NM0S電晶體的一源極 (source)，其一閘極係連接至第二反相器的輸出，而且其一 源極係連接至一接地電壓。 根據本發明另一實施例，一脈衝產生器係包括：一個 NAND閘，用來接收一時脈訊號、一個致能訊號(enable signal)、以及一可變延遲電路的輸出，並且輸出一第一時 脈脈衝訊號；一個第一反相器，用來接收NAND閘的輸 出，並且輸出一苐二時脈脈衝訊號；一個可變延遲電路， 1321902 15391pif.doc 用來接收時脈訊號與第 號，輸入至NAND閘； 卜 H竹一莉ί出訊 第一反相器，用來接收可變延 遲電路的輸出；以及一個NM0S電晶體 至可變延遲電路的輪出，其i極係連接至—接地電^接 而且其一閘極係連接至第二反相器的輸出。 根據本發㈣-實關_產生器係包括：一個 NAND閘，用來接收—時脈訊號、—個致能訊號、 =延遲電路的輸出，並且輸出―第—時脈脈衝訊號；一 個弟-反相器，用來接收NAN㈣的輸出，並且輸出15391pif.doc IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a pulsed flip-flop (f|ip_fl〇pS). [Prior Art] The flip-flops and latches can be used in a semiconductor integrated circuit as a data storage device. The flip-flop can be used to sample-input the signal' and convert the input signal into an output signal based on a clock signal. The difference between the latch and the flip-flop is that in the signal processing part, the latch can continuously sample an input signal and convert the input signal into an output according to the receivable clock pulse (d〇ckpulse). Signal. Figure 1 is a block diagram showing a conventional pulsed flip-flop. The pulsed flip-flop 100 can include a latch 〇 构成 constituting a first clock pulse signal φ φ and a second clock pulse signal Φ generated by the pulse generator 120 to input data. DIN, converted to output data D〇UT ° Because the pulsed flip-flop 1〇〇 can use a single latch different from a master-slave flip-flop, so the pulse positive and negative benefits 100 can be ideal Operating speed and power consumption characteristics. Wherein, the master servant flip-flop can be composed of two latches, that is, a master latch, and a slave latch, and each latch can be configured by at least four logic gates. (gates) is composed of. The pulse generator 120 of the 'pulse type flip-flop 100 shown in Fig. 2 may include two inverters 122, 124, and 126 connected in series with each other. Wherein the 'first inverter 122 receives a clock signal cL〇CK, 15391pif.doc NAND gate 128 receives the clock signal CL〇CK and the third inverter 12 an output city, and outputs - (four) - clock pulse signal The phase detector m receives the output signal of the NAND gate 128 and outputs an f-clock pulse signal Φ ϋ, and the delay times of the first, second, and third inverters 122, 124, and 126 may determine the first And the pulse width of the second pulse signal ~φ and φ. However, since the pulse generator can be composed of more than four poles, the pulse generator 120 takes up a larger wafer area than the conventional latch used in the flip-flop and consumes Higher power. When a high-voltage operation and/or a low-power consumption circuit is used for a high-speed operation and/or a low power consumption circuit, such a high power consumption and/or a large wafer area may become a problem. [Inventive content] Thus, a preferred embodiment of the present invention provides a pulsed positive and negative. The pulsed flip-flop includes a pulse generator and/or a latch, and the latch is comprised of a lower number of gates than conventional pulse generators. According to a preferred embodiment of the present invention, the pulsed flip-flop includes: - a locker's response - a - pulse pulse signal and a second clock pulse signal, a latch - a data input signal; and a a pulse generator for receiving a clock signal for generating a first clock pulse signal and a second clock pulse signal. According to an embodiment of the invention, a pulse generator includes: a NAND gate for receiving a clock signal and a variable delay circuit wheel 15391pif.doc, and outputting a -th clock pulse signal; An inverter for receiving an output between the NAND and outputting a second clock pulse signal; a variable delay circuit for receiving the output of the clock signal and the first inverter, and an output signal , input to the gate; a second inverter for receiving the output of the variable delay circuit; and an NM〇s transistor 'the secret of the circuit in the variable circuit - Between the voltages, and one of the gates is connected to an output of the second inverter. According to another embodiment of the present invention, a pulse generator includes: a NAND gate for receiving an output of a clock signal and a variable delay circuit, and outputting a first clock pulse signal; a first inverter For receiving the output of the NAND gate, and outputting a second clock pulse signal; a variable delay circuit for receiving the clock signal and the output of the first inverter, and inputting an output signal to the NAND gate a second inverter 'for receiving the output of the variable delay circuit; and a first - NM〇s transistor having a drain connected to the output of the variable delay circuit and having a gate ( a gate receiving a clock signal; and a second nm 〇S transistor having a drain connected to a source of the first NMOS transistor and a gate connected to the second inverter The output is connected to a ground voltage. According to another embodiment of the present invention, a pulse generator includes: a NAND gate for receiving a clock signal, an enable signal, and an output of a variable delay circuit, and outputting a first time Pulse signal; a first inverter for receiving the output of the NAND gate and outputting a pulse signal of a clock; a variable delay circuit, 1321902 15391pif.doc for receiving the clock signal and the number, input To NAND gate; Bu Hzhu Yili ί signal first inverter for receiving the output of the variable delay circuit; and an NM0S transistor to the variable delay circuit, the i-pole is connected to - ground The gate is connected and its gate is connected to the output of the second inverter. According to the present invention, the NAND gate includes: a NAND gate for receiving the output of the clock signal, the enable signal, the delay circuit, and the output of the -th clock pulse signal; Inverter for receiving the output of NAN (four) and output
一個可變延遲電路，用來接收時脈訊號 二第二 輸出’並且將一輸出訊號，輸入至NAND 3 -個弟二反相器，用來接收可變延遲電路的輸出；以 ^一個第—NM〇S電晶體，其—祕係連接至可變延遲電 路的輸出’且其1極係接收時脈訊號；以及=電 體’其一及極係連接至第-胸os電晶體 f極’其—閘極係連接至第二反相器的輸出，而且其一源 極係連接至一接地電壓。 ’、 根據本發明另一實施例，一脈衝產生器係包括：一個 、〇=’用來接收-時脈訊號與—可變延遲電路的輸出， 亚且輸出一第一時脈脈衝訊號；-個第-反相器，用來接 =〇R _輸出’並且輸出—第二時脈脈衝訊號；一個 :交延遲電路’用來接收時脈訊號與第—反相器的輸出， 並且將-輸出訊號，輸人至似·閘；—個第二反相器， 用來接收可變延遲電路的輸出；以及—個刚⑽電晶體， 1321902 15391pif.doc 其一汲極係接收可變延遲電路的輸出，其一源極係接收一 電源供應電壓’以及其一閘極係接收第二反相器的輸出。 根據本發明另一實施例，一脈衝產生器係包括：—個 NOR閘，用來接收一時脈訊號與一可變延遲電路的輸出， 並且輸出一第一時脈脈衝訊號；一個第一反相器，用來接 收NOR閘的輸出，並且輸出一第二時脈脈衝訊號；一個 可變延遲電路，用來接收時脈訊號與第一反相器的輸出， 並且將一輸出訊说，輸入至NAND閘；一個第二反相芎， 用來接收可變延遲電路的輸出；以及一個第一 pM〇s ^晶 體，其一汲極係連接至可變延遲電路的輸出， 接收時脈訊號;以及-個第二顧電晶體，其一= 連接至第-PMQS電晶體的-祕’其—閘極係連接至第 二反相器的輸出，以及其—源極係連接至—電源供應電壓。 根據本發明另-實施例，一脈衝產生器係包括：一個 NOR閘’用來接收_時脈減、—致能職、以及一 延遲電路的輸出’並且輸出—第—時脈脈衝訊號；一個第 -反相器，用來接收NOR閘的輸出，並且輸出一第二時 脈脈衝=號；-個可變延遲電路，用來接㈣脈訊號與第 -反相is的輸出，並且將—輸出訊號，輸人至财肋間； -個第二反相器，用來接收可變延遲電路的輸出；以及— f P^S電晶體’其—祕係連接至可變延遲電路的輸 出，其-源極係連接至—電源供應電壓，而 連接至第二反相器的輸出。 闸往係 個 根據本發明另-實關，—脈衝產生器係包括：一 15391pif.doc NOR閘，用來接收一時脈訊號、一致能訊號、以及一可 延遲電，的輸出，並且輸出—第—時脈脈衝訊號；一個第 -反相裔’用來接收N0R閘的輸出，並且輸出—第 脈脈衝號；—個可變延遲電路，用來接收時脈訊號與第 -反相㈣輸出’並且將—輸出訊號，輸人至似肋閉； -個第二反相器，用來接收可變延遲電路的輸出；以及— 個第- PMOS電晶體，其一汲極係連接至可變延遲電路的 其一汲極係連接至第一 pM〇s電晶體的 晶 源極，其 輸出，其一閘極係接收時脈訊號；以及一個第二pM〇 θ體*# 、一——…· % -閘極係連接至第二反相器的輸出，以及其—源極係連接 至一電源供應電壓。 相較於習知脈魅生⑽言，_本發明較佳實施例 的脈衝產μ，可賴少錄關絲域正反器電路。 因使用較少個數的閘極，所以可降低其功率消耗與電 佔用的晶片面積。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所關式，作詳細說 明如下》 【實施方式】 圖3係繪示一個根據本發明一較佳實施例的脈衝產生 器的電路圖。脈衝產生器300會響應一個時脈訊號 CLOCK，產生-㈣-時脈脈衝錢〜仪—㈣二時脈脈 衝訊號φ。其中，脈衝產生器300係包括：一個NAND閘 302，用來接收時脈訊號CLOCK與一個可變延遲電路3〇6 1321902 15391pif.doc 的輸出；一個第一反相器304 ’用來接閘3〇2的 輸出；以及一個可變延遲電路306，用來接收時脈訊號 CLOCK與第一反相器304的輸出。NAND閘3〇2的輸出 可變為第-時脈脈衝訊號〜φ，而且第一反相器施的輸 出，可變為第二時脈脈衝訊號φ。 脈衝產生器300可更加包括一個第二反相器3〇7及一 個NMOS電晶體308。其中，第二反相器3〇7係接收可變 ，遲電路306的輸出與第二反相器3〇7的輸出。第二反相 器307的輸出，可施加至NM〇s電晶體3〇8的一個閘極。 NM0S電晶體308的一個汲極，係連接至可變延遲電路3〇6 的輸出，而且NM0S電晶體308的一個源極，係連接至— 接地電壓VSS。藉由第二反相器307及NM0S電晶體308 =共同運作，可避免當時脈訊號CL〇CK為高邏輯位準 h•，可變延遲電路306的輸出變為飄浮不定(fl〇ating)。 脈衝產生斋300可由三個邏輯閘(gates)組成。因此， 可降低組成電路的閘極個數，並且藉此降低其功率消耗和/ 或電路所佔用的晶片面積。 可用多種不同方式實現可變延遲電路3〇6。圖4到圖 係示可邊延遲電路的多個範例。可變延遲電路係 包括.一個輸入端點P，用來接收時脈訊號CL〇CK ; 一個 輸入端點N，絲接收反相器3〇4的輸出；和/或一個輸出 端點OUT。 圖4所不的可變延遲電路3〇6包括一個pM〇s電晶體 402及個NM0S電晶體404，且該兩電晶體係串聯在一 12 15391pif.doc 電源供應電壓VDD與一接地電壓vss之間。其中，pm〇s 電晶體402的一閘極，係當成一輸入端點p，NM〇s電晶 體404的一閘極，可對應於一輸入端點N，而且PMOS電 晶體402的一汲極與NMOS電晶體404的一汲極，係共同 連接至一輸出端點OUT。 圖5所示的可變延遲電路306包括一個pm〇S電晶體 〇2 個弟一 NMOS電晶體504、以及一個第二NM〇S 電晶體506，且該兩NM0S電晶體504及506係串聯在— 電源供應電壓VDD與一接地電壓VSS之間。其中，pm〇s 電晶體502的一閘極，係當成一輸入端點P，第二NM0S 電晶體506的一閘極，係連接至一輸入端點N。PM0S電 晶體502的一汲極與第一 NM0S電晶體504的一汲極，係 共同連接至一輸出端點OUT。第一 NM0S電晶體504的 閘極’係連接至一電源供應電壓VDD。 圖6所示的可變延遲電路3〇6包括一個pm〇s電晶體 602及一個NM〇s電晶體6〇4，且該兩電晶體係串聯在一 電源供應電壓VDD與一接地電壓VSS之間。其中，PM0S 電晶體602的一汲極與NM0S電晶體604的一汲極，係連 接至第一反相器606的一輸入端。第一反相器606的輸出， 係連接至第二反相器608的一輸入端。PM0S電晶體602 的一閘極，係當成一輸入端點p，NM0S電晶體6〇4的一 間極，係對應至一輸入端點N，而且第二反相器的輪出係 連接至一輸出端點OUT。 圖7所示的可變延遲電路306包括從一輸入端點n開 13 1321902 15391pif.doc 始互相串聯的一個第一反相器702及一個第二反相器 704。而且在一電源供應電壓vDD與一接地電壓vss之 間，會有互相串聯的一個PMOS電晶體706及一個NMOS 電晶體708。其中，PMOS電晶體706的閘極係當成一輸 入端點P ’且PMOS電晶體706的一汲極與NMOS電晶體 708的一汲極，係共同連接至一輸出端點〇ut<>nm〇S電 晶體708的一閘極，係連接至第二反相器7〇4的輸出。a variable delay circuit for receiving the second signal of the clock signal 2 and inputting an output signal to the NAND 3 - the second inverter for receiving the output of the variable delay circuit; NM〇S transistor, which is connected to the output of the variable delay circuit and its one pole receives the clock signal; and = the electric body 'one and the pole is connected to the first thirth os transistor f pole' The gate is connected to the output of the second inverter, and a source thereof is connected to a ground voltage. According to another embodiment of the present invention, a pulse generator includes: one, 〇=' for receiving the output of the clock signal and the variable delay circuit, and outputting a first clock pulse signal; a first-inverter for connecting = 〇R _ output 'and outputting - a second clock pulse signal; a: an intersection delay circuit 'for receiving the clock signal and the output of the first-inverter, and Output signal, input to the gate; - a second inverter for receiving the output of the variable delay circuit; and - a rigid (10) transistor, 1321902 15391pif.doc one of the gate receiving variable delay circuit The output of one of the sources receives a power supply voltage 'and one of its gates receives the output of the second inverter. According to another embodiment of the present invention, a pulse generator includes: a NOR gate for receiving a clock signal and an output of a variable delay circuit, and outputting a first clock pulse signal; a first inversion The device is configured to receive the output of the NOR gate and output a second clock pulse signal; a variable delay circuit for receiving the clock signal and the output of the first inverter, and inputting an output signal to a NAND gate; a second inverted chirp for receiving the output of the variable delay circuit; and a first pM〇s^ crystal having a drain connected to the output of the variable delay circuit for receiving the clock signal; a second transistor, one of which is connected to the -PMQS transistor, the gate is connected to the output of the second inverter, and the source is connected to the power supply voltage. In accordance with another embodiment of the present invention, a pulse generator includes: a NOR gate 'for receiving _clock subtraction, - enabling, and outputting a delay circuit' and outputting - a first pulse pulse signal; a first-inverter for receiving the output of the NOR gate and outputting a second clock pulse=number; a variable delay circuit for receiving the output of the (four) pulse signal and the first-inverting is, and Output signal, input to the intercostal space; - a second inverter for receiving the output of the variable delay circuit; and - f P ^ S transistor 'the secret system is connected to the output of the variable delay circuit, The source is connected to the power supply voltage and to the output of the second inverter. According to the present invention, the pulse generator includes: a 15391pif.doc NOR gate for receiving a clock signal, a uniform signal, and a delayable output, and outputting - - a clock pulse signal; a first-inverted person's output for receiving the N0R gate, and an output - a pulse number of the pulse; a variable delay circuit for receiving the clock signal and the first-inverting (four) output' And the output signal is input to the rib closure; a second inverter is used to receive the output of the variable delay circuit; and a first PMOS transistor is connected to the variable delay One of the drains of the circuit is connected to the crystal source of the first pM〇s transistor, the output of which is a gate receiving the clock signal; and a second pM〇θ body*#, a... The %-gate is connected to the output of the second inverter, and its source is connected to a power supply voltage. Compared with the conventional pulse (10), the pulse generation μ of the preferred embodiment of the present invention can be used to reduce the number of loop domain flip-flop circuits. Since a smaller number of gates are used, the power consumption and the area occupied by the power can be reduced. The above and other objects, features, and advantages of the present invention will become more apparent and understood. A circuit diagram of a pulse generator in accordance with a preferred embodiment of the invention. The pulse generator 300 responds to a clock signal CLOCK to generate a - (four) - clock pulse money ~ instrument - (four) two-clock pulse signal φ. The pulse generator 300 includes a NAND gate 302 for receiving the output of the clock signal CLOCK and a variable delay circuit 3〇6 1321902 15391pif.doc; a first inverter 304' is used for the gate 3 An output of 〇2; and a variable delay circuit 306 for receiving the clock signal CLOCK and the output of the first inverter 304. The output of the NAND gate 3〇2 can be changed to the first-clock pulse signal ~φ, and the output of the first inverter can be changed to the second clock pulse signal φ. The pulse generator 300 may further include a second inverter 3〇7 and an NMOS transistor 308. The second inverter 3〇7 receives the output of the variable, late circuit 306 and the output of the second inverter 3〇7. The output of the second inverter 307 can be applied to one of the gates of the NM〇s transistor 3〇8. A drain of the NMOS transistor 308 is connected to the output of the variable delay circuit 3〇6, and a source of the NMOS transistor 308 is connected to the ground voltage VSS. By cooperating with the second inverter 307 and the NMOS transistor 308, the current pulse signal CL CK can be prevented from being a high logic level h•, and the output of the variable delay circuit 306 becomes fl〇ating. The pulse generation zhai 300 can be composed of three logic gates. Therefore, the number of gates constituting the circuit can be reduced, and thereby the power consumption thereof and/or the area of the wafer occupied by the circuit can be reduced. The variable delay circuit 3〇6 can be implemented in a number of different ways. Figures 4 through illustrate various examples of edge-to-edge delay circuits. The variable delay circuit includes an input terminal P for receiving the clock signal CL〇CK, an input terminal N, a wire receiving output of the inverter 3〇4, and/or an output terminal OUT. The variable delay circuit 3〇6 shown in FIG. 4 includes a pM〇s transistor 402 and an NMOS transistor 404, and the two transistor systems are connected in series with a 12 15391 pif.doc power supply voltage VDD and a ground voltage vss. between. Wherein, a gate of the pm〇s transistor 402 is formed as an input terminal p, a gate of the NM〇s transistor 404, corresponding to an input terminal N, and a drain of the PMOS transistor 402 A drain of the NMOS transistor 404 is commonly connected to an output terminal OUT. The variable delay circuit 306 shown in FIG. 5 includes a pm 〇S transistor 〇 2 NMOS transistors 504 and a second NM 〇S transistor 506, and the two NMOS transistors 504 and 506 are connected in series. – between the power supply voltage VDD and a ground voltage VSS. Wherein, a gate of the pm〇s transistor 502 is formed as an input terminal P, and a gate of the second NMOS transistor 506 is connected to an input terminal N. A drain of the PM0S transistor 502 and a drain of the first NMOS transistor 504 are commonly connected to an output terminal OUT. The gate of the first NMOS transistor 504 is connected to a power supply voltage VDD. The variable delay circuit 3〇6 shown in FIG. 6 includes a pm〇s transistor 602 and an NM〇s transistor 6〇4, and the two transistor systems are connected in series with a power supply voltage VDD and a ground voltage VSS. between. A drain of the PMOS transistor 602 and a drain of the NMOS transistor 604 are coupled to an input of the first inverter 606. The output of the first inverter 606 is coupled to an input of the second inverter 608. A gate of the PM0S transistor 602 is an input terminal p, a pole of the NM0S transistor 6〇4 corresponds to an input terminal N, and the wheel of the second inverter is connected to a Output endpoint OUT. The variable delay circuit 306 shown in FIG. 7 includes a first inverter 702 and a second inverter 704 which are connected in series from an input terminal n 13 1321902 15391 pif.doc. Further, between a power supply voltage vDD and a ground voltage vss, there is a PMOS transistor 706 and an NMOS transistor 708 connected in series with each other. Wherein, the gate of the PMOS transistor 706 is an input terminal P' and a drain of the PMOS transistor 706 and a drain of the NMOS transistor 708 are connected together to an output terminal 〇ut<>nm A gate of the NMOS transistor 708 is coupled to the output of the second inverter 〇4.
圖8所示的可變延遲電路3〇6包括一個PMOS電晶體The variable delay circuit 3〇6 shown in FIG. 8 includes a PMOS transistor
802、一個第一 NMOS電晶體804、以及一個第二NMOS 電晶體806，且該些電晶體802、804及806係串聯在一電 源供應電壓VDD與一接地電壓vsS之間。其中，PMOS 電晶體802的一閘極，係當成一輸入端點p ,第一及第二 NMOS電晶體804及806的閘極，係當成一輸入端點N。 PMOS電晶體802的一汲極與第一 NMOS電晶體804的一 汲極’係共同連接至一輸出端點out。802, a first NMOS transistor 804, and a second NMOS transistor 806, and the transistors 802, 804, and 806 are connected in series between a power supply voltage VDD and a ground voltage vsS. The gate of the PMOS transistor 802 is regarded as an input terminal p, and the gates of the first and second NMOS transistors 804 and 806 are regarded as an input terminal N. A drain of PMOS transistor 802 is coupled to an output terminal out in conjunction with a drain of first NMOS transistor 804.
圖9到圖12係繪示可用在如圖丨所示的脈衝式正反 器100的閂鎖器範例的電路圖。 圖9的閂鎖器900係包括：一個第一反相器9〇2，其 係架構成響應一第一時脈脈衝訊號〜φ及一第二時脈脈衝 訊號^接收—資料輸入訊號DIN ; —個第二反相器904， 巧收第一反相器902的輸出；一個第三反相器906，響應 第一時脈脈衝訊號〜Φ及第二時脈脈衝訊號ψ ,接收第二反 相，904的輸出；以及一個第四反相器908 ’接收第一反 相器902的輪出。帛四反相器_的輸出即為一資料輸出 14 1321902 15391pif.doc 訊號DOUT。第二反相器904的輸出，可連接至第__反相 器902的輸出。閂鎖器900可響應第一時脈脈衝訊號〜小的 一下降邊緣與第二時脈脈衝訊號φ的一上升邊緣，將資料 輸入訊號DIN，轉換成資料輸出訊號d〇UT輸出。 圖10的閂鎖器1000係包括：一個第一 AND閘1〇〇2, 接收一資料輸入訊號DIN與一反向掃描致能訊號〜SE ; 一 個第二AND閘1004 ’接收一掃描輸入訊號SI與一掃描致 能訊號SE ; —個NOR閘1006，響應第一時脈脈衝訊號〜小 及第二時脈脈衝訊號φ’接收第一及第二閘極1〇〇2及1〇〇4 的輸出；一個第一反相器1008,接收NOR閘1〇〇6的輸出； 一個第二反相器1010,響應第一時脈脈衝訊號〜φ及第二時 脈脈衝sfl號φ ’接收第一反相器1008的輸出；以及一個第 二反相斋1012，接收NOR閘1006的輸出，並且輸出一資 料輸出5孔5虎D0UT。第二反相器1〇1〇的輸出，可連接至 NOR閘1006的輸出。 §知描致症號SE在邏輯高位準而被致能(activate(j) 時，閂鎖器1000會接收掃描輸入訊號SI，並且將其當成 輸入訊號。當掃描致能訊號SE在邏輯低位準而被禁能 (inactivated)時’閂鎖器1〇〇〇會接收資料輸入訊號din， 並且將其當成輸入訊號。接下來，閂鎖器1000會響應第一 時脈脈衝訊號〜φ及第二時脈脈衝訊號φ，將所接收的輸入 訊號’轉換成一個資料輸出訊號D0UT輸出。 圖11的閂鎖器1100係包括：一個第一反相器11〇2， 響應一第一時脈脈衝訊號〜φ及一第二時脈脈衝訊號φ，接 15 1321902 15391pif.doc 收一資料輸入訊號DIN ; —個NAND閘1104，接收第一 反相器1102的輸出與一設定訊號(set signai)〜set，當成其 輸入訊號；一個第二反相器1106，響應第一時脈脈衝訊號 〜φ及第二時脈脈衝訊號φ’接收NAND閘1104的輸出；以 及一個第三反相器1108，接收第一反相器1102的輸出， 並且輸出一資料輸出訊號D0UT。第二反相器π〇6的輪 出’可連接至第一反相器1102的輸出。 當設定訊號〜SET在邏輯高位準而被禁能時，問鎖器 1100會響應苐一時脈脈衝訊號〜φ及第二時脈脈衝訊號φ， 將資料輸入訊號DIN’當成資料輸出訊號DOUT輸出。當 設定訊號〜SET在邏輯低位準而被致能時，閂鎖器11〇〇會 將資料輸出訊號DOUT，設定為邏輯高位準。 圖12的閂鎖器1200係包括：一個第一反相器12〇2, 響應一第一時脈脈衝訊號〜φ及一第二時脈脈衝訊號φ，接 收一資料輸入訊號DIN ; —個NOR閘1204，接收第—反 相器1202的輸出與一重置訊號(reset signai)RESET，當成 其輸入訊號；一個第二反相器1206，響應第一時脈脈衝訊 號〜φ及第二時脈脈衝訊號φ，接收NOR閘1204的輸出； 以及一個第三反相器1208’接收第一反相器1202的輸出， 並且輸出一資料輸出訊號DOUT。第二反相器12〇6的輸 出，可連接至第一反相器1202的輸出。 當重置訊號RESET在邏輯低位準而被禁能時，閃鎮 器1200會響應第一時脈脈衝訊號〜φ及第二時脈脈衝訊號 Φ ’將資料輸入訊號DIN ’當成資料輸出訊號DOUT輸出。 16 1321902 15391pif.doc 當重置§fl號RESET在邏輯高位準而被致能時，閂鎖器1200 會將資料輸出訊號DOUT，重置為邏輯低位準。 圖13係繪不·~~個根據本發明另一較佳實施例的一個 脈衝產生器1300的電路圖。請參考圖丨3所示，與圖3所 示的脈衝產生器300不同的是’脈衝產生器boo更加包括 一個第二NMOS電晶體1309 ’且該第二NMOS電晶體1309 係連接在一可變延遲電路1306的輸出與一第一 NMOS電 晶體1308之間，且其一閘極係連接至一時脈訊號 CLOCK。在圖3所示的脈衝產生器300中，可再加入一個 第一 NMOS電晶體1309，以避免在可變延遲電路1306的 輸出增加至邏輯高位準時，NMOS電晶體308被關閉(turn off)—段時間，而產生一個連接到接地電壓vss的電流路 徑。換έ之，當可變延遲電路13〇6的輸出響應邏輯低位準 的日脈δίΐ號CLOCK ’而增加至邏輯高位準時，第二nm〇s 電晶體1309會被關閉，以切斷從可變延遲電路13〇6的輸 出到接地電壓VSS之間的電流路徑。 圖14係繪示一個用來說明由脈衝產生器3〇〇(如圖工 所。示)所產生的一第一時脈脈衝訊號〜φ及一第二時脈脈衝 訊號Φ，施加至圖9所示的閂鎖器9〇〇時，根據本發明一 較佳實施_脈衝式正反H的操作時序圖。響應根據時脈 訊，CLOCK的-上升邊緣而產生的第—時脈脈衝訊號〜φ 及第二時脈脈衝訊號φ，可將資料輸入訊號Dm，冬成一 資料輸出訊號D0UT輸出。圖η所示的操作時序^，亦 可應用於包括根據本發明另一較佳實施例如圖13所示的 17 1321902 15391pif.doc =ΐΓ〇與如圖9所示_器_的-脈衝式正 脈衝Γ二康本發明另—較佳實施例的一個 ^ ㈣路®。當致能峨enable被致能 至一邏輯高位準時’脈衝產生 ==，接收一時脈訊號CL0CK、致能訊號 變延遲電路1506的輸出；一個反相器 、接收NAND開15〇2的輸出訊號；以及一個可變延 遲電路1506，經由一輸入端點P，接收時脈訊號CLOCK， 由—輸入端點N，接收反相器1504的輸出訊號。 f甲1 1502的輸出訊號’可被當成一第一時脈脈衝訊 號〜Φ，且反相器聰的輸出訊號，可被當成一第二時脈 端脈衝訊號φ。 脈衝產生器1500更加包括：一個第二反相器丨jo?， f枚可變延遲電路15〇6的輸出訊號；以及一個舰〇s電 b曰體.1508 ’其係連接在可變延遲電路15()6的輸出與一接 地，壓vss之間’而且為了避免在時脈訊號CL〇CK'的邏 ，向位準賴，讓可變輯電路15G6的輸出變得飄浮不 定L其一閘極係連接至第二反相器1507的輸出。熟習相關 技蟄者當知亦可使用如圖4到圖8中所示的其中一電路， 取代可變延遲電路1506。 圖16係繪示一個根據本發明另一較佳實施例的一個 脈衝產生器1600的電路圖。當致能訊號ENABLE被致能 15391pif.doc 至一邏輯高位準時，脈衝產生器1600可被當成如圖13所 示的脈衝產生器1300操作。脈衝產生器16〇〇係包括：一 個NAND閘1602，接收一時脈訊號CL〇CK、致能訊號 ENABLE、以及一可變延遲電路16〇6的輸出；一個第一反 相器1604，接收NAND閘1602的輸出訊號；以及一個可 變延遲電路1606，經由一輸入端點p，接收時脈訊號 CLOCK，並且經由一輸入端點N，接收反相器16〇4的輸 出訊號。NAND閘1602的輸出訊號，可被當成一第一時 脈脈衝況號〜φ ’且反相器1604的輸出訊號，可被當成一 第二時脈端脈衝訊號φ。 脈衝產生器1600更加包括：一個第二反相器16〇7， 接收可變延遲電路1606的輸出訊號；以及一個第— NM〇s 電晶體1608及一個第二NM0S電晶體1609，其係串聯在 可變延遲電路1606的輸出與一接地電壓vss之間。第一 NMOS電晶體1608的一閘極，係連接至第二反相器16〇7 的輸出’而且第二NM0S電晶體1609的一閘極，係連接 至時脈訊號CLOCK。 圖17係繪示一個根據本發明另一較佳實施例的一個 脈衝產生器1700的電路圖。脈衝產生器17〇〇係包括：一 個NOR閘1702，接收一時脈訊號CL〇CK以及一可變延 遲電路1706的輸出；一個反相器1704，接收NOR閘1702 的輸出訊號；以及一個可變延遲電路17〇6，接收時脈訊號 CLOCK與反相器17〇4的輸出訊號。N0R閘17〇2的輸出 汛號’可被當成一第一時脈脈衝訊號〜ψ，且反相器17〇4 1321902 15391pif.doc 的輸出訊號，可被當成一第二時脈端脈衝訊號φ。 脈衝產生器1700更加包括一個pm〇s電晶體及 一個第二反相器1707，用來接收可變延遲電路17〇6的輪 出Λ旒。其中’ pm〇S電晶體17〇8係連接在可變延遲電路 17〇6的輸出與一電源供應電壓vcc之間，而且為了避免 在時脈訊號CLOCK的邏輯低位準期間，讓可變延遲電路 的輸出變得飄浮不定，其一閘極係連接至第二反相器 1707的輸出。 ，圖18係繪示一個根據本發明另一較佳實施例的一個 脈衝產1_的電路圖。與圖17所示的脈衝產生器 1700不同的是’脈衝產生器1800更加包括一個第二NM〇^ 電晶體1809，言亥第二NM0S電晶體i8〇9係連接在一可變 延遲電路1806的輸出與一第一 PM〇s電晶體18〇8之間， 且其-閘極侍、連接至-時脈訊號CL〇CK。在圖17所示的 脈衝產生器1700中’可再加入一個第二pM〇s電晶體 1809’以避免在可·遲電路簡的輸出降低至邏輯低位 準時，PM0S電晶體1708被關閉一段時間，而產生一個連 接到電源供應魏VCC的電流路徑。齡之，當可變延 遲電路18G6的輸出響應邏輯高位準的時脈訊號cl〇ck， =降低至_低位科’第二PMQS電麟蘭會被關 乂刀斷從可^延遲電路1806的輸出到電源供應電壓 VCC之間的電流路徑。 圖19係繪示一個用來說明由根據本發明另一實施例 如圖17所不的脈衝產生器17〇〇,以及如圖9所示的閃鎖 20 1321902 15391pif.doc 器900所組成的一個脈衝式正反器的操作時序圖。 ==CLOCK的一下降邊緣而產生的第一時:二 Λ唬〜φ及第一時脈脈衝訊號φ ,可將資料輸入訊號D取， 當成一資料輸出訊號D0UT輸出。目19所示的操 圖：亦可應用於包括根據本發明另—較佳實施例如圖Μ 所不的脈，產生II 18QQ與如圖9所示的閃鎖器_的一脈 衝式正反器的操作。 “圖20係緣示一個根據本發明另一較佳實施例的一個 脈衝產生g 2_的電㈣。當魏職/enable被致能 至-邏輯低位準時，脈衝產生器鳩可被當成如圖_ 不的脈衝產生㈢1700操作。脈衝產生器2_係包括：一 個NOR㈤2002，接收一時脈訊號cl〇(：k、致能訊號 /ENABLE、以及—可變延遲電路雇的輸出，·一個第二 反相器2004 ’接收職閘·2的輸出訊號；以及一個可 電路2_，經由—輸人端點p，接收時脈訊號 OCK ’並且經由一輸入端點N，接收反相器雇的輸 出訊號。。NOR閘纖的輸出訊號，可被當成一第一時脈 脈衝减十且反相器2004的輸出訊號，可被當成一第 二時脈端脈衝訊號φ。 脈衝產生益2000更加包括：一個第二反相器2〇〇7， 接收可4延遲電路2GG6的輸出訊號，·以及―個pM〇s電 B曰體2008，其係連接在可變延遲電路2_的輸出斑一電 1 供應電壓vcc之間’且其—·係連接至第二反相器 2007的輸出。 21 1321902 15391pif.doc 圖21係繪示一個根據本發明另一較佳實施例的一個 脈衝產生II 2100的電路圖。當致能訊號/ENABLE被致能 至一邏輯高位準時，脈衝產生器21〇〇可被當成如圖13所 示的脈衝產生器1300操作。脈衝產生器21〇〇係包括：一 個NOR閘2102，接收一時脈訊號CL〇CK、致能訊號 /ENABLE、以及-可變延遲電路21〇6的輸出；一個第一 反相器2104 ’接收NOR閘2102的輸出訊號；以及一個可 變延遲電路2106 ’經由-輸入端點p，接收時脈訊號 CLOCK，並且經由一輸入端點N，接收反相器21〇4的輸 出訊號。NOR閘2102的輸出訊號，可被當成一第一時脈 脈衝訊號〜φ，且反相器2104的輸出訊號，可被當成一第 一時脈端脈衝訊號φ。 脈衝產生态2100更加包括：一個第二反相器21〇7， 接收可變延遲電路2106的輸出訊號；以及一個第一 pM〇s 電晶體2108及-個第二PM〇s電晶體21〇9，其係串聯在 可炎延遲電路2106的輸出與一電源供應電慶vcc之間。 第- _電晶體2108的一閘極，係連接至第二反相器 2107的輸出，而且第二PM〇s電晶體21〇9的一閘極，係 連接至時脈訊號CLOCK。 ,雖然圖14係繪示由圖3的脈衝產生器與由圖9的问 鎖器所組成的-個正反器的操作，且圖19係緣示由圖17 的脈衝產生器與由圖9的問鎖器所組成的一個正反器的操 作:熟習相關技藝者當知，根據本發明陳述，可用脈衝產 生器與問鎖器的任何組合，來架構一正反器。此外，在此 22 15391pif.doc 所述之PMOS電晶體、NM0S電晶體、高及低訊號、 體、低 晶 邏，閘，亦可以熟習相關技藝者所熟知之等效電 及尚訊號、以及邏輯閘取代。 ，然本發明已啸佳實麵揭露如上，财並非用以 限疋本發明’任何孰習此枯蓺去 ^ 白此技☆者，在不脫離本發明之精神 當可作些許之更動與潤飾，因此本發明之保： 摩巳圍备視後附之申請專利範圍所界定者 又 【圖式簡單說明】 ，1係繪示-個習知的脈衝式正反器的方塊圖。 =2係繪示—個習知的脈衝產生器的電路圖。 器的=考示一個根據本發明-較佳實施例的脈衝產生 圖4到圖8係繪示可用在如囝 _ -個可變延遲電路範例的電路圖Y不的脈衝產生器的 圖9到圖12係繪示可用在如圖 器的多數個_錄_電關/ 1所示的脈衝式正反 圖13係繪示一個根據本發明 脈衝產生器的電路圖。 月另—較佳實施例的一個 圖14係繪示一個用來說 圖9的閃鎖器的一佩衝=圖3的脈衝產生器與 圖Π佐a- 、久為靶例的時序圖。 ΰ 15係繪不一個根據本發明 脈衝產生器的電路圖。 乃—較佳實施例的一個 囷16係緣示一個根據本 脈衝產生器的電路圖。 β乃—較佳實施例的一個 23 1321902 15391pif.doc 圖17係繪示一個根據本發明另一 脈衝產生器的電路圖。 較铨實施例的一個 圖18係繪示一個根據本發 脈衝產生器的電路圖。 較佳實施例的一個 圖19係繪示-個用來說明包括圖 圖她 圖20係繪不-個根據本發明另 Μ口 脈衝產生器的電路圖。 車又佳具施例的一個 較佳實施例的·一個 圖21係繪示一個根據本發明另— 脈衝產生器的電路圖。 【主要元件符號說明】 100 :正反器 110 :閂鎖器 120 :脈衝產生器 122 :第一反相器 124 :第二反相器 126 :第三反相器 128 : NAND 閘 130 :第四反相器 DIN :輸入資料 DOUT :輸出資料 CLOCK :時脈訊號 VDD :電源供應電壓 VSS :接地電壓 24 1321902 15391pif.doc OUT :輸出端點 P、N:輸入端點 φ:第二時脈脈衝訊號 〜φ :第一時脈脈衝訊號 300 :脈衝產生器 302 : NAND 閘 304 :第一反相器 306 :可變延遲電路 307 :第二反相器 308 : NM0S電晶體 402 : PM0S電晶體 404 : NM0S電晶體 502 : PM0S電晶體 504 :第一 NM0S電晶體 506 :第二NM0S電晶體 602 : PM0S電晶體 604 : NM0S電晶體 606 ·•第一反相器 608 :第二反相器 702 :第一反相器 704 :第二反相器 706 : PM0S電晶體 708 : NM0S電晶體 802 : PM0S電晶體 25 1321902 15391pif.doc 804 :第一 NMOS電晶體 806 :第二NM0S電晶體 900 :閂鎖器 902 :第一反相器 904 :第二反相器 906 :第三反相器 908 :第四反相器 1000 :閂鎖器 1002 :第一 AND 閘 1004 :第二 AND 閘 1006 : NOR 閘 1008 :第一反相器 1010 ··第二反相器 1012 :第三反相器 SE :掃描致能訊號 〜SE :反向掃描致能訊號 SI .掃描輸入訊號 1100 :閂鎖器 1102 :第一反相器 1104 : NAND 閘 1106 :第二反相器 1108 :第三反相器 〜SET :設定訊號 1200 :閂鎖器 26 1321902 15391pif.doc 1202 :第一反相器 1204 : N〇R 閘 1206 :第二反相器 1208 :第三反相器 RESET :重置訊號 1300 :脈衝產生器 1302 : NAND 閘 1304 :第一反相器 1306 :可變延遲電路 1307 :第二反相器 1308 :第一 NMOS電晶體 1309 ··第二NMOS電晶體 1500 :脈衝產生器 1502 : NAND 閘 1504 :第一反相器 1506 :可變延遲電路 1507 :第二反相器 1508 : NMOS電晶體 ENABLE、/ENABLE :致能訊號 1600 :脈衝產生器 1602 : NAND 閘 1604 :第一反相器 1606 :可變延遲電路 1607 :第二反相器 27 1321902 15391pif.doc 1608 :第一 NMOS電晶體 1609 :第二NM0S電晶體 1700 :脈衝產生器 1702 : NOR 閘 1704 :第一反相器 1706 :可變延遲電路 1707 :第二反相器 1708 : PMOS電晶體 1800 :脈衝產生器 1802 : NOR 閘 1804 :第一反相器 1806 :可變延遲電路 1807 :第二反相器 1808 :第一 PMOS電晶體 1809 :第二NMOS電晶體 2000 :脈衝產生器 2002 : NOR 閘 2004 :第一反相器 2006 :可變延遲電路 2007 :第二反相器 2008 : PMOS電晶體 2100:脈衝產生器 2102 : NOR 閘 2104 :第一反相器 28 1321902 15391pif.doc 2106 :可變延遲電路 2107 :第二反相器 2108 :第一 PMOS電晶體 2109 :第二PMOS電晶體 299 through 12 are circuit diagrams showing an example of a latch that can be used in the pulsed flip-flop 100 shown in FIG. The latch 900 of FIG. 9 includes: a first inverter 9〇2, the frame is configured to respond to a first clock pulse signal φ and a second clock pulse signal to receive data input signal DIN; a second inverter 904, which receives the output of the first inverter 902; a third inverter 906 receives the second inverse in response to the first clock pulse signal Φ and the second clock signal ψ Phase, the output of 904; and a fourth inverter 908' receives the turn-out of the first inverter 902. The output of the quad inverter _ is a data output 14 1321902 15391pif.doc signal DOUT. The output of the second inverter 904 can be connected to the output of the __ inverter 902. The latch 900 converts the data input signal DIN into a data output signal d〇UT output in response to a falling edge of the first clock pulse signal and a rising edge of the second clock pulse signal φ. The latch 1000 of FIG. 10 includes: a first AND gate 1〇〇2, receiving a data input signal DIN and a reverse scan enable signal~SE; and a second AND gate 1004' receiving a scan input signal SI. And a scan enable signal SE; a NOR gate 1006, receiving the first and second gates 1〇〇2 and 1〇〇4 in response to the first clock pulse signal~small and the second clock pulse signal φ' Output; a first inverter 1008 receives the output of the NOR gate 1〇〇6; a second inverter 1010 receives the first response in response to the first clock pulse signal φ φ and the second clock pulse sfl φ ' The output of the inverter 1008; and a second inverting 1012, receives the output of the NOR gate 1006, and outputs a data output of 5 holes 5 Tiger D0UT. The output of the second inverter 1〇1〇 can be connected to the output of the NOR gate 1006. § Knowing that the SE is enabled at the logic high level (activate(j), the latch 1000 receives the scan input signal SI and treats it as an input signal. When the scan enable signal SE is at a logic low level When inactivated, the latch 1 receives the data input signal din and uses it as an input signal. Next, the latch 1000 responds to the first clock pulse signal ~φ and the second. The clock pulse signal φ converts the received input signal into a data output signal DOUT output. The latch 1100 of FIG. 11 includes: a first inverter 11〇2, responsive to a first clock pulse signal ~φ and a second clock pulse signal φ, connected to 15 1321902 15391pif.doc to receive a data input signal DIN; a NAND gate 1104, receiving the output of the first inverter 1102 and a set signal (set signai) ~ set As a second input signal, a second inverter 1106 receives the output of the NAND gate 1104 in response to the first clock pulse signal φ and the second clock pulse signal φ'; and a third inverter 1108 receives the first An output of the inverter 1102, and A data output signal D0UT is output. The rounding of the second inverter π〇6 can be connected to the output of the first inverter 1102. When the setting signal ~SET is disabled at the logic high level, the lock 1100 is asked. The data input signal DIN' is output as the data output signal DOUT in response to the first pulse signal ~φ and the second clock signal φ. When the setting signal ~SET is enabled at the logic low level, the latch 11 The data output signal DOUT is set to a logic high level. The latch 1200 of FIG. 12 includes: a first inverter 12〇2, responsive to a first clock pulse signal φ φ and a second time The pulse signal φ receives a data input signal DIN; a NOR gate 1204 receives the output of the first inverter 1202 and a reset signai RESET as its input signal; a second inverter 1206 Receiving an output of the NOR gate 1204 in response to the first clock pulse signal ~φ and the second clock pulse signal φ; and a third inverter 1208' receiving the output of the first inverter 1202 and outputting a data output Signal DOUT. Second inverter 12〇6 The output can be connected to the output of the first inverter 1202. When the reset signal RESET is disabled at the logic low level, the flasher 1200 responds to the first clock pulse signal φ and the second clock pulse signal. Φ 'Use the data input signal DIN ' as the data output signal DOUT output. 16 1321902 15391pif.doc When the reset §fl number RESET is enabled at the logic high level, the latch 1200 will reset the data output signal DOUT. It is a low level of logic. Figure 13 is a circuit diagram of a pulse generator 1300 in accordance with another preferred embodiment of the present invention. Referring to FIG. 3, unlike the pulse generator 300 shown in FIG. 3, 'the pulse generator boo further includes a second NMOS transistor 1309' and the second NMOS transistor 1309 is connected to a variable The output of the delay circuit 1306 is connected to a first NMOS transistor 1308, and a gate thereof is connected to a clock signal CLOCK. In the pulse generator 300 shown in FIG. 3, a first NMOS transistor 1309 can be added to avoid the NMOS transistor 308 being turned off when the output of the variable delay circuit 1306 is increased to a logic high level. For a period of time, a current path connected to the ground voltage vss is generated. In other words, when the output of the variable delay circuit 13〇6 is increased to the logic high level in response to the logic low level of the clock δίΐ CLOCK ', the second nm〇s transistor 1309 is turned off to cut off the variable The current path between the output of the delay circuit 13〇6 to the ground voltage VSS. FIG. 14 is a diagram showing a first clock pulse signal φ and a second clock pulse signal Φ generated by the pulse generator 3 (shown in the figure), applied to FIG. 9. When the latch 9 is shown, an operational timing diagram of the pulsed positive and negative H is implemented in accordance with a preferred embodiment of the present invention. In response to the first pulse pulse signal ~φ and the second clock pulse signal φ generated by the rising edge of the CLOCK, the data input signal Dm and the winter data output signal D0UT can be output. The operation sequence shown in FIG. 2 can also be applied to include - 17 1321902 15391 pif. doc = ΐΓ〇 shown in FIG. 13 and - pulse type positive as shown in FIG. 9 according to another preferred embodiment of the present invention. Pulse Γ 康 康 本 发明 发明 发明 发明 发明 发明 发明 本 ^ ^ ^ ^ ^ ^ ^ ^ When the enable enable is enabled to a logic high level, the pulse generation ==, receiving the output of the pulse signal CL0CK, the enable signal delay circuit 1506; and an inverter, receiving the output signal of the NAND switch 15? And a variable delay circuit 1506, which receives the clock signal CLOCK via an input terminal P, and receives the output signal of the inverter 1504 by the input terminal N. The output signal of the 1A 1502 can be regarded as a first clock pulse signal ~Φ, and the output signal of the inverter can be regarded as a second clock pulse signal φ. The pulse generator 1500 further includes: a second inverter 丨jo?, f output signals of the variable delay circuit 15 〇 6; and a ship s electric b body. 1508 ' is connected to the variable delay circuit The output of 15()6 is connected to a ground, voltage vss' and in order to avoid the logic of the clock signal CL〇CK', the output of the variable circuit 15G6 becomes floating. The pole is connected to the output of the second inverter 1507. It is known to those skilled in the art that one of the circuits as shown in Figs. 4 to 8 can be used instead of the variable delay circuit 1506. Figure 16 is a circuit diagram of a pulse generator 1600 in accordance with another preferred embodiment of the present invention. When the enable signal ENABLE is enabled 15391pif.doc to a logic high level, the pulse generator 1600 can be operated as the pulse generator 1300 as shown in FIG. The pulse generator 16 includes: a NAND gate 1602 receiving a clock signal CL〇CK, an enable signal ENABLE, and an output of a variable delay circuit 16〇6; a first inverter 1604 receiving the NAND gate An output signal of 1602; and a variable delay circuit 1606 receives the clock signal CLOCK via an input terminal p and receives an output signal of the inverter 16〇4 via an input terminal N. The output signal of the NAND gate 1602 can be regarded as a first clock pulse condition number φ φ ' and the output signal of the inverter 1604 can be regarded as a second clock pulse signal φ. The pulse generator 1600 further includes: a second inverter 16〇7, receiving the output signal of the variable delay circuit 1606; and a first NM〇s transistor 1608 and a second NMOS transistor 1609 connected in series The output of the variable delay circuit 1606 is between a ground voltage vss. A gate of the first NMOS transistor 1608 is coupled to the output ' of the second inverter 16A7 and a gate of the second NMOS transistor 1609 is coupled to the clock signal CLOCK. Figure 17 is a circuit diagram of a pulse generator 1700 in accordance with another preferred embodiment of the present invention. The pulse generator 17 includes: a NOR gate 1702 receiving a clock signal CL〇CK and an output of a variable delay circuit 1706; an inverter 1704 receiving an output signal of the NOR gate 1702; and a variable delay The circuit 17〇6 receives the output signals of the clock signal CLOCK and the inverter 17〇4. The output nickname ' of the N0R gate 17〇2 can be regarded as a first clock pulse signal ~ψ, and the output signal of the inverter 17〇4 1321902 15391pif.doc can be regarded as a second clock pulse signal φ . The pulse generator 1700 further includes a pm〇s transistor and a second inverter 1707 for receiving the turns of the variable delay circuit 17〇6. Wherein the 'pm〇S transistor 17〇8 is connected between the output of the variable delay circuit 17〇6 and a power supply voltage vcc, and in order to avoid the variable delay circuit during the logic low level of the clock signal CLOCK The output becomes floating and its gate is connected to the output of the second inverter 1707. Figure 18 is a circuit diagram showing a pulse generation 1_ according to another preferred embodiment of the present invention. Different from the pulse generator 1700 shown in FIG. 17, the pulse generator 1800 further includes a second NM transistor 1809, and the second NMOS transistor i8〇9 is connected to a variable delay circuit 1806. The output is connected to a first PM〇s transistor 18〇8, and its gate is connected to the -clock signal CL〇CK. In the pulse generator 1700 shown in FIG. 17, a second pM〇s transistor 1809 can be added to avoid the PMOS transistor 1708 being turned off for a period of time when the output of the programmable circuit is reduced to a logic low level. And a current path is generated that is connected to the power supply Wei VCC. When the output of the variable delay circuit 18G6 responds to the logic high level, the pulse signal cl〇ck, = is reduced to _ low position. The second PMQS is replaced by the output of the delay circuit 1806. Current path to the power supply voltage VCC. Figure 19 is a diagram showing a pulse composed of a pulse generator 17A according to another embodiment of the present invention, such as Figure 17, and a flash lock 20 1321902 15391pif.doc 900 shown in Figure 9. Operation timing diagram of the flip-flop. == The first time generated by a falling edge of CLOCK: two Λ唬~φ and the first clock pulse signal φ, the data input signal D can be taken as a data output signal D0UT output. The figure shown in FIG. 19 can also be applied to a pulsed flip-flop which generates II 18QQ and the flash locker shown in FIG. 9 including the pulse according to another preferred embodiment of the present invention. Operation. Fig. 20 is a diagram showing a pulse (g) for generating a g 2_ according to another pulse according to another preferred embodiment of the present invention. When the Wei/enable is enabled to the logic low level, the pulse generator 鸠 can be regarded as _ No pulse generation (3) 1700 operation. Pulse generator 2_ includes: a NOR (5) 2002, receiving a clock signal cl〇 (: k, enable signal / ENABLE, and - variable delay circuit hired output, · a second counter The phaser 2004 'receives the output signal of the job gate 2; and a circuit 2_ receives the clock signal OCK' via the input terminal p and receives the output signal of the inverter hire via an input terminal N. The output signal of the NOR brake fiber can be regarded as a first clock pulse minus ten and the output signal of the inverter 2004 can be regarded as a second clock pulse signal φ. The pulse generation benefit 2000 further includes: a first The second inverter 2〇〇7 receives the output signal of the 4th delay circuit 2GG6, and the “pM〇s electric B body 2008, which is connected to the output spot of the variable delay circuit 2_. Between vcc 'and its - is connected to the second inverter Output of 2007. 21 1321902 15391pif.doc Figure 21 is a circuit diagram showing a pulse generation II 2100 in accordance with another preferred embodiment of the present invention. Pulse generation occurs when the enable signal /ENABLE is enabled to a logic high level. The device 21A can be operated as a pulse generator 1300 as shown in Fig. 13. The pulse generator 21 includes a NOR gate 2102 that receives a clock signal CL〇CK, an enable signal/ENABLE, and a The output of the variable delay circuit 21〇6; a first inverter 2104' receives the output signal of the NOR gate 2102; and a variable delay circuit 2106' receives the clock signal CLOCK via the input terminal p, and via an input End point N, receiving the output signal of the inverter 21〇4. The output signal of the NOR gate 2102 can be regarded as a first clock pulse signal ~φ, and the output signal of the inverter 2104 can be regarded as a first The pulse end signal φ. The pulse generating state 2100 further includes: a second inverter 21〇7, receiving the output signal of the variable delay circuit 2106; and a first pM〇s transistor 2108 and a second PM 〇s transistor 21〇9 , which is connected in series between the output of the flammable delay circuit 2106 and a power supply circuit vcc. A gate of the first-electrode transistor 2108 is connected to the output of the second inverter 2107, and the second PM 〇 A gate of the s transistor 21〇9 is connected to the clock signal CLOCK. Although FIG. 14 is a cross-reactor formed by the pulse generator of FIG. 3 and the question lock of FIG. Operation, and FIG. 19 is the operation of a flip-flop consisting of the pulse generator of FIG. 17 and the question lock of FIG. 9: It is known to those skilled in the art that, in accordance with the present invention, a pulse generator can be used with Ask any combination of locks to structure a flip-flop. In addition, the PMOS transistor, the NM0S transistor, the high and low signal, the body, the low crystal logic, and the gate described in the 22 15391 pif.doc can also be familiar with the equivalent electrical and signal, and logic known to those skilled in the art. The brake is replaced. However, the present invention has been disclosed in the above, and the financials are not intended to limit the invention to any of the techniques of the present invention, and may be modified and retouched without departing from the spirit of the present invention. Therefore, the protection of the present invention: The definition of the patent application scope attached to the 巳 巳 又 又 又 【 【 【 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 = 2 is a circuit diagram of a conventional pulse generator. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The series 12 shows a circuit diagram of a pulse generator according to the present invention, which is shown in a plurality of _records_electricity/1 shown in the figure. Another embodiment of the preferred embodiment Fig. 14 is a timing diagram showing a pulse generator of Fig. 9 and a pulse generator of Fig. 3 and Fig. 3 a. ΰ 15 is a circuit diagram of a pulse generator according to the present invention. That is, a 囷16 lining of the preferred embodiment shows a circuit diagram according to the present pulse generator. β is a 23 of the preferred embodiment. 132 1321902 15391pif.doc Figure 17 is a circuit diagram showing another pulse generator in accordance with the present invention. A Figure 18 of a more simplified embodiment shows a circuit diagram of a pulse generator in accordance with the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 19 is a circuit diagram for illustrating the inclusion of a diagram. Figure 20 is a circuit diagram of another mouthpiece pulse generator in accordance with the present invention. A preferred embodiment of a preferred embodiment of the vehicle is shown in Figure 21 which is a circuit diagram of another pulse generator in accordance with the present invention. [Main component symbol description] 100: flip-flop 110: latch 120: pulse generator 122: first inverter 124: second inverter 126: third inverter 128: NAND gate 130: fourth Inverter DIN: Input data DOUT: Output data CLOCK: Clock signal VDD: Power supply voltage VSS: Ground voltage 24 1321902 15391pif.doc OUT : Output terminal P, N: Input terminal φ: Second clock pulse signal 〜φ: first clock pulse signal 300: pulse generator 302: NAND gate 304: first inverter 306: variable delay circuit 307: second inverter 308: NM0S transistor 402: PM0S transistor 404: NM0S transistor 502: PM0S transistor 504: first NMOS transistor 506: second NMOS transistor 602: PM0S transistor 604: NMOS transistor 606 • First inverter 608: second inverter 702: An inverter 704: a second inverter 706: a PM0 transistor 708: an NMOS transistor 802: a PM0 transistor 251321902 15391pif.doc 804: a first NMOS transistor 806: a second NMOS transistor 900: a latch 902: first inverter 904: second inverter 906: third inverter 908: fourth inverter 1000 : Latch 1002: first AND gate 1004: second AND gate 1006: NOR gate 1008: first inverter 1010 · second inverter 1012: third inverter SE: scan enable signal ~ SE : Reverse scan enable signal SI. Scan input signal 1100: Latch 1102: First inverter 1104: NAND gate 1106: Second inverter 1108: Third inverter ~ SET: Set signal 1200: Latch Locker 26 1321902 15391pif.doc 1202 : First inverter 1204 : N〇R Gate 1206 : Second inverter 1208 : Third inverter RESET : Reset signal 1300 : Pulse generator 1302 : NAND gate 1304 : First inverter 1306: variable delay circuit 1307: second inverter 1308: first NMOS transistor 1309 · second NMOS transistor 1500: pulse generator 1502: NAND gate 1504: first inverter 1506 Variable delay circuit 1507: second inverter 1508: NMOS transistor ENABLE, /ENABLE: enable signal 1600: pulse generator 1602: NAND gate 1604: first inverter 1606: variable delay circuit 1607: Two inverters 27 1321902 15391pif.doc 1608 : First NMOS transistor 1609 : Second NMOS transistor 1700 : Pulse production 1702: NOR gate 1704: first inverter 1706: variable delay circuit 1707: second inverter 1708: PMOS transistor 1800: pulse generator 1802: NOR gate 1804: first inverter 1806: variable Delay circuit 1807: second inverter 1808: first PMOS transistor 1809: second NMOS transistor 2000: pulse generator 2002: NOR gate 2004: first inverter 2006: variable delay circuit 2007: second counter Phaser 2008: PMOS transistor 2100: pulse generator 2102: NOR gate 2104: first inverter 28 1321902 15391pif.doc 2106: variable delay circuit 2107: second inverter 2108: first PMOS transistor 2109: Second PMOS transistor 29