TWI320932B - Output driver for dynamic random access memory - Google Patents

Output driver for dynamic random access memory Download PDF

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Publication number
TWI320932B
TWI320932B TW095124005A TW95124005A TWI320932B TW I320932 B TWI320932 B TW I320932B TW 095124005 A TW095124005 A TW 095124005A TW 95124005 A TW95124005 A TW 95124005A TW I320932 B TWI320932 B TW I320932B
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unit
pull
conversion rate
output
output driver
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TW095124005A
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Chinese (zh)
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TW200713315A (en
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Kwang-Myoung Rho
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Description

1320932 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種輸出驅動器；且更明確地說，係關於 一種用於輸出一穩定位準之輸出訊號的輸出驅動器。 【先前技術】 隨著一包括於一動態隨機存取記憶體（DRAM)中之輸出 驅動器的驅動強度增大，該DRAM與一連接至該DRAM之 系統之間的資料傳輸速度變得更快。為了確保一高速資料 傳輸，要求輸出驅動器之轉換率（slew rate)大於一預定最 J值而與製程、電壓及溫度的變化無關。若輸出驅動器 之轉換率過大，則輸出驅動器之電流耗用突然增大。另 外，當轉換率過大時’由DRAM與系統之間之不完美終端 所引起的反射亦增大。因此，一輸出訊號具有不穩定值。 由於此原因，輸出驅動器之轉換率需要小於一預定最大 值。換言之，要求即使當諸如製程、電壓及溫度之環境條 件變化時，輸出驅動器之轉換率維持於一在最小值與最大 值之間變動的值，以輸出一穩定輸出訊號。 圖1係一習知輸出驅動器的方塊圖。 如所展示，輸出驅動器包括一預上拉驅動單元2〇，其用 於響應於-預上拉驅動訊號pre_UP而執行_預上拉驅動操 作；一預下拉驅動單元3〇,其用於響應於_預下拉驅動訊 號pre_DNb而執行一預下拉驅動操作；及—驅動單元w， 其用於響應於預上拉驅動單元20及預下拉驅動單元％之輸 出而驅動一輸出訊號。 j 112691.doc 1320932 晶體PMl、NMl、NM2及PM3與輸出節點A、B及c之間的 被動/0件（意即，電阻器R1至R4)，以減小輸出驅動器之轉 換率的變化。吾人已熟知諸如電阻器之被動元件比諸如一 MOS電晶體之主動元件較少受製程、電壓及溫度的變化之 影響。因此，藉由包括被動元件（例如，電阻器旧至尺斗）， 輸出驅動器之轉換率的變化可稍微減小。在此情況下，因 為電阻器R1至R4，所以輸出驅動器之轉換率減小。轉換 率之減小可藉由增大NMOS電晶體之尺寸來補償。 雖然可能藉由在MOS電晶體與輸出節點之間組態被動元 件來減小輸出驅動器之轉換率的變化，但輸出驅動器之轉 換率仍根據製程、電壓及溫度而變化。 【發明内容】 因此，本發明之一目標係提供一種輸出一穩定位準之輸 出訊號的輸出驅動器β 根據本發明之一態樣，提供一種輸出驅動器其包括： 一預上拉驅動單元，其經組態以響應於一預上拉驅動訊號 而執仃一預上拉驅動操作；一預下拉驅動單元，其經組態 以響應於一預下拉驅動器訊號而執行一預下拉驅動操作； 一驅動單元，其經組態以響應於該預上拉驅動單元及該預 二拉驅動單元之輸出而執行—驅動操作；及—轉換率補償 單元，其經組態以感測該驅動單元之轉換率的變化，藉此 控制預上拉驅動單元及預下拉驅動單元。預上拉驅動單元 及預下拉驅動單元之驅動強度係可調的。 根據本發明之另一態樣，提供一種輸出驅動器，其包 112691.doc 1320932 轉換率補償單元，其經組態以感測輸出驅動器之轉 換率的變化’藉此產生複數個轉換率補償訊號；一預上拉 驅動單元’其經組態以響應於該複數個轉換率補償訊號而 執行預上拉操作；一預下拉驅動單元’其經組態以響應 於該複數個轉換率補償訊號而執行一預下拉操作；及一驅 動單元’其經組態以響應於該預上拉驅動單元及該預下拉 驅動單元的輪出而驅動一輸出訊號。 【實施方式】1320932 IX. Description of the Invention: [Technical Field] The present invention relates to an output driver; and more particularly to an output driver for outputting a stable level of output signal. [Prior Art] As the driving strength of an output driver included in a dynamic random access memory (DRAM) increases, the data transfer speed between the DRAM and a system connected to the DRAM becomes faster. In order to ensure a high speed data transmission, the slew rate of the output driver is required to be greater than a predetermined maximum J value regardless of variations in process, voltage and temperature. If the conversion rate of the output driver is too large, the current consumption of the output driver suddenly increases. In addition, when the conversion rate is too large, the reflection caused by the imperfect terminal between the DRAM and the system also increases. Therefore, an output signal has an unstable value. For this reason, the conversion rate of the output driver needs to be less than a predetermined maximum value. In other words, it is required that the output driver's slew rate is maintained at a value that varies between a minimum value and a maximum value even when environmental conditions such as process, voltage, and temperature change to output a stable output signal. Figure 1 is a block diagram of a conventional output driver. As shown, the output driver includes a pre-pull drive unit 〇 for performing a _ pre-pull drive operation in response to the pre-pull drive signal pre_UP; a pre-pull drive unit 〇 for responding to _ pre-pull down the drive signal pre_DNb to perform a pre-pull-down drive operation; and - a drive unit w for driving an output signal in response to the output of the pre-pull drive unit 20 and the pre-pull drive unit %. j 112691.doc 1320932 Passive / 0 pieces (ie, resistors R1 to R4) between crystals PM1, NM1, NM2, and PM3 and output nodes A, B, and c to reduce the change in the conversion ratio of the output driver. It is well known that passive components such as resistors are less susceptible to variations in process, voltage, and temperature than active components such as a MOS transistor. Thus, by including a passive component (eg, a resistor old to a bucket), the change in slew rate of the output driver can be slightly reduced. In this case, since the resistors R1 to R4, the conversion ratio of the output driver is reduced. The reduction in conversion rate can be compensated by increasing the size of the NMOS transistor. Although it is possible to reduce the change in the slew rate of the output driver by configuring a passive element between the MOS transistor and the output node, the conversion rate of the output driver varies depending on the process, voltage, and temperature. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an output driver that outputs a stable level output signal. According to an aspect of the present invention, an output driver includes: a pre-pull drive unit Configuring to perform a pre-pull drive operation in response to a pre-pull drive signal; a pre-pull drive unit configured to perform a pre-pull drive operation in response to a pre-pull drive signal; Configuring, in response to the output of the pre-pull drive unit and the pre-two pull drive unit, performing a drive operation; and - a conversion rate compensation unit configured to sense a conversion rate of the drive unit The change thereby controls the pre-pull drive unit and the pre-pull drive unit. The drive strength of the pre-pull drive unit and the pre-pull drive unit is adjustable. In accordance with another aspect of the present invention, an output driver is provided that includes a 112691.doc 1320932 slew rate compensation unit configured to sense a change in a slew rate of an output driver 'by generating a plurality of slew rate compensation signals; a pre-pull drive unit configured to perform a pre-pull operation in response to the plurality of conversion rate compensation signals; a pre-pull drive unit configured to execute in response to the plurality of conversion rate compensation signals a pre-pull operation; and a drive unit configured to drive an output signal in response to the rotation of the pre-pull drive unit and the pre-pull drive unit. [Embodiment]

下文中將參看隨附圖式詳細描述一根據本發明的用於一 半導體記憶體裝置中之輸出驅動器。 圖2係一根據本發明之一實施例之輸出驅動器的方塊 圖0 如所展示，輸出驅動器包括一驅動單元1〇〇、一預上拉 驅動單元200、一預下拉驅動單元300及一轉換率補償單元 400 ^轉換率補償單元4〇〇感測環境條件（例如，製程、電 壓及溫度）’且產生轉換率補償訊號EN[1:3]及ENb[l:3]。 在轉換率補償訊號EN[1:3]及ENb[l:3]之控制下，預上拉驅 動單元200響應於一預上拉驅動訊號pre_Up而執行一預上 拉驅動操作。在轉換率補償訊號EN[L3]&ENb[1:3]之控制 下，預下拉驅動單元3〇〇響應於一預下拉驅動訊號pre_DNb 而執行一預下拉驅動操作。驅動單元1〇〇響應於分別自預 上拉驅動單元200及預下拉驅動單元3〇〇輸出之一上拉驅動 訊號UPb及一下拉驅動訊號DN，而驅動一輸出訊號。如上 文所提及，藉由根據環境條件之轉換率補償訊號en[i 3] 112691.doc 1320932 及ENb[ 1:3]來控制預上拉驅動單元200及預下拉驅動單元 300之驅動強度。DETAILED DESCRIPTION OF THE INVENTION An output driver for use in a semiconductor memory device in accordance with the present invention will now be described in detail with reference to the accompanying drawings. 2 is a block diagram of an output driver according to an embodiment of the present invention. As shown, the output driver includes a driving unit 1 , a pre-pull driving unit 200 , a pre-pull driving unit 300 , and a conversion rate. The compensation unit 400 ^ conversion rate compensation unit 4 〇〇 senses environmental conditions (eg, process, voltage, and temperature) and generates conversion rate compensation signals EN[1:3] and ENb[l:3]. Under the control of the conversion rate compensation signals EN[1:3] and ENb[l:3], the pre-pull drive unit 200 performs a pre-pull drive operation in response to a pre-pull drive signal pre_Up. Under the control of the conversion rate compensation signal EN[L3]&ENb[1:3], the pre-pull drive unit 3 performs a pre-pull-down driving operation in response to a pre-pull drive signal pre_DNb. The driving unit 1 drives an output signal in response to one of the pull-up driving signal UPb and the pull-up driving signal DN from the pre-pull driving unit 200 and the pre-pull driving unit 3, respectively. As mentioned above, the driving strengths of the pre-pull driving unit 200 and the pre-pull driving unit 300 are controlled by the conversion rate compensation signals en[i 3] 112691.doc 1320932 and ENb[ 1:3] according to environmental conditions.

驅動單元100包括一第四PMOS電晶體PM4、一第四 NMOS電晶體NM4，以及一第五及一第六電阻器R5及R6。 連接於一電源電壓VDDQ端子與第五電阻器R5之間的第四 PMOS電晶體PM4在其閘極處接收上拉驅動訊號UPb。第五 電阻器R5連接於第四PMOS電晶體PM4與一輸出節點D之 間。連接於一接地電壓VSSQ端子與第六電阻器R6之間的 第四NMOS電晶體NM4在其閘極處接收下拉驅動訊號DN。 第六電阻器R6連接於第四NMOS電晶體NM4與輸出節點D 之間。 圖3係描繪圖2中所示之轉換率補償單元400的示意電路 圖。The driving unit 100 includes a fourth PMOS transistor PM4, a fourth NMOS transistor NM4, and a fifth and sixth resistors R5 and R6. The fourth PMOS transistor PM4 connected between a power supply voltage VDDQ terminal and the fifth resistor R5 receives the pull-up drive signal UPb at its gate. The fifth resistor R5 is connected between the fourth PMOS transistor PM4 and an output node D. The fourth NMOS transistor NM4 connected between a ground voltage VSSQ terminal and the sixth resistor R6 receives the pull-down driving signal DN at its gate. The sixth resistor R6 is connected between the fourth NMOS transistor NM4 and the output node D. FIG. 3 is a schematic circuit diagram depicting the conversion rate compensation unit 400 shown in FIG. 2.

如所展示，轉換率補償單元400包括一轉換率感測單元 420、一數位化單元440及一訊號產生單元460。轉換率感 測單元420包括一組態相同於預上拉驅動單元200及預下拉 驅動單元300之組態的MOS電晶體組態，且感測該MOS電 晶體之轉換率根據製程、電壓及溫度之變化的變化。數位 化單元440劃分轉換率感測單元420之一輸出。接收數位化 單元440之輸出的訊號產生單元460輸出轉換率補償訊號 EN[1:3]及 ENb[l:3]。 轉換率感測單元420係用串聯連接於一内部電壓VINT端 子與接地電壓VSSQ端子之間的複數個電晶體予以實施。 該等電晶體之一者係一 MOS電晶體，其相同於組態於預上 112691.doc 1320932As shown, the conversion rate compensation unit 400 includes a conversion rate sensing unit 420, a digitizing unit 440, and a signal generating unit 460. The conversion rate sensing unit 420 includes a MOS transistor configuration configured in the same configuration as the pre-pull drive unit 200 and the pre-pull drive unit 300, and senses the conversion rate of the MOS transistor according to the process, voltage, and temperature. Changes in change. The digitizing unit 440 divides the output of one of the conversion rate sensing units 420. The signal generating unit 460 that receives the output of the digitizing unit 440 outputs the conversion rate compensation signals EN[1:3] and ENb[l:3]. The conversion rate sensing unit 420 is implemented by a plurality of transistors connected in series between an internal voltage VINT terminal and a ground voltage VSSQ terminal. One of the transistors is a MOS transistor, which is identical to the configuration in the previous 112691.doc 1320932

拉驅動單元200及預下拉驅動單元3 00中的電晶體。圖3中 所示之轉換率感測單元420包括串聯連接之一第七電阻器 R7、一第五NMOS電晶體NM5及一第六NMOS電晶體 NM6。第七電阻器R7連接於内部電壓VINT端子與一輸出 節點之間。在其閘極處接收一外部電源電壓VDD的第五 NMOS電晶體NM5連接於輸出節點與第六NMOS電晶體 NM6之間。在其閘極處接收一感測訊號SEN的第六NMOS 電晶體NM6連接於第五NMOS電晶體NM5與接地電壓VSSQ 端子之間。第五NMOS電晶體NM5相同於包括於組態於預 上拉驅動單元200及預下拉驅動單元300中的NMOS電晶 體。The driving unit 200 and the transistor in the pre-pull driving unit 300 are pulled. The slew rate sensing unit 420 shown in Fig. 3 includes a seventh resistor R7, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6 connected in series. The seventh resistor R7 is connected between the internal voltage VINT terminal and an output node. A fifth NMOS transistor NM5 receiving an external power supply voltage VDD at its gate is connected between the output node and the sixth NMOS transistor NM6. A sixth NMOS transistor NM6 receiving a sense signal SEN at its gate is connected between the fifth NMOS transistor NM5 and the ground voltage VSSQ terminal. The fifth NMOS transistor NM5 is identical to the NMOS transistor included in the pre-pull driving unit 200 and the pre-pull driving unit 300.

一供應至轉換率感測單元420之内部電壓VINT維持一預 定穩定位準。因此，轉換率感測單元420能可靠地感測外 部電源電壓VDD之位準而不受環境條件（例如，製程、電 壓及溫度）之影響。感測訊號SEN僅當達到一適當臨限位準 時啟用轉換率感測單元420，以節省轉換率感測單元420的 電流耗用。 數位化單元440包括一參考電壓產生器442及一比較單元 444。參考電壓產生器442輸出複數個參考電壓。比較單元 444將參考電壓之每一者與轉換率感測單元420之輸出比 較。參考電壓產生器442包括複數個電阻器R8、R9及 R10，其串聯連接於内部電壓VINT端子與接地電壓VSSQ 端子之間。比較單元444包括複數個差動放大器DAM1及 DAM2。每一差動放大器接收參考電壓之一者及轉換率感 11269i.doc -10- 1320932 測單元420之輸出。 訊號產生單元460響應於數位化單元440之複數個輸出訊 號而輸出轉換率補償訊號EN[1:3]及ENb[l:3]。訊號產生單 元460可用通用邏輯區塊及鎖存器來實施。An internal voltage VINT supplied to the conversion rate sensing unit 420 maintains a predetermined stable level. Therefore, the conversion rate sensing unit 420 can reliably sense the level of the external power supply voltage VDD without being affected by environmental conditions such as process, voltage, and temperature. The sensing signal SEN enables the slew rate sensing unit 420 only when an appropriate threshold level is reached to save current consumption of the slew rate sensing unit 420. The digitizing unit 440 includes a reference voltage generator 442 and a comparing unit 444. The reference voltage generator 442 outputs a plurality of reference voltages. Comparison unit 444 compares each of the reference voltages to the output of slew rate sensing unit 420. The reference voltage generator 442 includes a plurality of resistors R8, R9, and R10 connected in series between the internal voltage VINT terminal and the ground voltage VSSQ terminal. Comparison unit 444 includes a plurality of differential amplifiers DAM1 and DAM2. Each of the differential amplifiers receives one of the reference voltages and the output of the sense unit 420 11269i.doc -10- 1320932. The signal generating unit 460 outputs the conversion rate compensation signals EN[1:3] and ENb[l:3] in response to the plurality of output signals of the digitizing unit 440. Signal generation unit 460 can be implemented with general purpose logic blocks and latches.

轉換率補償單元400可經由第五NMOS電晶體NM5來感測 預上拉驅動單元200及預下拉驅動單元3 00之轉換率的變 化。當外部電源電壓VDD之位準較低且MOS電晶體之驅動 強度較小時，已啟用之轉換率補償訊號EN[1:3]及ENb[l:3] 的數目增大。反之，當外部電源電壓VDD之位準較高且 MOS電晶體之驅動強度較大時，已啟用之轉換率補償訊號 EN[ 1:3]及ENb[ 1:3]的數目減小。另外，數位化單元440中 之電阻器及比較器的數目可根據所要之轉換率補償單元 4 0 0的敏感性而變化。 圖4係根據本發明之一實施例之描繪訊號產生單元的示 意電路圖。The conversion rate compensation unit 400 can sense a change in the conversion ratio of the pre-pull drive unit 200 and the pre-pull drive unit 300 through the fifth NMOS transistor NM5. When the level of the external power supply voltage VDD is low and the driving strength of the MOS transistor is small, the number of enabled conversion rate compensation signals EN[1:3] and ENb[l:3] increases. Conversely, when the level of the external power supply voltage VDD is high and the driving strength of the MOS transistor is large, the number of enabled conversion rate compensation signals EN[1:3] and ENb[1:3] is reduced. Additionally, the number of resistors and comparators in the digitizing unit 440 can vary depending on the sensitivity of the desired slew rate compensation unit 400. 4 is a schematic circuit diagram of a depicted signal generating unit in accordance with an embodiment of the present invention.

訊號產生單元460包括一邏輯單元462、一鎖存器單元 464，以及複數個傳輸閘TGI、TG2及TG3。邏輯單元462 邏輯地將數位化單元440之輸出COMP_OUTl及 COMP_OUT2與外部電源電壓VDD組合並輸出複數個邏輯 訊號。鎖存器單元464鎖存邏輯訊號並輸出轉換率補償訊 號EN[1:3]及ENb[l:3]。複數個傳輸閘TGI、TG2及TG3之 每一者響應於一轉換率控制訊號對SR_LAT及SR_LATB而 傳輸對應之邏輯訊號。 訊號產生單元460接收兩個輸出COMP_OUTl及 112691.doc 1320932The signal generating unit 460 includes a logic unit 462, a latch unit 464, and a plurality of transmission gates TGI, TG2, and TG3. The logic unit 462 logically combines the outputs COMP_OUT1 and COMP_OUT2 of the digitizing unit 440 with the external power supply voltage VDD and outputs a plurality of logic signals. The latch unit 464 latches the logic signal and outputs the conversion rate compensation signals EN[1:3] and ENb[l:3]. Each of the plurality of transmission gates TGI, TG2, and TG3 transmits a corresponding logic signal in response to a conversion rate control signal pair SR_LAT and SR_LATB. The signal generating unit 460 receives two outputs COMP_OUT1 and 112691.doc 1320932

COMP—OUT2並輸出三對轉換率補償訊號EN[1:3]及 ENb[l:3]。邏輯單元462包括三個「反及」（NAND)閘 ND1、ND2及ND3 »第一「反及」閘ND1通常經由兩個輸 入端子接收外部電源電壓VDD並邏輯地將其組合，意即， 外部電源電壓VDD經由第一「反及」閘ND1之兩個輸入端 子而輸入。第二「反及」閘ND2邏輯地將外部電源電壓 VDD與數位化單元440之第二輸出COMP_OUT2組合。第三 「反及」閘ND3邏輯地將外部電源電壓VDD與數位化單元 440之第一輸出COMP_OUTl組合》鎖存器單元464包括複 數個鎖存器，其每一者鎖存對應之邏輯訊號。響應於一邏 輯高位準之轉換率控制訊號SRJLAT而更新鎖存器單元464 中所鎖存之值。 表1展示圖4中所示之訊號產生單元的操作》 表1COMP-OUT2 outputs three pairs of conversion rate compensation signals EN[1:3] and ENb[l:3]. Logic unit 462 includes three "NAND" gates ND1, ND2, and ND3. The first "reverse" gate ND1 typically receives the external supply voltage VDD via two input terminals and logically combines it, that is, external The power supply voltage VDD is input via the two input terminals of the first "reverse" gate ND1. The second "reverse" gate ND2 logically combines the external supply voltage VDD with the second output COMP_OUT2 of the digitizing unit 440. The third "reverse" gate ND3 logically combines the external supply voltage VDD with the first output COMP_OUT1 of the digitizing unit 440. The latch unit 464 includes a plurality of latches, each of which latches a corresponding logic signal. The value latched in latch unit 464 is updated in response to a logic high level slew rate control signal SRJLAT. Table 1 shows the operation of the signal generating unit shown in Fig. 4" Table 1

VDD COMP一OUT1 COMP_OUT2 EN[1] EN[2] EN[3] 低 Η H H H H 中 L H H H L Tfj L L H L LVDD COMP-OUT1 COMP_OUT2 EN[1] EN[2] EN[3] Low Η H H H H L H H H L Tfj L L H L L

根據包括於轉換率感測單元420及數位化單元440中的 NMOS電晶體之尺寸及電阻器之電阻而將外部電源電壓 VDD分類為三個位準，意即，"低"、"中"及"高"。若外部 電源電壓VDD具有一"低”位準，則數位化單元440之第一 及第二輸出COMP-OUT1及COMP_OUT2皆具有一邏輯高位 準。若外部電源電壓VDD具有"中”位準，則第一輸出 112691.doc -1?· 1^20932 拉驅動單元200之電路類似的電路。因此，為了避免冗 餘，將不再對其進行詳細描述。 當外部電源電壓VDD之位準較低且MOS電晶體之驅動強 度較小時（意即，當轉換率較小時），自轉換率補償單元4〇〇 輸出的已啟用之轉換率補償訊號EN[1:3]&ENb[1:3]的數目The external power supply voltage VDD is classified into three levels according to the size of the NMOS transistor included in the conversion rate sensing unit 420 and the digitizing unit 440 and the resistance of the resistor, that is, "low"," Medium " &"high". If the external power supply voltage VDD has a "low" level, the first and second outputs COMP-OUT1 and COMP_OUT2 of the digitizing unit 440 have a logic high level. If the external power supply voltage VDD has a "medium" Then, the first output 112691.doc -1?·1^20932 pulls the circuit similar to the circuit of the driving unit 200. Therefore, in order to avoid redundancy, it will not be described in detail. When the level of the external power supply voltage VDD is low and the driving strength of the MOS transistor is small (that is, when the conversion rate is small), the enabled conversion rate compensation signal EN of the self-conversion rate compensation unit 4〇〇 is output. Number of [1:3]&ENb[1:3]

增大。因此，包括於預上拉驅動單元2〇〇及預下拉驅動單 元300中的開啟之反轉器的數目增大。因此，輸出驅動器 之一輸出訊號的轉換率增大。當外部電源電壓VDD之位準 較高且MOS電晶體之驅動強度較大時（意即，當轉換率較 大時），自轉換率補償單元4〇〇輸出的已啟用之轉換率補償 訊號EN[ 1:3]及ENb[ 1:3]的數目減小。因此，開啟之反轉器 的數目減小。因此，輸出驅動器之輸出訊號的轉換率減 小。以此方式，輸出訊號之轉換率經穩定調節以具有一在 一預定範圍中的值。Increase. Therefore, the number of inverters included in the pre-pull driving unit 2A and the pre-pull driving unit 300 is increased. Therefore, the conversion rate of the output signal of one of the output drivers increases. When the level of the external power supply voltage VDD is high and the driving strength of the MOS transistor is large (that is, when the conversion rate is large), the enabled conversion rate compensation signal EN of the self-conversion rate compensation unit 4〇〇 is output. The number of [ 1:3] and ENb[ 1:3] is reduced. Therefore, the number of inverters that are turned on is reduced. Therefore, the conversion rate of the output signal of the output driver is reduced. In this way, the conversion rate of the output signal is stably adjusted to have a value within a predetermined range.

在圖3中所示之實施例中，轉換率補償單元4〇〇在轉換率 感測早元420中包括NMOS電晶體NM5。然而，在另一實施 例中’轉換率感測單元420可包括一 pm〇s電晶體，其與包 括於預上拉驅動單元200及預下拉驅動單元3〇〇中之pM〇s 電晶體相同。 根據本發明之輸出驅動器根據環境條件（例如，製程、 電壓及溫度）之變化而適當地調節預上拉驅動單元及預下 拉驅動單元的驅動強度。因此’輸出訊號之轉換率的變化 保持於一預定範圍内。因此’本發明改良輸出驅動器之可 靠性及訊號完整性。 112691.(10-. 1320932 400 轉換率補償單元 420 轉換率感測單元 440 數位化單元 442 參考電壓產生器 444 比較單元 . 460 訊號產生單元 462 邏輯單元 464 鎖存器單元 • DAM1 差動放大器 DAM2 差動放大器 ND1 「反及」（NAND)閘 ND2 「反及」（NAND)閘 ND3 「反及」（NAND)閘 NM1 第一 NMOS電晶體/MOS電晶體 NM2 第二NMOS電晶體/MOS電晶體 NM3 第三NMOS電晶體 ^ NM4 第四NMOS電晶體 - NM5 第五NMOS電晶體/NMOS電晶體 NM6 第六NMOS電晶體 NM7 第七NMOS電晶體 NM8 第八NMOS電晶體/NMOS電晶體 NM9 第九NMOS電晶體/NMOS電晶體 NM10 第十NMOS電晶體 NM11 第十一 NMOS電晶體/NMOS電晶體 112691.doc -17- 1320932In the embodiment shown in FIG. 3, the conversion rate compensation unit 4A includes an NMOS transistor NM5 in the conversion rate sensing early element 420. However, in another embodiment, the 'conversion rate sensing unit 420 may include a pm〇s transistor that is the same as the pM〇s transistor included in the pre-pull drive unit 200 and the pre-pull drive unit 3〇〇. . The output driver according to the present invention appropriately adjusts the driving strength of the pre-pull driving unit and the pre-drawing driving unit in accordance with changes in environmental conditions (e.g., process, voltage, and temperature). Therefore, the change in the conversion rate of the output signal is maintained within a predetermined range. Thus, the present invention improves the reliability and signal integrity of the output driver. 112691. (10-. 1320932 400 conversion rate compensation unit 420 conversion rate sensing unit 440 digital unit 442 reference voltage generator 444 comparison unit. 460 signal generation unit 462 logic unit 464 latch unit • DAM1 differential amplifier DAM2 difference Active Amplifier ND1 "Reverse" (NAND) Gate ND2 "Reverse" (NAND) Gate ND3 "Reverse" (NAND) Gate NM1 First NMOS transistor / MOS transistor NM2 Second NMOS transistor / MOS transistor NM3 Third NMOS transistor ^ NM4 Fourth NMOS transistor - NM5 Fifth NMOS transistor / NMOS transistor NM6 Sixth NMOS transistor NM7 Seventh NMOS transistor NM8 Eight NMOS transistor / NMOS transistor NM9 Ninth NMOS Crystal/NMOS transistor NM10 Tenth NMOS transistor NM11 Eleventh NMOS transistor/NMOS transistor 112691.doc -17- 1320932

NM12 第十二NMOS電晶體/NMOS電盖 PM1 第一 PMOS電晶體/MOS電晶體 PM2 第二PMOS電晶體 PM3 第三PMOS電晶體/MOS電晶體 PM4 第四PMOS電晶體 PM5 第五PMOS電晶體 PM6 第六PMOS電晶體/PMOS電晶體 PM7 第七PMOS電晶體/PMOS電晶體 PM8 第八PMOS電晶體 PM9 PMOS電晶體 PM10 第十PMOS電晶體/PMOS電晶體 R1 第一電阻器/電阻器 R2 第二電阻器/電阻器 R3 第三電阻器/電阻器 R4 第四電阻器/電阻器 R5 第五電阻器 R6 第六電阻器 R7 第七電阻器 R8 電阻器 R9 電阻器 RIO 電阻器 112691.doc -18 -NM12 Twelfth NMOS transistor/NMOS cap PM1 First PMOS transistor/MOS transistor PM2 Second PMOS transistor PM3 Third PMOS transistor/MOS transistor PM4 Fourth PMOS transistor PM5 Fifth PMOS transistor PM6 Sixth PMOS transistor/PMOS transistor PM7 Seventh PMOS transistor/PMOS transistor PM8 Eight PMOS transistor PM9 PMOS transistor PM10 Tenth PMOS transistor/PMOS transistor R1 First resistor/resistor R2 Second Resistor / Resistor R3 Third Resistor / Resistor R4 Fourth Resistor / Resistor R5 Fifth Resistor R6 Sixth Resistor R7 Seventh Resistor R8 Resistor R9 Resistor RIO Resistor 112691.doc -18 -

Claims (1)

1320932 第095124005號專利申請案 中文申請專利範圍替換本(98年1〇月） 十、申請專利範圍： 1. 一種輸出驅動器，其包含： 一預上拉驅動單元 作； 其經組態以執行— 預上拉驅動操 作了預下拉驅動單元，其經組態以執行—預下拉驅動操 ▲ -驅動單元，其經組態以響應於該預上拉職單元及 該預下拉驅動單元之輸出而執行一驅動操作；及 一補償單元，其經組態以感測該預上拉驅動單元及該 預下拉驅動單元之驅動強度的變化，以控制該預上拉驅 動單兀及該預下拉驅動單元的該等驅動操作，其中該補 償單元包含： 轉換率感測單元，其經組態以感測根據環境條件的 該驅動單元之該轉換率的變化；及 一訊號產生單元’其經組態以基於該轉換率之該變化 而產生複數個轉換率補償訊號。 2. 如請求項1之輸出驅動器，其中該預上拉驅動單元及該 預下拉驅動單元之該等驅動強度響應於自該補償單元輪 出的該轉換率補償訊號而穩定化。 3. 如請求項2之輪出驅動器，其中該預上拉驅動單元包 含： 一主預上拉驅動單元，其經組態以執行一主驅動操 作；及 一補充預上拉驅動單元，其經組態以調節該預上拉藤 112691-981007.DOC 動單元之該驅動強度。 如請求項3之輸出驅動器，其中該預下拉驅動單元包 含： 一主預下拉驅動單元，其經組態以執行該主驅動操 作；及 一補充預下拉驅動單元，其經組態以調節該預下拉驅 動單元之該驅動強度。 如請求項4之輸出驅動器，其中該補償單元包含： 一數位化單元，其經組態以數位化該轉換率感測單元 之一輸出； 其中該轉換率感測單元包含一 MOS電晶體；且 该預上拉驅動單元及該預下拉驅動單元之每一者包含 —MOS電晶體。 6.如請求項5之輸出驅動器，其中該轉換率感測單元、該 預上拉驅動單元及預下拉驅動單元之該等MOS電晶體為 相同組態。 •如請求項6之輸出驅動器，其中該轉換率感測單元包^ 串聯連接於一第一内部電源電愿端子與一接地電壓則 之間的禝數個電阻器，並經由複數個連接節點之一者赛 f 一輸出訊號，其中該複數個電阻器之—者係該娜^ 曰曰體，其之一閘極耦接至一外部電源電壓。 8_ :請求項7之輸出驅動器，其中該轉換率感測單元包 第—被動元件電阻器 其連接於該第一内部電源電 Π269卜981007.doc -2- 1320932 壓端子與一第一輸出節點之間； -第-NMOS電晶體’其連接至該第一輸出節點，該 第一 NM0S電晶體之—閘極純至—外部電源電壓；及 一第二NMOS電晶體，其連接於該第一職⑽電晶體與 該接地電壓端子之間’該第刪電晶體之_問極輕 接至一感測訊號， 其中該感測訊號僅當達到一適當臨限位準時啟用囔轉 換率感測單元，藉此最小化該轉換率感測單元之電：耗 用。 9. 如請求項7之輸出驅動器， 態相同於該主預上拉驅動 電晶體的組態。 其中該第一 NMOS電晶體的組 單元及該主預下拉驅動單元之 10.如請求項7之輸出駆動器’纟中該轉換率感測單元之該 電晶體係一 PMOS電晶體。 11·如請求項9之輸出驅動器’其中該數位化單元包括：1320932 Patent application No. 095124005 Replacement of patent application scope (98 years 1 month) X. Patent application scope: 1. An output driver comprising: a pre-pull drive unit; configured to perform - The pre-pull drive operates a pre-pull drive unit configured to perform a pre-pull drive operation-drive unit configured to execute in response to the pre-pull-up unit and the output of the pre-pull drive unit a driving operation; and a compensation unit configured to sense a change in driving strength of the pre-pull driving unit and the pre-pull driving unit to control the pre-pull driving unit and the pre-pull driving unit The driving operation, wherein the compensation unit comprises: a conversion rate sensing unit configured to sense a change in the conversion rate of the driving unit according to an environmental condition; and a signal generating unit configured to be based on The change in the conversion rate produces a plurality of conversion rate compensation signals. 2. The output driver of claim 1, wherein the drive strengths of the pre-pull drive unit and the pre-pull drive unit are stabilized in response to the conversion rate compensation signal rotated from the compensation unit. 3. The turn-out driver of claim 2, wherein the pre-pull drive unit comprises: a main pre-pull drive unit configured to perform a main drive operation; and a supplemental pre-pull drive unit Configured to adjust the drive strength of the pre-upper vine 112691-981007.DOC moving unit. The output driver of claim 3, wherein the pre-pull drive unit comprises: a master pre-pull drive unit configured to perform the main drive operation; and a supplemental pre-pull drive unit configured to adjust the pre- Pull down the drive strength of the drive unit. The output driver of claim 4, wherein the compensation unit comprises: a digitizing unit configured to digitize an output of the conversion rate sensing unit; wherein the conversion rate sensing unit comprises a MOS transistor; Each of the pre-pull drive unit and the pre-pull drive unit includes a MOS transistor. 6. The output driver of claim 5, wherein the MOS transistors of the conversion rate sensing unit, the pre-pull drive unit, and the pre-pull drive unit are of the same configuration. The output driver of claim 6, wherein the conversion rate sensing unit is connected in series to a plurality of resistors between a first internal power supply terminal and a ground voltage, and is connected to the plurality of connection nodes. One match f is an output signal, wherein the plurality of resistors are the ones of the body, one of which is coupled to an external power supply voltage. 8_: The output driver of claim 7, wherein the conversion rate sensing unit includes a passive component resistor connected to the first internal power supply 269 981007.doc -2- 1320932 pressure terminal and a first output node a first NMOS transistor connected to the first output node, the gate of the first NMOS transistor being gated to an external power supply voltage, and a second NMOS transistor connected to the first node (10) between the transistor and the ground voltage terminal, the light is connected to a sensing signal, wherein the sensing signal is enabled only when a proper threshold level is reached, Thereby minimizing the electricity of the conversion rate sensing unit: consumption. 9. As in the output driver of request 7, the state is the same as the configuration of the main pre-pull drive transistor. The group unit of the first NMOS transistor and the main pre-pull drive unit 10. The output transistor of the request item 7 is the PMOS transistor of the electro-transformation system of the conversion rate sensing unit. 11. The output driver of claim 9 wherein the digitizing unit comprises: 一參考電壓提供器 壓；及 其經組態以提供複數個參考電 t匕权早兀，其 經組態以比較該等參考電壓之每一 與該轉換率感測單元之該輸出。 12. 如明求項11之輸出驅動s，其甲該參考電屡提供器包括 串聯連接於該第—内部電源㈣端子與該接地電麼端子 之間的複數個電阻器，哕箄兩 “矿 且3等电阻态之間之連接節點處 的電壓提供該等參考電壓。 13. 如”月求項12之輪出驅動 立 。。― /、于这比較早凡包括複數個 112691-981007.DOC 14. 差動放大g ’其經M接以接收參考電屢之-者及該轉換 率感測單元的該輪出。 如請求項13之輸出驅動器’其中該驅動單元包括： 第PMOS包晶體，其連接至—第二内部電源電壓 端:’在其閘極處接收該預上拉驅動單元之一輸出； 第一被動7L件電阻器，其連接於該第一 pM〇s電晶 體與一第二輸出節點之間； 第一 NMOS電晶體，其連接至該接地電壓端子，在 其閘極處接收該預下拉驅動單元之_輸出；及 第一被動元件電阻器，其連接於該第三nm〇s電晶 體與該第二輸出節點之間。 15. 16. 如請求項6之輸出驅動器，其中該驅動單元包括： 電源電壓端子並接收該 一 PMOS電晶體，其連接至一 預上拉驅動單元之一輸出； 被動元件電阻器，其連接於該PMOS電晶體與 一輸出節點之間； NMOS電明體，其連接至一接地電壓端子並接收該 預下拉驅動單元之一輸出；及 第一被動兀件電阻器，其連接於該NM〇s電晶體與 該輸出節點之間。 如π求項15之輸出驅動||，其中該主預上拉驅動單元包 括： 主預上拉驅動反轉器單元，其經組態以將一第一驅 動訊號反轉，藉此輸出一上拉驅動訊號；及 112691^98l〇〇7.D〇c -4- 1320932 -主驅動電壓提供器，其經組態以響應於該複數個轉 換率補償訊號，而選擇性地將—驅動電壓提供㈣㈣ 上拉驅動反轉器單元。 Λ 17. 如請求項16之輸出驅動器，其中該主預上拉驅動反轉写 單元包括： ° - PMOS電晶體，其在其閘極處接收該第—驅動訊 號；及 ° —NM〇S電晶體，其在其閘極處接收該第-驅動訊 ，號。 ° 18. 如請求項17之輸出驅動器，其中該主驅動電壓提供器包 括： 一PMOS電晶體，其在其閘極處接收對應的經反轉之 轉換率補償訊號；及 一 NMOS電晶體，其在其閘極處接收對應之轉換率補 償訊號。 _ 19.如請求項18之輸出焉區動器，其中該補充預上拉驅動單元 包括： 一補充預上拉驅動反轉器單元，其經組態以將一第一 驅動訊號反轉，藉此輸出一上拉驅動訊號；及 一補充驅動電壓提供器，其經組態以響應於該複數個 轉換率補償訊號，而選擇性地將一驅動電壓提供至該補 充預上拉驅動反轉器單元。 20.如請求項19之輸出驅動器，其中該補充預上拉驅動反轉 器單元包括： 112691-981007.DOC 複數個PMOS電晶體，其彼此並聯連接於該驅動電壓 提供器與一輸出節點之間，每一 PMOS電晶體在其閘極 處接收該第一驅動訊號；及 複數個NMOS電晶體，其彼此並聯連接於該輸出節點 與該驅動電壓提供器之間，每一 NMOS電晶體接收該第 一驅動訊號。 21. 如請求項20之輸出驅動器，其中該補充驅動電壓提供器 包括： 複數個PMOS電晶體，其連接於該電源電壓端子與包 括於該補充預上拉驅動反轉器單元中的該複數個PMOS 電晶體之間，每一 PMOS電晶體在其閘極處接收對應的 經反轉之轉換率補償訊號；及 複數個NMOS電晶體，其連接於包括於該補充預上拉 驅動反轉器單元中的該複數個NMOS電晶體之間，每一 NMOS電晶體在其閘極處接收對應之轉換率補償訊號。 22. —種輸出驅動器，其包含： 一補償單元，其經組態以感測該輸出驅動器之一轉換 率之一變化，藉此產生複數個轉換率補償訊號； 一預上拉驅動單元，其經組態以響應於該複數個轉換 率補償訊號而執行一預上拉操作； 一預下拉驅動單元，其經組態以響應於該複數個轉換 率補償訊號而執行一預下拉操作；及 一驅動單元，其經組態以響應於該預上拉驅動單元及 該預下拉驅動單元之輸出而驅動一輸出訊號，其中該補 112691-981007.DOC 1320932 償單元包含： 一轉換率感測單元，其經組態以根據諸如電壓及溫度 之環境條件來感測該輸出驅動器之該轉換率的該變化； 及 一訊號產生單元，其經組態以基於該轉換率之該變化 而產生複數個轉換率補償訊號。 23. 如請求項22之輸出驅動器，其中該補償單元包括： 一數位化單元，其經組態以數位化該轉換率感測單元 之一輸出； 其中該轉換率感測單元、該預上拉驅動單元及該預下 拉驅動單元之每一者包括一相同組態的MOS電晶體。 24. 如請求項23之輸出驅動器，其中該預上拉驅動單元包 括： 一反轉器單元，其經組態以將一第一驅動訊號反轉， 藉此輸出為一上拉驅動訊號；及 一驅動電壓提供器，其經組態以響應於該複數個轉換 率補償訊號，而選擇性地將一驅動電壓提供至該反轉器 〇〇 — 早兀。 25. 如請求項24之輸出驅動器，其中該反轉器單元包括： 複數個PMOS電晶體，其彼此並聯連接於該驅動電壓 提供器與一輸出節點之間，每一 PMOS電晶體在其閘極 處接收該第一驅動訊號；及 複數個NMOS電晶體，其彼此並聯連接於該輸出節點 與該驅動電壓提供器之間，每一 NMOS電晶體接收該第 112691-981007.DOC 1320932 一驅動訊號。 26. 如請求項25之輸出驅動器，其中該驅動電壓提供器包 括： 複數個PMOS電晶體，其連接於一第一内部電源電壓 端子與包括於該反轉器單元中的該複數個PMOS電晶體 之間，每一 PMOS電晶體在其閘極處接收一對應之轉換 率補償訊號；及 複數個NMOS電晶體，其連接於包括於該反轉器單元 中的該複數個NMOS電晶體與一接地電壓端子之間，每 一 NMOS電晶體在其閘極處接收一對應之轉換率補償訊 號。 27. 如請求項26之輸出驅動器，其中該轉換率感測單元係用 串聯連接於一第二内部電源電壓端子與一内部接地電壓 端子之間的複數個電阻器予以實施，並經由該等連接節 點之一者輸出一輸出訊號，其中該複數個電阻器之一者 係該MOS電晶體，其在其閘極處接收一外部電源電壓。 28. 如請求項27之輸出驅動器，其中該轉換率感測單元包 括： 一第一被動元件電阻器，其連接於該第二内部電源電 壓端子與一第一輸出節點之間； 一第一 NMOS電晶體，其連接至該第一輸出節點，經 由其閘極接收一外部電源電壓；及 一第二NMOS電晶體，其連接於該第一 NMOS電晶體與 該内部接地電壓端子之間，接收一感測訊號， 112691-981007.DOC 1320932 其中该感測訊號僅當該感測訊號達到一適當臨限值時 啟用該轉換率感測單元，以節省該轉換率感測單元之電 流耗用。 29·如請求項28之輸出驅動器，其中該第一]^]^〇8電晶體相 同於包括於該預上拉驅動單元及該預下拉驅動單元中的 電晶體。 3 0·如請求項27之輸出驅動器，其中該轉換率感測單元、該 預上拉驅動單元及該預下拉驅動單元之每一者包含— PMOS電晶體。 31_如請求項30之輸出驅動器，其中該數位化單元包括： 一參考電壓提供器，其經組態以提供複數個參考電 壓；及 一比較單元，其經組態以比較該等參考電壓之每—者 與S玄轉換率感測單元之該輸出。 32. 如請求項31之輸出驅動器，其中該參考電壓提供器包括 串聯連接於該第^内部電源電壓力子與該接地電壓端子 之間的複數個電阻器’且該等電阻器之間之連接節點處 的電壓提供該等參考電壓。 33. 如請求項32之輸出驅動器，其中該比較單元包括複數個 差動放大器，其接收參考電壓之一者及該轉換率感測單 元的該輸出。 34. 如6月求項33之輸出驅動器，其中該驅動單元包括： 第PMOS電晶冑，其連接至一第二内部電源電壓 端子，在其閘極處接收該預上拉驅動單元之一輸出； 112691.981007.DOC 1320932 一第二被動元件電阻器，其連接於該第一 PMOS電晶 體與一第二輸出節點之間； 一第三NMOS電晶體，其連接至該接地電壓端子，在 其閘極處接收該預下拉驅動單元之一輸出；及 一第三被動元件電阻器，其連接於該第三NMOS電晶 體與該第二輸出節點之間。 3 5.如請求項34之輸出驅動器，其中該驅動單元包括： 一 PMOS電晶體，其連接至一電源電壓端子，接收該 預上拉驅動單元之一輸出； 一第一被動元件電阻器，其連接於該PMOS電晶體與 一輸出節點之間； 一 NMOS電晶體，其連接至一接地電壓端子，接收該 預下拉驅動單元之一輸出；及 一第二被動元件電阻器，其連接於該NMOS電晶體與 該輸出節點之間。 112691-981007.DOC 10- 1320932 第095124005號專利申請案 '- 中文說明書替換頁(98年10月） 七、 指定代表圖： (一) 本案指定代表圖為：第（2 )圖。 (二) 本代表圖之元件符號簡單說明： 100 驅動單元 200 預上拉驅動單元 300 預下拉驅動單元 400 轉換率補償單元 • NM4 第四NMOS電晶體 # PM4 第四PMOS電晶體 R5 第五電阻器 R6 第六電阻器 八、 本案若有化學式時，請揭示最能顯示發明特徵的化學式： (無）a reference voltage supply voltage; and configured to provide a plurality of reference voltages configured to compare each of the reference voltages to the output of the conversion rate sensing unit. 12. The output driver s of claim 11, wherein the reference electrical repeater comprises a plurality of resistors connected in series between the first internal power supply (four) terminal and the ground electrical terminal, and the two "mines" And the voltage at the connection node between the three equal-resistance states provides the reference voltages. . ― /, This includes a plurality of 112691-981007.DOC 14. The differential amplification g ′ is connected by the M to receive the reference power and the rotation of the conversion rate sensing unit. The output driver of claim 13 wherein the driving unit comprises: a PMOS packet crystal connected to the second internal power supply voltage terminal: 'receives one of the pre-pull drive unit outputs at its gate; the first passive a 7L resistor connected between the first pM〇s transistor and a second output node; a first NMOS transistor connected to the ground voltage terminal and receiving the pre-pull drive unit at a gate thereof And a first passive component resistor coupled between the third nm 〇s transistor and the second output node. 15. The output driver of claim 6, wherein the driving unit comprises: a power supply voltage terminal and receiving the PMOS transistor, which is connected to an output of a pre-pull drive unit; a passive element resistor connected to An NMOS transistor coupled to a ground voltage terminal and receiving an output of the pre-pull drive unit; and a first passive component resistor coupled to the NM〇s Between the transistor and the output node. For example, the output driver of the π-term 15 is ||, wherein the main pre-pull drive unit comprises: a main pre-pull drive inverter unit configured to invert a first drive signal, thereby outputting an upper Pull drive signal; and 112691^98l〇〇7.D〇c -4- 1320932 - a main drive voltage provider configured to selectively provide a drive voltage in response to the plurality of slew rate compensation signals (d) (iv) Pull-up drive inverter unit. 17. The output driver of claim 16, wherein the main pre-pull drive reverse write unit comprises: - a PMOS transistor that receives the first drive signal at its gate; and - NM 〇 S A crystal that receives the first-drive signal at its gate. The output driver of claim 17, wherein the main driving voltage provider comprises: a PMOS transistor receiving a corresponding inverted conversion rate compensation signal at a gate thereof; and an NMOS transistor A corresponding conversion rate compensation signal is received at its gate. 19. The output of claim 18, wherein the supplemental pre-pull drive unit comprises: a supplemental pre-pull drive inverter unit configured to invert a first drive signal, The output is a pull-up drive signal; and a supplemental drive voltage provider configured to selectively provide a drive voltage to the supplemental pre-pull drive inverter in response to the plurality of slew rate compensation signals unit. 20. The output driver of claim 19, wherein the supplemental pre-pull drive inverter unit comprises: 112691-981007.DOC a plurality of PMOS transistors connected in parallel with each other between the drive voltage provider and an output node Each PMOS transistor receives the first driving signal at its gate; and a plurality of NMOS transistors connected in parallel with each other between the output node and the driving voltage supplier, each NMOS transistor receiving the first A drive signal. 21. The output driver of claim 20, wherein the supplemental drive voltage provider comprises: a plurality of PMOS transistors coupled to the supply voltage terminal and the plurality of included in the supplemental pre-pull drive inverter unit Between the PMOS transistors, each PMOS transistor receives a corresponding inverted conversion rate compensation signal at its gate; and a plurality of NMOS transistors connected to the complementary pre-pull drive inverter unit Between the plurality of NMOS transistors, each NMOS transistor receives a corresponding conversion rate compensation signal at its gate. 22. An output driver comprising: a compensation unit configured to sense a change in one of a conversion rate of the output driver, thereby generating a plurality of conversion rate compensation signals; a pre-pull drive unit Configuring to perform a pre-pull operation in response to the plurality of conversion rate compensation signals; a pre-pull drive unit configured to perform a pre-pull operation in response to the plurality of conversion rate compensation signals; a driving unit configured to drive an output signal in response to an output of the pre-pull drive unit and the pre-pull drive unit, wherein the complement 112691-981007.DOC 1320932 compensation unit comprises: a conversion rate sensing unit, It is configured to sense the change in the conversion rate of the output driver based on environmental conditions such as voltage and temperature; and a signal generating unit configured to generate a plurality of conversions based on the change in the conversion rate Rate compensation signal. 23. The output driver of claim 22, wherein the compensation unit comprises: a digitizing unit configured to digitize an output of the conversion rate sensing unit; wherein the conversion rate sensing unit, the pre-up pull Each of the drive unit and the pre-pull drive unit includes a MOS transistor of the same configuration. 24. The output driver of claim 23, wherein the pre-pull drive unit comprises: an inverter unit configured to invert a first drive signal, thereby outputting a pull-up drive signal; A drive voltage provider configured to selectively provide a drive voltage to the inverter in response to the plurality of slew rate compensation signals. 25. The output driver of claim 24, wherein the inverter unit comprises: a plurality of PMOS transistors connected in parallel between the driving voltage provider and an output node, each PMOS transistor being at its gate Receiving the first driving signal; and a plurality of NMOS transistors connected in parallel with each other between the output node and the driving voltage provider, each NMOS transistor receiving the 112691-981007.DOC 1320932 driving signal. 26. The output driver of claim 25, wherein the driving voltage provider comprises: a plurality of PMOS transistors coupled to a first internal supply voltage terminal and the plurality of PMOS transistors included in the inverter unit Between each PMOS transistor receives a corresponding conversion rate compensation signal at its gate; and a plurality of NMOS transistors connected to the plurality of NMOS transistors and a ground included in the inverter unit Between the voltage terminals, each NMOS transistor receives a corresponding slew rate compensation signal at its gate. 27. The output driver of claim 26, wherein the conversion rate sensing unit is implemented by a plurality of resistors connected in series between a second internal supply voltage terminal and an internal ground voltage terminal, and via the connections One of the nodes outputs an output signal, wherein one of the plurality of resistors is the MOS transistor, which receives an external supply voltage at its gate. 28. The output driver of claim 27, wherein the conversion rate sensing unit comprises: a first passive component resistor coupled between the second internal supply voltage terminal and a first output node; a first NMOS a transistor connected to the first output node, receiving an external power supply voltage via the gate thereof; and a second NMOS transistor connected between the first NMOS transistor and the internal ground voltage terminal, receiving a The sensing signal, 112691-981007.DOC 1320932, wherein the sensing signal enables the conversion rate sensing unit only when the sensing signal reaches an appropriate threshold to save current consumption of the conversion rate sensing unit. 29. The output driver of claim 28, wherein the first transistor is the same as the transistor included in the pre-pull drive unit and the pre-pull drive unit. The output driver of claim 27, wherein each of the conversion rate sensing unit, the pre-pull drive unit, and the pre-pull drive unit comprises a PMOS transistor. 31. The output driver of claim 30, wherein the digitizing unit comprises: a reference voltage provider configured to provide a plurality of reference voltages; and a comparison unit configured to compare the reference voltages The output of each sensing unit and the S-conversion rate sensing unit. 32. The output driver of claim 31, wherein the reference voltage provider comprises a plurality of resistors connected in series between the first internal power supply voltage and the ground voltage terminal and a connection between the resistors The voltage at the node provides these reference voltages. 33. The output driver of claim 32, wherein the comparison unit comprises a plurality of differential amplifiers that receive one of the reference voltages and the output of the conversion rate sensing unit. 34. The output driver of claim 33, wherein the driving unit comprises: a PMOS transistor, connected to a second internal power voltage terminal, and receiving an output of the pre-pull driving unit at a gate thereof 112691.981007.DOC 1320932 a second passive component resistor connected between the first PMOS transistor and a second output node; a third NMOS transistor connected to the ground voltage terminal at the gate thereof Receiving an output of the pre-pull drive unit; and a third passive element resistor connected between the third NMOS transistor and the second output node. 3. The output driver of claim 34, wherein the driving unit comprises: a PMOS transistor coupled to a power supply voltage terminal for receiving an output of the one of the pre-pull drive units; and a first passive element resistor Connected between the PMOS transistor and an output node; an NMOS transistor connected to a ground voltage terminal for receiving an output of the pre-pull drive unit; and a second passive device resistor coupled to the NMOS Between the transistor and the output node. 112691-981007.DOC 10- 1320932 Patent Application No. 095124005 '- Chinese Manual Replacement Page (October 98) VII. Designation of Representative Representatives: (1) The representative representative of the case is: (2). (2) A brief description of the component symbols of the representative figure: 100 drive unit 200 pre-pull drive unit 300 pre-pull drive unit 400 conversion rate compensation unit • NM4 fourth NMOS transistor # PM4 fourth PMOS transistor R5 fifth resistor R6 Sixth Resistor 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: (none) 112691-981007.DOC112691-981007.DOC
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KR101894470B1 (en) * 2012-05-21 2018-09-03 에스케이하이닉스 주식회사 Output driver circuit
TWI503821B (en) * 2012-07-09 2015-10-11 Faraday Tech Corp Static random access memory apparatus and bit-line volatge controller thereof
CN103905028B (en) * 2012-12-25 2018-05-25 中芯国际集成电路制造(上海)有限公司 Signal receiver and signal transmission apparatus
CN104104383B (en) * 2013-04-09 2017-12-26 北京时代全芯科技有限公司 A kind of Slew Rate and the adjustable offline drive device of resistance
CN105306043B (en) * 2014-06-04 2018-11-06 晶豪科技股份有限公司 Input buffer
CN107919154B (en) * 2017-12-11 2018-10-26 长鑫存储技术有限公司 A kind of input/output driver calibration circuit, method and semiconductor memory
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KR102526256B1 (en) * 2018-03-06 2023-04-28 에스케이하이닉스 주식회사 Data output buffer
CN112383299B (en) * 2020-10-26 2024-04-02 中车株洲电力机车研究所有限公司 Signal logic conversion circuit

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TW200713315A (en) 2007-04-01
CN1941199A (en) 2007-04-04

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