1320921 九、發明說明： 【發明所屬之技術領域】 本發明有關於-種移位暫存器’特別有關—種移位暫存器能夠不需緩 過NAND電路而直接產生一驅動信號。 【先前技術】 於現今技術中，低溫多晶矽(OTS)薄膜電晶體之驅動電路，由於其對 於製程變異具有較大的忍受力，因此靜態移位暫存器被廣泛地使肖。铁而， •由於相鄰輸出時脈會發生重疊，因此需使用N娜電路來得到非重疊之輸 出時脈。 第1圖所示係為-傳統驅動器之示意圖，而第2圖係為第丨圖所示之 驅動器的時序圖。如第！圖、第2圖所示，傳統驅動器ι〇包括串聯連接之 複數移位暫存器SR1〜SR3以及對應之ΝΑΝ〇電路⑵、123。移位暫存器 SR1與SR3皆具有一第一控制端係織時脈信號⑽，一第二控制端係輕 接時脈信號CLK之反相信號/CLK ;而移位暫存器SR2具有一第一控制端 係耦接時脈信號CLK之反相信號/CLK，一第二控制端係雛時^信號 鲁CLK。移位暫存器SR1係根據啟始信號以、時脈信號clk以及反相信號 /CLK’產生-對應之輸出時脈獅小轉位暫存器測之輸㈣脈 係作為下-級移位暫存器SR2之啟始信號，並且移位暫存器sr2之輸出時 脈Vout-2係作為下一級移位暫存器之啟始信號。 於傳統驅動器中，需要將第—及第二移位暫存器SR1與肥之輸出時 脈Vout-1與Vout_2，輸入至一對應之獅^電路i2i，且根據致能時脈信 號腿來產生驅動信號G卜並且將需要經由第二及第三移位暫存器肥 與SR3之輸出時脈v〇m·2與v〇ut_3 ,輸入另一對應之ναν〇電路⑵，且 根據時脈七號而產生驅動信號。也就是說，傳統驅動電路為了產 生不重疊之驅動信號，除了移位暫存器之外，需設置額外的歸^電路。 0773-A31462TWF(5.0) 5 【發明内容】 有鑑於此，本發明之首要目的，係在於一種 _電路而直接產生―夠不4過 2成上述目的，本發明提供_種移位暫存器，包括—栓鎖電路，用 以麵接-_靖_ puise)以及肤向信號，根據 輸出時脈信號；以及—輸出單元，包括-控制單元以及-輸it鎖=， 雛時脈錢以狀向錢，崎__脈钱，細―麟作號。 根據上述目的，本發明亦提供_種驅動器，包括—第—及—第二前述 之移位暫存器’肋依序產生—第—及—第二驅動信號，其中第一移位暫 存器之輸«鋪作為第二移鱗雜之啟始信號，抑—移位暫存器係 具有-第-、第二控制端分聰接時脈信號以及反向信號，而第二移位暫 存器係具有-第-、第二控制端分職接反向信號以及時脈信號。 根據上述目的，本發日神提供—麵示雜，.包括—晝素矩陣，以及 一前述之驅動器，用以驅動晝素矩陣。 根據上述目的，本發明亦提供_子裝置，包括—前述之顯示面板， 以及一電源供應單元，用以供電至顯示面板。 為了讓本發明之上述和其他目的'特徵、和優點能更明顯易僅，下文 特舉一較佳實施例，並配合所附圖示，作詳細說明如下： 【實施方式】 第3圖所示係為根據本發明實施例之一驅動器。如圖所示所示，驅動 器1〇〇包括複數個串聯連接的移位暫存器SR1〜SR4。移位暫存器SRI與sr3 普具有-第-控制端係#接時脈信號CLK，-第二控制端係輕接時脈信號 CLK之反相信號/CLK ;而移位暫存器SR2、SR4係具有-第-控制端係_ 接時脈彳§號CLK之反相信號/CLK，一第二控制端係糕接時脈信號CLK。 〇773-A31462TWF(5.0) 6 私位暫存S SR1係根據啟始信號m、時脈信號clk以及反相信號/clk， 產生對應之輪ώ時脈Vbutj作為下一級移位暫存器肥之啟始信號，以 及-對應之驅動信號Sdl。移位暫存器SR2係根擄移位暫存器測之輪出 時脈V〇Ut·!、時脈域似以及反相信號/clk，產生一對應之輸出_ V祕2作為下—級移位暫存器如之啟始信號，以及—對應之驅動信號 X此類推ϋ此’驅動器1〇〇可以依序地輸出不重疊之驅動信號。 第4圖所示係為本發明實施例之移位暫存器。如圖所示，移位暫存器 一 c括栓鎖電路3〇，用以輕接一時脈信號pulse)CLK以及其反向 信號/CLK，根據-啟始信號m，輸出一輸出時脈信號漏，以及一輸出單 兀4〇 ’，括-控制單元42以及一輪出栓鎖單元44，輕接時脈信號CM以 及反向L號/CLK ’用以根據輸出時脈信號Vcjut，輸出—驅動信號^。 检鎖電路30係包括二個時脈控制型反相柳〇制匕她^刪、 CINV2以及-反相物verter)騰丨。時脈控制型 入端輕接啟始信號I -第_控制_接時脈信號_，—第 CXKt«_/CXK ’ n輸㈣減反相器膽〗之輸入 端。也就是說’於時脈信號CLK為ffiGH(即/CLK為LOWM，時脈控制 型反相器CINV1才會動作。 反相器INV1係具有—輸入端係耦接時脈控制型反相器c腑i之輸出 端’以及-輸出端輕用以輸出一時脈信號v〇ut。時脈控制型反相器 錯有-輸人_接時脈信號VGUt，n綱耦接時脈信號CLK之反 相信號/CLK ’ 一第二控制端輕接時脈信號CLK，以及一輸出端輕接反相器 卿1之輸入端。也就是說’於時脈信號CLK為聊(即/clk為邮聊， 時脈控制型反相器CINV2才會動作。 π輸出單το 4〇係包括-控制單元π以及—輸出栓鮮元μ，輸出检鎖 單元44係用以根據時脈信號CLK以及反向信號/(χκ，產生驅動信號別； 而控制單兀42係耦接於時脈信號CLK及反向信號/CLK與輸出检鎖單元44 〇773-A31462TWF(5.0) 7 :::=出時脈信號"t ’傳送時脈信號CLK及反向信歸 缺包括:電晶體M1及奶，電晶體M1係具有-第-端 時脈^CLK，-第二端_至栓鎖單以4，以及—控制端 第目益：丄之輸出端。電晶體⑽係具有—第一端耦接時脈信號/CLK，- 鎖單元44 ’以及，端柄至_腑〗之輸出端，1320921 IX. Description of the Invention: [Technical Field] The present invention relates to a shift register. In particular, a shift register can directly generate a drive signal without slowing down the NAND circuit. [Prior Art] In the prior art, the driving circuit of the low temperature polysilicon (OTS) thin film transistor has a large tolerance to process variation, so the static shift register is widely used. Iron, • Because the adjacent output clocks overlap, the N Na circuit is used to obtain non-overlapping output clocks. Figure 1 is a schematic diagram of a conventional driver, and Figure 2 is a timing diagram of the driver shown in Figure 1-3. As the first! As shown in Fig. 2, the conventional driver ι includes a plurality of shift register registers SR1 to SR3 and corresponding ΝΑΝ〇 circuits (2) and 123 connected in series. Each of the shift registers SR1 and SR3 has a first control terminal multiplexed clock signal (10), and a second control terminal is connected to the inverted signal /CLK of the clock signal CLK; and the shift register SR2 has a The first control terminal is coupled to the inverted signal /CLK of the clock signal CLK, and the second control terminal is coupled to the signal CLK. The shift register SR1 is generated according to the start signal, the clock signal clk, and the inverted signal /CLK'-corresponding output clock lion small transposition register measurement (four) pulse system as the lower-level shift The start signal of the register SR2, and the output clock Vout-2 of the shift register sr2 is used as the start signal of the next stage shift register. In the conventional driver, the first and second shift register SR1 and the fat output clocks Vout-1 and Vout_2 need to be input to a corresponding lion circuit i2i, and generated according to the enable clock signal leg. The drive signal G and will need to be input to the other corresponding ναν〇 circuit (2) via the second and third shift register fertilizers and the output clocks v〇m·2 and v〇ut_3 of SR3, and according to the clock seven The number produces a drive signal. That is to say, in order to generate non-overlapping driving signals, the conventional driving circuit needs to set an additional switching circuit in addition to the shift register. 0773-A31462TWF(5.0) 5 SUMMARY OF THE INVENTION In view of the above, the primary object of the present invention is to directly generate a _circuit and to achieve the above-mentioned purpose, and the present invention provides a shift register. Including - latching circuit for face-to-hand _ puise and skin direction signal, according to the output clock signal; and - output unit, including - control unit and - input it lock =, Money, Qi __ pulse money, fine - Lin Zuo. According to the above object, the present invention also provides a driver, including - the first and the second shift register, the rib sequentially generates - the first and the second drive signal, wherein the first shift register The transmission «shop as the second shifting start signal, the shift register has - the first, the second control end is connected to the clock signal and the reverse signal, and the second shift is temporarily stored. The device has a -first-and second-control terminal divided into a reverse signal and a clock signal. According to the above purpose, the present invention provides a surface display, including a halogen matrix, and a driver for driving the pixel matrix. In accordance with the above objects, the present invention also provides a sub-device comprising: the aforementioned display panel, and a power supply unit for supplying power to the display panel. The above and other objects, features and advantages of the present invention will become more apparent and obvious. The following detailed description of the preferred embodiments, together with the accompanying drawings, It is a driver according to an embodiment of the present invention. As shown, the driver 1 includes a plurality of shift registers SR1 to SR4 connected in series. The shift register SRI and sr3 have a -th-control terminal system# connected to the clock signal CLK, and the second control terminal is connected to the inverted signal /CLK of the clock signal CLK; and the shift register SR2 The SR4 system has a -th control terminal system _ connected to the clock signal CLK of the CLK number CLK, and a second control terminal is connected to the clock signal CLK. 〇773-A31462TWF(5.0) 6 Private temporary storage S SR1 is based on the start signal m, the clock signal clk and the inverted signal /clk, and generates the corresponding rim clock Vbutj as the next stage shift register fertilizer The start signal, and the corresponding drive signal Sdl. The shift register SR2 is based on the shift clock of the shift register V〇Ut·!, the clock domain and the inverted signal /clk, and generates a corresponding output _ V secret 2 as the lower level The shift register, such as the start signal, and the corresponding drive signal X, such that the driver 1 can sequentially output non-overlapping drive signals. Figure 4 is a shift register of an embodiment of the present invention. As shown in the figure, the shift register 1 includes a latch circuit 3A for lightly connecting a clock signal pulse CLK and its reverse signal /CLK, and outputting an output clock signal according to the -start signal m. Leakage, and an output unit 4', including - control unit 42 and a round latching unit 44, the light clock signal CM and the reverse L number / CLK ' are used to output-drive according to the output clock signal Vcjut Signal ^. The lock-up circuit 30 includes two clock-controlled inverted banks, and the CINV2 and the -verter verter. The clock control type is connected to the input signal of the start signal I - the _ control _ the clock signal _, - the CXKt «_ / CXK ’ n input (four) minus the inverter. That is to say, 'the clock signal CLK is ffiGH (ie, /CLK is LOWM, the clock-controlled inverter CINV1 will operate. The inverter INV1 has - the input is coupled to the clock-controlled inverter c输出i's output terminal 'and-output terminal light is used to output a clock signal v〇ut. The clock-controlled inverter is wrong--the input _ is connected to the clock signal VGUt, and the n-coupled clock signal CLK is reversed. Phase signal /CLK ' A second control terminal is connected to the clock signal CLK, and an output terminal is connected to the input terminal of the inverter 1 . That is to say, 'the clock signal CLK is chat (ie /clk is a mail chat) The clock-controlled inverter CINV2 will operate. The π output single το 4 包括 includes a - control unit π and an output plug fresh element μ, and the output lock-lock unit 44 is configured to use the clock signal CLK and the reverse signal. / (χ κ, generate drive signal; and control unit 42 is coupled to clock signal CLK and reverse signal / CLK and output lock unit 44 〇 773-A31462TWF (5.0) 7 ::: = out clock signal "t 'Transmission clock signal CLK and reverse letter default include: transistor M1 and milk, transistor M1 has - first-end clock ^CLK, - second end _ to The lock is 4, and the control terminal is: the output of the transistor. The transistor (10) has the output of the first terminal coupled to the clock signal /CLK, the lock unit 44', and the output from the end handle to the _腑. end,
及=係根據輸出時脈信號、之控制，而傳送時脈信號CLK 2飢K至輸出栓鎖單元44。電晶體奶捕係可為薄膜電晶體， 最好為多晶矽薄膜電晶體。 端耗二反相^勝2 #购，反相器腑2具有一輸入 日日-第一端，以及一輪出端耦接電晶體Ml之第二端。反相 瞻3具有一輸入端_電晶體奶之第二端與反相器讀之輪出= =^出_接電晶體M2之第二端與反相器騰2之輸出端，其中反相 益^之輸出端與反相器卿3之輸入端係用以輸出驅動信號Sd。 說明称之崎㈣街帛4喝5圖 於第一周期T1時’ B寺脈信號CLK與反相n/CiK在八 與=辑脈控制型反相咖動作， 不會動作。因此時脈控_反㈣贈i會根據啟始信號 邱㈣’於祕N1上產生之-嫌(L〇W)，故反撼疆會因^出 -南電位(HIGH)之輸出時脈信號_。 因而輸出 由於輸出時脈信號VouM為高電罐GH)，控制單元*中 Mi與M2會導通’以傳輸時脈信號咖與反相信號/clk 心And = according to the output clock signal, the control, and the clock signal CLK 2 is transmitted to the output latch unit 44. The transistor milk capture system can be a thin film transistor, preferably a polycrystalline germanium film transistor. The terminal consumes two inversions, and the inverter 腑2 has an input day-to-first end, and a round end is coupled to the second end of the transistor M1. The anti-phase 3 has an input terminal _ the second end of the transistor milk and the inverter reads the wheel ==^ _ the second end of the transistor M2 and the output of the inverter T2, where the inversion The output terminal of the benefit ^ and the input terminal of the inverter 3 are used to output the driving signal Sd. Description Sasaki (4) Street 帛 4 drink 5 map In the first cycle T1 'B temple pulse signal CLK and reverse n / CiK in the eight and = pulse control type inverted coffee action, will not operate. Therefore, the time pulse control _ anti (four) gift i will be based on the start signal Qiu (four) 'on the secret N1 - suspected (L〇W), so the anti-Yujiang will be due to ^ output - South potential (HIGH) output clock signal _. Therefore, since the output clock signal VouM is a high tank GH), Mi and M2 in the control unit* are turned on to transmit the clock signal and the inverted signal/clk heart.
44中。信饥K狀觸獻編卿GH 脈信雜係物動信號_出，同時被_在輪出检 〇773-A31462TWF(5.0) 8 接著’於第二顺T2時，時脈信號CLK與反相信號/clk係分別為 LOW與HIGH，因此時脈控制型反相器c丽不會動作，而時脈控制型反 相器CINV2會動作。賴控制型反撼CINV2會根據高電牵呵之輸 出時脈信V〇ut]，於節點N1上產生之低電雖，，使得反撼圓仍 然將輸出時脈信號誕i維持在高電位。由於輸㈣脈信v〇ut i仍為高電 位(刪），控制單元40中之電晶體與⑽會維持導通，此時由树脈 信號CLK與反相信號/CLK係分別為歸與腦H，故驅動信號如就會 被拉低(pull low) ’同時被栓鎖在輸出栓鎖單元私中。 此外，由於時脈錢VouU係下一級之移位暫存器之啟始信號，且下 一級移位暫存器中第-時脈控制型反相器c顯之第_、第二控制端係分 別麵接至反相信號/CLK與時脈信號CLK，而第二時脈控制型反相器C刪 之第-、第二控制端係分職接至時脈信號CLK與反相信號/cLK。所以於 第二周期時，下—級移位暫存器中第二雜控制型反相器〇刪不會動 作’而第-時脈控制型反相器CINV1會動作，使得反相器刪產生一另 -個輸出時脈V〇ut-2。由於輪出時脈信v祕2為高電位卿印，控制單元 令之電曰曰，Ml與M2會導通’以傳輸時脈信號CLK與反相信號 至輪出栓鎖單元44中。此時由於時脈信號CLK與反相信號/clk係分別為 LOW與HIGH，故高準位之時脈信號獻係作為驅動信號泌輸出，同時 破栓鎖在下-輸出栓鎖單元44中。其它後級移位暫存器之動作係為前者相 同’請依此類推，於此不再累述。 因此’本發明之驅動器1〇〇中，每個移位暫存器sr皆可自行產生一驅 動信號，而不用如傳統驅動器―般，需要設置額外之_電路，且需要 二級移位暫存H之輸祕衝才可得到—驅動信號。 。。第6圖係為本發明貫施例之—顯示面板。顯*面板射包括一驅 動器100以及晝素陣列11〇，驅動器1〇〇係用以驅動畫素陣列no，以產 生Ά且驅動器1〇〇係可為顯示面板之一掃描(閘極)驅動器或資料驅動 〇773-A31462TWF(5.0) 9 1320921 器，而顯示面板200係可為一液晶顯示面板、一有機發光二極體顯示面板 或一射發射顯示(FED)面板。 第7圖係為本發明實施例之一電子裝置。電子裝置3〇〇係使用前述之 顯示面板，顯示面板200係可為一液晶顯示面板，但不限定於此。電子裝 置300係可為一可攜式裝置，例如一個人數位助理(pDA)、一筆記型電腦、 -平板電腦、-行動電話或是-顯示器…等等…般來說，電子裝置3〇〇 係具有一外殼210、一顯示面板200以及一電源供應器22〇，電源供應器22〇 係用以提供電源雜至顯示面板綱’而顯示面板係用以顯示影像。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任 何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作些許之更動與 潤飾’因此本發明之賴範圍#視後社冑請專補贿界定者為準。 【圖式簡單說明】 第1圖所示係為一傳統信號驅動器之示意圖。 第2圖係為第1圖所示之驅動器的時序圖。 第3圖所示係為根據本發明實施例之—驅動器。 第4圖所示係為本發明實施例之移位暫存器。 第5圖係為本發明移位暫存器之時序示意圖。 第6圖係為本發明實施例之一顯示面板。 第7圖係為本發明實施例之-電子裝置。 【主要元件符號說明】 /CLK： : 脈信號之反相信號； ENB :致能時脈信號； 10、100 :驅動器； 40 :輪出單元； CLK :時脈信號； IN :啟始信號； 121 ' 123 ‘ IsiAjsjj)電路； 30 :栓鎖單元； 0773-A31462TWF(5.〇) 1320921 42 :控制單元； 44 :輸出栓鎖單元； Μ卜M2 :電晶體； INV1〜INV3 :反相器； Ν1 :節點； 110 :晝素陣列； 200 :顯示面板； 210 :外殼； 220 :電源供應器； 300 :電子裝置； CINV1、CINV2 :時脈控制型反相器；44. The hunger K-like touches the GH pulse signal of the GH signal, and is _ in the round 〇 773-A31462TWF (5.0) 8 then 'in the second cis T2, the clock signal CLK and inversion Since the signal /clk is LOW and HIGH, respectively, the clock-controlled inverter C does not operate, and the clock-controlled inverter CINV2 operates. The control loopback CINV2 will generate the clock signal V〇ut] according to the high voltage, and the low voltage generated at the node N1 will cause the output loop signal to maintain the output signal at a high potential. Since the input (four) pulse signal v〇ut i is still high (deleted), the transistor and (10) in the control unit 40 will remain conductive, and the tree pulse signal CLK and the inverted signal / CLK system respectively belong to the brain H. Therefore, if the drive signal is pulled low, it will be latched in the output latch unit. In addition, since the clock signal VouU is the start signal of the shift register of the next stage, and the first-stage and second control end of the first-stage clock-controlled inverter c in the next-stage shift register Connected to the inverted signal /CLK and the clock signal CLK respectively, and the second and second control terminals of the second clocked inverter C are respectively connected to the clock signal CLK and the inverted signal /cLK . Therefore, in the second cycle, the second miscellaneous control type inverter in the lower-stage shift register does not operate, and the first-clock-controlled inverter CINV1 operates, so that the inverter is deleted. One another - the output clock V〇ut-2. Since the clock signal 2 is a high-potential print, the control unit causes the power to be turned on, and M1 and M2 are turned on to transmit the clock signal CLK and the inverted signal to the wheel latch unit 44. At this time, since the clock signal CLK and the inverted signal /clk are LOW and HIGH, respectively, the clock signal of the high level is output as the driving signal, and the break is locked in the lower-output latch unit 44. The actions of other post-stage shift registers are the same as the former ones, and so on. Therefore, in the driver 1 of the present invention, each shift register sr can generate a driving signal by itself, instead of using a conventional circuit, it needs to set an additional circuit, and requires a secondary shift temporary storage. The loss of H can be obtained - the drive signal. . . Figure 6 is a display panel of the present invention. The display panel includes a driver 100 and a pixel array 11〇, the driver 1 is used to drive the pixel array no to generate a buffer, and the driver 1 can be a scanning (gate) driver for the display panel or The data drive 〇 773-A31462TWF (5.0) 9 1320921, and the display panel 200 can be a liquid crystal display panel, an organic light emitting diode display panel or a radiation emitting display (FED) panel. Figure 7 is an electronic device according to an embodiment of the present invention. The electronic device 3 uses the aforementioned display panel, and the display panel 200 can be a liquid crystal display panel, but is not limited thereto. The electronic device 300 can be a portable device, such as a number of assistants (pDA), a notebook computer, a tablet computer, a mobile phone, or a display, etc., in general, the electronic device 3 The utility model has a casing 210, a display panel 200 and a power supply 22, wherein the power supply 22 is used to supply power to the display panel and the display panel is used to display images. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the reliance # 视后社胄Please define the bribe. [Simple description of the diagram] Figure 1 is a schematic diagram of a conventional signal driver. Fig. 2 is a timing chart of the driver shown in Fig. 1. Figure 3 shows a driver in accordance with an embodiment of the present invention. Figure 4 is a shift register of an embodiment of the present invention. Figure 5 is a timing diagram of the shift register of the present invention. Figure 6 is a display panel of one embodiment of the present invention. Figure 7 is an electronic device in accordance with an embodiment of the present invention. [Main component symbol description] /CLK: : Inverted signal of pulse signal; ENB: Enable clock signal; 10, 100: Driver; 40: Round-out unit; CLK: Clock signal; IN: Start signal; ' 123 ' IsiAjsjj) circuit; 30: latch unit; 0773-A31462TWF (5.〇) 1320921 42 : control unit; 44: output latch unit; MM2: transistor; INV1~INV3: inverter; Ν1 : node; 110: pixel array; 200: display panel; 210: housing; 220: power supply; 300: electronic device; CINV1, CINV2: clock-controlled inverter;
Vout、Vout-1 〜Vout-4 :輸出時脈； SR、SR1〜SR4 :移位暫存器；Gl、G2、Sd、Sdl〜Sd4 :驅動信號 11 0773-A31462TWF(5.O)Vout, Vout-1 to Vout-4: output clock; SR, SR1 to SR4: shift register; Gl, G2, Sd, Sd1 to Sd4: drive signal 11 0773-A31462TWF (5.O)