CN100489932C - Panel display, drive device for display and shift temporary register - Google Patents
Panel display, drive device for display and shift temporary register Download PDFInfo
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- CN100489932C CN100489932C CNB2006100014211A CN200610001421A CN100489932C CN 100489932 C CN100489932 C CN 100489932C CN B2006100014211 A CNB2006100014211 A CN B2006100014211A CN 200610001421 A CN200610001421 A CN 200610001421A CN 100489932 C CN100489932 C CN 100489932C
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Abstract
A shift temporary storage receiving input signal and time pulse signal is prepared for using delay unit to make said input signal be a half-cycle delay of said time pulse signal then outputting said input signal, receiving signal outputted from said delay unit by buffer unit then providing extradriving ability to output received signal out, operating said buffer unit by the first and the second set voltages.
Description
Technical field
The invention relates to a kind of shift registor, and particularly relevant for a kind of flat-panel screens, drive device for display and shift registor.
Background technology
That flat-panel screens (for example LCD) has is in light weight, the characteristic of thin thickness, little, the low radiation of volume and power saving, and these characteristics make it can save usage space in office or family, and reduce and watch the sense of fatigue that human eye is caused for a long time.Therefore, flat-panel screens has the characteristics of comprehensive replacement conventional cathode ray tube (CRT).
Figure 1A for known application of cold temperature polysilicon technology to be implemented in the circuit diagram of the shift registor on the glass substrate, this shift registor can be applicable to the flat-panel screens driving circuit, for example the gate pole driver of liquid crystal screen vertical scanning please refer to Figure 1A.This figure comprises 5 grades of identical shift registors, is respectively SR1, SR2, SR3, SR4 and SR5.Each shift registor comprises input end In, time pulse signal input end CKA and CKB and output terminal Out.Comprise 4 time pulse signal lines among Figure 1A, imported the first time pulse signal CK1, the second time pulse signal CK2, the 3rd time pulse signal CK3 and the 4th time pulse signal CK4 respectively.In addition, Figure 1A has also comprised initial pulse line SP.
Figure 1B is that known application of cold temperature polysilicon technology is to be implemented in the detailed circuit diagram of SR1 among the shift registor Figure 1A on the glass substrate.This circuit comprises thin film transistor (TFT) 101,102,103 and electric capacity 104.First source/drain of thin film transistor (TFT) 101 is the input end In of SR1.Second source/drain of thin film transistor (TFT) 101 couples the gate of thin film transistor (TFT) 102.The gate of thin film transistor (TFT) 101 is time pulse signal input end CKA, and couples the gate of thin film transistor (TFT) 103.First source/drain of thin film transistor (TFT) 102 is time pulse signal input end CKB.Second source/drain of thin film transistor (TFT) 102 is the output terminal Out of SR1.First source/drain of thin film transistor (TFT) 103 couples second source/drain of thin film transistor (TFT) 102.Second source/drain of thin film transistor (TFT) 103 is the power input VSS of electronegative potential.
Fig. 1 C is Figure 1A circuit timing diagram, please also refer to Figure 1A, Figure 1B and Fig. 1 C.We must suppose the time pulse signal voltage amplitude earlier at low level=VSS, and the time pulse signal voltage amplitude is at high levle=VDD, VDD〉VSS.At first, In imports an initial pulse SP, and this moment, time pulse signal CK1 was high levle VDD, and thin film transistor (TFT) 101 and 103 beginning conductings make noble potential be stored on the electric capacity 104.CK1 transfers low level to by high levle when the clock pulse signal, and this moment, time pulse signal CK3 also transferred high levle to by low level.Because electric capacity 104 stores noble potentials, makes thin film transistor (TFT) 102 gates receive high levle, with the high levle VDD conducting of time pulse signal CK3 to output terminal Out.Make the shift registor SR2 of next stage begin to receive noble potential.
Though the known framework that has a kind of shift registor, this kind framework have a shortcoming, see also Figure 1B.Can see among Figure 1B that time pulse signal CKB must be by the input of the source/drain of thin film transistor (TFT) 102, so can cause the time pulse signal generator must very strong driving force, certainly will will increase layout area and reach yet strengthen driving force.
Summary of the invention
Purpose of the present invention is providing a kind of shift registor exactly, in order to the required driving force that provides of time pulse signal to be provided.
A further object of the present invention provides a kind of drive device for display, in order to reduce the wafer layout area.
Another purpose of the present invention provides a kind of flat-panel screens, can reduce the cost.
The present invention proposes a kind of shift registor, is used to drive flat-panel screens, and this shift registor receives input signal and time pulse signal, and this shift registor comprises delay cell and buffer cell.Delay cell is exported after in order to a semiperiod that this input signal is postponed this time pulse signal.Buffer cell receives the output signal of this delay cell, and extra driving force and output are provided, and wherein, this buffer cell is with one first fixing voltage and one second voltage-operated.
According to the described a kind of shift registor of preferred embodiment of the present invention, this above-mentioned delay cell comprises the first transistor, charge storage element and transistor seconds.The first transistor comprises first end and second end, and first end is the input end of delay cell, according to this time pulse signal, whether to determine the circuit between conducting first end and second end.Charge storage element one end couples first current potential, and its other end couples second end.Transistor seconds comprises the 3rd end and the 4th end, and the 3rd end couples second end, and the 4th end is the output terminal of delay cell, according to the anti-phase signal of time pulse signal, whether to determine the circuit between conducting the 3rd end and the 4th end.
According to the described a kind of shift registor of preferred embodiment of the present invention, above-mentioned buffer cell comprises the 3rd transistor and the 4th transistor.The 3rd transistor comprises first control end, five terminal and the 6th end, and first control end couples the 4th end, and five terminal couples second current potential.The 4th transistor comprises second control end, the 7th end and the 8th end, and second control end couples time pulse signal, and the 7th end couples the 6th end, and the 8th end couples first current potential.
The present invention proposes a kind of drive device for display, comprises N shift registor, and each those shift registor comprises input node, output node, delay cell and buffer cell.The delay cell input end couples this input node, in order to export after the semiperiod that will import node signal delay time pulse signal.The buffer cell output terminal couples this output node, output signal in order to the receive delay unit, extra driving force and output is provided, wherein, N is a natural number, the input node of N shift registor couples the output node of N-1 shift registor, and in addition, this buffer cell is with one first fixing voltage and one second voltage-operated.
The present invention proposes a kind of flat-panel screens, comprises drive device for display and display panel.Drive device for display comprises N shift registor, and each those shift registor has input node, output node, delay cell and buffer cell.The delay cell input end couples this input node, in order to export after the semiperiod that will import this time pulse signal of node signal delay.The buffer cell output terminal couples this output node, in order to receive the output signal of this delay cell, extra driving force and output is provided, wherein, N is a natural number, the input node of N shift registor couples the output node of N-1 shift registor, and in addition, this buffer cell is with one first fixing voltage and one second voltage-operated.Display panel receives the signal of inner those output nodes of this drive device for display, in order to display frame.
The present invention adopts fixing voltage supply because of delay cell, and because time pulse signal only need provide to transistorized gate, so the load that time pulse signal is faced is less, so the driving force that time pulse signal does not need to provide too many just can make the shift registor normal operation, make the volume-diminished of clock pulse generator, therefore can reduce layout area, reduce cost.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A illustrate for known application of cold temperature polysilicon technology to be implemented in the circuit diagram of the shift registor on the glass substrate.
Figure 1B is the detailed circuit diagram of SR1 among Figure 1A.
Fig. 1 C illustrates and is known Figure 1A circuit operation oscillogram.
Fig. 2 A illustrates the flat-panel screens circuit block diagram into one embodiment of the invention.
Fig. 2 B illustrates the drive device for display figure into one embodiment of the invention.
Fig. 2 C illustrates the shift registor circuit diagram into one embodiment of the invention.
Fig. 3 A illustrates the shift registor circuit diagram into one embodiment of the invention.
Fig. 3 B illustrates and is one embodiment of the invention Fig. 3 A shift registor circuit operation waveform.
Fig. 4 illustrates and is one embodiment of the invention shift registor circuit diagram.
Fig. 5 illustrates and is one embodiment of the invention shift registor circuit diagram.
Fig. 6 illustrates and is one embodiment of the invention shift registor circuit diagram.
Fig. 7 illustrates and is one embodiment of the invention shift registor circuit diagram.
Fig. 8 illustrates and is one embodiment of the invention shift registor circuit diagram.
Fig. 9 A illustrates and is one embodiment of the invention shift registor circuit diagram.
Fig. 9 B illustrates and is one embodiment of the invention shift registor circuit diagram.
SR, SR1, SR2, SR3: shift registor
10: latch circuit
12: the signal control circuit
14: buffer circuit
101,102,121,122,141,142,301,302,303,304,305,306,307,308:P transistor npn npn
VDD, VSS: fixed power source current potential
CLK1, CLK2, CLK3: time pulse signal
INPUT, Sin: input node
OUT0, OUT1, OUT2, Out1, Out2: output node
20: display panel
22A, 22B: drive device for display
Delay, 200,800: delay cell
Buffer, 210,810: buffer cell
A, b, A, B, C, D: node
CK, XCK: time pulse signal
Vcc, Vss: voltage source
201,202,211,212,812: transistor
Cap: charge storage element
C1, C2: electric capacity
INV: phase inverter
900: on-off element
Embodiment
The present invention proposes a kind of flat-panel screens, as Fig. 2 A, comprises display panel 20 and drive device for display 22A and 22B.The inside of drive device for display 22A and 22B has comprised many shift registor SR.Drive device for display 22A and 22B couple display panel 20, in order to drive panel with display frame.Wherein, drive device for display 22A illustrates the B at Fig. 2 than detail circuits.This drive unit has comprised most shift registor SR, and wherein each shift registor SR inside comprises delay cell Delay and buffer cell Buffer again.Wherein, the circuit of more detailed shift registor SR illustrates the C at Fig. 2.
Please refer to Fig. 2 C shift registor of the present invention, this circuit can be divided into two parts, and first part is that 200, the second parts of delay cell are buffer cell 210.Also marking on the figure and found several nodes, is respectively Sin, CK, XCK, a, b, Vcc and Vss.Wherein Sin is the input node, and CK and XCK are anti-phase each other time pulse signals, and Vcc (noble potential) and Vss (electronegative potential) then are the voltage sources of fixing.And the function of delay cell 200 is that input signal Sin is postponed to export after semiperiod of time pulse signal.Buffer cell 210, the output signal of receive delay unit 200, just the signal of node b provides extra driving force and output.
Please also refer to the transistor 102,103 of Figure 1B and the buffer cell 210 of Fig. 2 C, it should be noted that buffer cell 210 is with fixing Vcc and Vss operation.Yet the shift registor of known Figure 1B is the source/drain at transistor 102 adds time pulse signal CKB.In addition, shift registor proposed by the invention uses four transistors altogether, use two 201,202 and charge storage element Cap of transistor (electric capacity) to do sampling respectively at delay cell 200 and keep (Sample and Hold), and buffer cell 210 uses two transistors 211 and 212 to increase driving force as output.
For the convenience that illustrates, we change single shift registor framework of Fig. 2 C into shift registor that Fig. 3 A places two Fig. 2 B, are respectively SR1 and SR2, and according to the operation waveform of Fig. 3 B as correspondence, please the reader simultaneously with reference to Fig. 3 A and Fig. 3 B.Fig. 3 A has comprised eight P transistor npn npns, is respectively 301,302,303,304,305,306,307 and 308.Also having comprised two electric capacity in addition on the figure, is respectively C1 and C2.In addition, for convenience of description, mark has found several nodes above Fig. 3 A, is respectively input node Sin, node A, Node B, node C, node D, output node Out1 and Out2.Time pulse signal CK and XCK are added in respectively on the delay cell of each shift registor SR1, SR2.In addition, Vcc (noble potential) and Vss (electronegative potential) represent fixing voltage source respectively.
At first, when input node Sin began to transfer electronegative potential to by noble potential, time pulse signal CK also began to transfer electronegative potential to by noble potential, and time pulse signal XCK begins to transfer noble potential to by electronegative potential.Transistor 301 gates received electronegative potential and began conducting this moment, and the gate of transistor 302 receives noble potential and ends.Capacitor C 1 is discharged to electronegative potential via transistor 301.The gate of the transistor 304 in the buffer cell also receives the electronegative potential of time pulse signal CK and conducting makes output node Out1 maintain noble potential.
When clock pulse signal CK begins to transfer noble potential to by electronegative potential, another time pulse signal XCK also begins to transfer electronegative potential to by noble potential, this moment, transistor 301 ended, transistor 302 conductings, the noble potential of Node B begins to discharge by the electric capacity on the node A and makes the gate of transistor 303 receive electronegative potential, transistor 303 beginning conductings this moment.Because time pulse signal CK makes transistor 304 end for noble potential this moment, node A goes up the data (electronegative potential) that stores, and exports output node Out1 to by buffer cell transistor 303 and 304.
Same, when XCK is that electronegative potential is when being received by transistor 305 gates, make transistor 305 begin conductings, capacitor C 2 on the node C begins output node is discharged, stored the data (electronegative potential) of shift registor SR1 output this moment on the capacitor C 2, and the gate of transistor 306 is a noble potential owing to coupling time pulse signal CK, and it is ended, and just keep (Hold) on capacitor C 2 data (electronegative potential) this moment.The gate of the transistor 308 in the buffer cell also receives the electronegative potential of time pulse signal XCK and conducting makes output node Out2 maintain noble potential.
When clock pulse signal XCK begins to transfer noble potential to by electronegative potential, another time pulse signal CK also begins to transfer electronegative potential to by noble potential, this moment, transistor 305 ended, transistor 306 conductings, the noble potential of node D begins to discharge by the electric capacity on the node C and makes the gate of transistor 307 receive electronegative potential, transistor 307 beginning conductings this moment.Because time pulse signal XCK makes transistor 308 end for noble potential this moment, node C goes up the data (electronegative potential) that stores, and exports output node Out2 to by buffer cell transistor 307 and 308.So repeatable operation just can be gone down the transmission of data (electronegative potential) one-level one-level.
Top embodiment is an example only, still has many kinds of embodiments, for example the embodiment of Fig. 4, change all crystals pipe into the N transistor npn npn, and general's Vss (electronegative potential) and Vcc (noble potential) exchange originally, its operator scheme are much at one, and reader Ying Ke deduces voluntarily.The present invention still can use the embodiment of complementary transistor (CMOS), as Fig. 5 and Fig. 6, its operator scheme much at one, reader Ying Ke deduces voluntarily.
Wherein, Fig. 2 B embodiment still can change the embodiment as Fig. 7 into.Capacitor among Fig. 7 couples Vcc originally and changes into and couple a reference potential Vref, and principle of operation is identical, so will not give unnecessary details.Fig. 8 is the another kind of embodiment of the embodiment of the invention, Fig. 8 and Fig. 2 B different be in, the gate of the transistor 212 among Fig. 2 B in the buffer cell 210 couples time pulse signal CK, yet the gate of the transistor 812 of the buffer cell 810 in Fig. 8 couples phase inverter INV output, the phase inverter input couples the output of delay cell 800, its operation is similar in appearance to Fig. 2 B, so will not give unnecessary details.
In addition, Fig. 9 A and Fig. 9 B are a kind of embodiment of the embodiment of the invention, and the difference of Fig. 9 A and Fig. 7 is that Fig. 9 A Duoed an on-off element 900 than Fig. 7.It for example is SR1 that the circuit of present embodiment Fig. 9 A is implemented among Fig. 9 B, and SR1 is output as Out1, and next stage output is Out2, and next stage is output as Out3 again.When Fig. 9 A circuit such as Fig. 9 B serial connection was a plurality of, the control end of gauge tap element 900 must couple output Out3.Implement with this embodiment, more stable output voltage can further be provided.
In sum, adopt fixing voltage supply in the present invention because of delay cell, and time pulse signal is all the driving gate, so can lower the load effect of time pulse signal circuit output, except the minimizing layout area reduces cost, the change of time pulse signal voltage also can not influence output terminal, can alleviate the phenomenon of output terminal concussion.。
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (19)
1. a shift registor is used to drive flat-panel screens, and this shift registor receives input signal and time pulse signal, comprising:
One delay cell has an input end and an output terminal, exports after receiving input signal and postponing semiperiod of this time pulse signal, and wherein this delay cell comprises:
One the first transistor comprises one first end and one second end, and this input end that this first end is this delay cell is according to one first time pulse signal, whether to determine the circuit between this first end of conducting and this second end;
One charge storage element, the one end couples a tertiary voltage, and its other end couples this second end; And
One transistor seconds comprises one the 3rd end and one the 4th end, and the 3rd end couples this second end, and the 4th end is this output terminal of this delay cell, according to one second time pulse signal, whether to determine the circuit between conducting the 3rd end and the 4th end; And
One buffer cell receives the output signal of this delay cell, and extra driving force and output is provided,
Wherein, this buffer cell is with one first fixing voltage and one second voltage-operated.
2. shift registor according to claim 1, wherein this buffer cell comprises:
One the 3rd transistor comprises one first control end, a five terminal and one the 6th end, and this first control end couples the 4th end, and this five terminal couples this second voltage; And
One the 4th transistor comprises one second control end, one the 7th end and one the 8th end, and this second control end couples this time pulse signal, and the 7th end couples the 6th end, and the 8th end couples this first voltage.
3. shift registor according to claim 1, wherein this buffer cell comprises:
One the 3rd transistor comprises one first control end, a five terminal and one the 6th end, and this first control end couples the 4th end, and this five terminal couples this second voltage;
One phase inverter, one input end couple the 4th end; And
One the 4th transistor comprises one second control end, one the 7th end and one the 8th end, and this second control end couples an output terminal of this phase inverter, and the 7th end couples the 6th end, and the 8th end couples this first voltage.
4. shift registor according to claim 2, wherein this buffer cell more comprises:
One the 5th transistor comprises one the 9th end, 1 the tenth end, and the 9th end couples the 6th end, and the tenth end couples this first voltage.
5. shift registor according to claim 4, wherein multistage when this shift registor serial connection, the 5th transistor comprises one the 3rd control end, and the 3rd control end couples this shift registor next stage shift registor buffer cell output.
6. shift registor according to claim 2, wherein the 3rd transistor is a P transistor npn npn and the two one of N transistor npn npn, and its gate is this first control end, and its first source/drain is this five terminal, and its second source/drain is the 6th end.
7. shift registor according to claim 2, wherein the 4th transistor is a P transistor npn npn and the two one of N transistor npn npn, and its gate is this second control end, and its first source/drain is the 7th end, and its second source/drain is the 8th end.
8. shift registor according to claim 3, wherein the 3rd transistor is a P transistor npn npn and the two one of N transistor npn npn, and its gate is this first control end, and its first source/drain is this five terminal, and its second source/drain is the 6th end.
9. shift registor according to claim 3, wherein the 4th transistor is a P transistor npn npn and the two one of N transistor npn npn, and its gate is this second control end, and its first source/drain is the 7th end, and its second source/drain is the 8th end.
10. shift registor according to claim 1, wherein this first transistor is a P transistor npn npn and the two one of N transistor npn npn, and its gate receives this time pulse signal, and its first source/drain is this first end, and its second source/drain is this second end.
11. shift registor according to claim 1, wherein this transistor seconds is a P transistor npn npn and the two one of N transistor npn npn, its gate receives the anti-phase signal of this time pulse signal, and its first source/drain is the 3rd end, and its second source/drain is the 4th end.
12. shift registor according to claim 1, wherein this charge storage element is an electric capacity, and this tertiary voltage equals this first voltage.
13. a drive device for display comprises:
N shift registor, each those shift registor comprises:
One input node;
One output node;
One delay cell, one input end couple this input node, export after receiving this input node signal and postponing semiperiod of this time pulse signal, and wherein this delay cell comprises:
One the first transistor comprises one first end and one second end, and this input end that this first end is this delay cell is according to one first time pulse signal, whether to determine the circuit between this first end of conducting and this second end;
One charge storage element, the one end couples a tertiary voltage, and its other end couples this second end; And
One transistor seconds comprises one the 3rd end and one the 4th end, and the 3rd end couples this second end, and the 4th end is an output terminal of this delay cell, according to one second time pulse signal, whether to determine the circuit between conducting the 3rd end and the 4th end; And
One buffer cell, the one output terminal couples this output node, in order to receive the output signal of this delay cell, provides extra driving force and output,
Wherein, N is a natural number, and the input node of N shift registor couples the output node of N-1 shift registor, and in addition, this buffer cell is with one first fixing voltage and one second voltage-operated.
14. drive device for display according to claim 13, wherein this buffer cell comprises:
One the 3rd transistor comprises one first control end, a five terminal and one the 6th end, and this first control end couples the 4th end, and this five terminal couples this second voltage; And
One the 4th transistor comprises one second control end, one the 7th end and one the 8th end, and this second control end couples this time pulse signal, and the 7th end couples the 6th end, and the 8th end couples this first voltage.
15. drive device for display according to claim 13, wherein this buffer cell comprises:
One the 3rd transistor comprises one first control end, a five terminal and one the 6th end, and this first control end couples the 4th end, and this five terminal couples this second voltage;
One phase inverter, one input end couple the 4th end; And
One the 4th transistor comprises one second control end, one the 7th end and one the 8th end, and this second control end couples an output terminal of this phase inverter, and the 7th end couples the 6th end, and the 8th end couples this first voltage.
16. drive device for display according to claim 13, wherein this charge storage element is an electric capacity, and this tertiary voltage equals this first voltage.
17. a flat-panel screens comprises:
One drive device for display comprises N shift registor, and each those shift registor comprises:
One input node;
One output node;
One delay cell, one input end couple this input node, export after receiving this input node signal and postponing semiperiod of this time pulse signal, and wherein this delay cell comprises:
One the first transistor comprises one first end and one second end, and this input end that this first end is this delay cell is according to one first time pulse signal, whether to determine the circuit between this first end of conducting and this second end;
One charge storage element, the one end couples a tertiary voltage, and its other end couples this second end; And
One transistor seconds comprises one the 3rd end and one the 4th end, and the 3rd end couples this second end, and the 4th end is an output terminal of this delay cell, according to one second time pulse signal, whether to determine the circuit between conducting the 3rd end and the 4th end; And
One buffer cell, the one output terminal couples this output node, in order to receive the output signal of this delay cell, provides extra driving force and output,
Wherein, N is a natural number, and the input node of N shift registor couples the output node of N-1 shift registor, and in addition, this buffer cell is with one first fixing voltage and one second voltage-operated; And
One display panel receives the signal of inner those output nodes of this drive device for display, in order to display frame.
18. flat-panel screens according to claim 17, wherein this buffer cell comprises:
One the 3rd transistor comprises one first control end, a five terminal and one the 6th end, and this first control end couples the 4th end, and this five terminal couples this second voltage; And
One the 4th transistor comprises one second control end, one the 7th end and one the 8th end, and this second control end couples this time pulse signal, and the 7th end couples the 6th end, and the 8th end couples this first voltage.
19. flat-panel screens according to claim 17, wherein this buffer cell comprises:
One the 3rd transistor comprises one first control end, a five terminal and one the 6th end, and this first control end couples the 4th end, and this five terminal couples this second voltage;
One phase inverter, one input end couple the 4th end; And
One the 4th transistor comprises one second control end, one the 7th end and one the 8th end, and this second control end couples an output terminal of this phase inverter, and the 7th end couples the 6th end, and the 8th end couples this first voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100014211A CN100489932C (en) | 2006-01-17 | 2006-01-17 | Panel display, drive device for display and shift temporary register |
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|---|---|---|---|
| CNB2006100014211A CN100489932C (en) | 2006-01-17 | 2006-01-17 | Panel display, drive device for display and shift temporary register |
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| CN101004881A CN101004881A (en) | 2007-07-25 |
| CN100489932C true CN100489932C (en) | 2009-05-20 |
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Families Citing this family (7)
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| CN104299554B (en) * | 2014-08-22 | 2017-07-18 | 京东方科技集团股份有限公司 | Shift register, array base palte and display device |
| CN104464628B (en) * | 2014-12-18 | 2017-01-18 | 京东方科技集团股份有限公司 | Shifting register unit, driving method of shifting register unit, grid drive circuit and display device |
| CN104464642B (en) * | 2014-12-30 | 2016-09-28 | 昆山国显光电有限公司 | GIP circuit and driving method thereof and display floater |
| TWI553621B (en) * | 2015-03-19 | 2016-10-11 | 友達光電股份有限公司 | Shift register |
| TWI579824B (en) * | 2016-04-01 | 2017-04-21 | 瑞鼎科技股份有限公司 | Gate driving circuit |
| CN105741745A (en) * | 2016-05-12 | 2016-07-06 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit and display panel |
| CN110428784A (en) * | 2018-04-27 | 2019-11-08 | 群创光电股份有限公司 | Display panel |
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