CN104464642B - GIP circuit and driving method thereof and display floater - Google Patents
GIP circuit and driving method thereof and display floater Download PDFInfo
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Abstract
The GIP circuit of the present invention, including drive circuit, described drive circuit includes one first circuit and a second circuit, described first circuit includes the first transistor, transistor seconds, third transistor and the first electric capacity, and described second circuit includes the 4th transistor, the 5th transistor, the 6th transistor and the second electric capacity.In the present invention, the signal between the first launch-control line of GIP circuit, the first scan line, the second launch-control line and the second scan line is separate, thus improves the reliability of GIP circuit；Between first launch-control line of GIP circuit and the first scan line, the second launch-control line and the second scan line, there is regular time relation so that the some screen effect of display floater is more preferable.
Description
Technical field
The present invention relates to OLED and show field, particularly relate to a kind of GIP circuit and driving method thereof and show
Show panel.
Background technology
OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) display device has with it
Lightweight, the feature such as volume is little, thickness is thin, be widely used in the terminal presentation facility of various sizes
In, in recent years, along with the development of science and technology, occur in that a kind of by the raster data model of OLED display
Device directly makes new technique GIP (Gate on the glass substrate by mask plate coating technique
Panel, door face board) technology.At present, GIP technology is scanning integrated chip technology on oled panel,
Can reach to save scanning chip, reduce material cost, reduce number of processes and shorten the process time, thus
Reduce liquid crystal panel cost, realize the purpose of narrower frame.
The circuit diagram of GIP circuit of the prior art is with reference to shown in Fig. 1, and GIP circuit includes the first transistor
T1, transistor seconds T2, third transistor T3, the 4th transistor T4 and the 5th transistor T5.When first
Clock holding wire XCK connects grid and the grid of third transistor T3 of the first transistor T1, and second clock is believed
Number line CK connects the source electrode of transistor seconds T2.First grid polar curve Vgh connects the source of the 4th transistor T4
Pole and the source electrode of the 5th transistor T5, second gate line Vgl connects the source electrode of third transistor T3.Typically
, display floater includes multistage GIP circuit, and the source electrode of the first transistor T1 of n-th grade of GIP circuit is even
Connect input signal cable SIN (n), be the input signal of n-th grade of circuit.The second of n-th grade of GIP circuit
The drain electrode of transistor T2 connects the output signal line of n-th grade of circuit, and, the output of n-th grade of GIP circuit
Signal is as input signal SIN (n+1) of (n+1)th grade of GIP circuit.
In prior art, the oscillogram of GIP drives is with reference to shown in Fig. 2, and first grid polar curve Vgh is high electricity
Flat, second gate line Vgl is low level, and the first clock cable XCK and second clock holding wire CK divides
Shu Chu the contrary digital signal of low and high level.When the first clock cable XCK saltus step is low level, the
1 grade of GIP circuit input signal line SIN (1) level inputs a low level, jumps at second clock holding wire CK
When becoming low level, the 1st grade of GIP circuit output low level, as the input signal of the 2nd grade of GIP circuit
SIN (2), and so on, the output signal of n-th grade of circuit is as the input signal of (n+1)th grade of circuit.
But, if the output signal of certain stage circuit is abnormal, then can cause follow-up all abnormal signals, give aobvious
Show that panel brings the worst.Additionally, GIP circuit structure of the prior art is complicated, technology difficulty is big.
Summary of the invention
It is an object of the invention to, it is provided that a kind of GIP circuit and driving method thereof, upper level GIP circuit and
Signal between next stage GIP circuit is separate, makes GIP circuit simple, and avoids the occurrence of certain one-level letter
Number exception causes the situation that follow-up signal is abnormal.
For solving above-mentioned technical problem, the present invention provides a kind of GIP circuit, including drive circuit, described in drive
Galvanic electricity road includes one first circuit and a second circuit；
Described first circuit includes: the first transistor, is connected between first grid polar curve and primary nodal point, its
Grid is connected to the first launch-control line；Transistor seconds, is connected to described first grid polar curve and the first scanning
Between line, its grid is connected to described first launch-control line；Third transistor, is connected to second gate line
And between described first scan line, its grid is connected to described primary nodal point；And first electric capacity, it is connected to
Between first clock cable and described primary nodal point；
Described second circuit includes: the 4th transistor, is connected between described first grid polar curve and secondary nodal point,
Its grid is connected to the second launch-control line；5th transistor, is connected to described first grid polar curve and second and sweeps
Retouching between line, its grid is connected to described second launch-control line；6th transistor, is connected to described second
Between gate line and described second scan line, its grid is connected to described secondary nodal point；And second electric capacity,
It is connected between described secondary nodal point and second clock holding wire.
Optionally, described the first transistor to described 6th transistor is P-type TFT.
Optionally, described the first transistor and described transistor seconds are all by described first emission control line traffic control
System, described 4th transistor and the 5th transistor are all by described second emission control line traffic control.
Optionally, described third transistor is by described first clock signal line traffic control, described 6th transistor
Controlled by described second clock holding wire.
Optionally, described GIP circuit includes multiple described drive circuit repeated arrangement, described each driving electricity
Road is connected with first grid polar curve, second gate line, the first clock cable and second clock holding wire respectively.
Optionally, the signal that described first grid polar curve provides is high level, and the signal that second gate line provides is
Low level.
Accordingly, the present invention also provides for the driving method of a kind of above-mentioned GIP circuit, and the scan period includes first
Time period, the second time period, the 3rd time period and the 4th time period, the signal that first grid polar curve provides is high
Level, the signal that second gate line provides is low level, wherein,
In first circuit:
In first time period, the control signal that the first launch-control line provides is low level, the first transistor
Opening with transistor seconds, third transistor is closed, the first scan line output high level；
Within the second time period, the control signal that the first launch-control line provides is high level, the first transistor
Being turned off with transistor seconds, the clock signal that the first clock cable provides is high level, and the first electric capacity fills
Electricity so that primary nodal point keeps high level, third transistor is closed, the first scan line output high level；
Within the 3rd time period, the control signal that the first launch-control line provides is high level, the first transistor
Being turned off with transistor seconds, the clock signal that the first clock cable provides is low level, and the first electric capacity is put
Electricity so that primary nodal point is low level, and third transistor is opened, the first scan line output low level；
Within the 4th time period, the control signal that the first launch-control line provides is low level, the first transistor
Opening with transistor seconds, third transistor is closed, the first scan line output high level；
In second circuit:
In first time period with in the second time period, the control signal that the second launch-control line provides is low level,
4th transistor and the 5th transistor are opened, and the 6th transistor is closed, the second scan line output high level；
Within the 3rd time period, the control signal that the second launch-control line provides is high level, the 4th transistor
Being turned off with the 5th transistor, the clock signal that second clock holding wire provides is high level, and the second electric capacity fills
Electricity so that secondary nodal point keeps high level, the 6th transistor to close, the second scan line output high level；
Within the 4th time period, the control signal that the second launch-control line provides is high level, the 4th transistor
Being turned off with the 5th transistor, the clock signal that second clock holding wire provides is low level, and the second electric capacity is put
Electricity so that secondary nodal point is low level, and the 6th transistor is opened, the second scan line output low level.
Optionally, between the 3rd time period and the 4th time period, also included for the 5th time period, in the 5th time
In inner segment, the control signal that the first launch-control line provides is high level, the letter that the first clock cable provides
Number become high level from low level, the first scan line output low level.
Optionally, after the 4th time period, also included for the 6th time period, in the 6th time inner segment, second
The control signal that launch-control line provides is high level, and the signal that second clock holding wire provides is become by low level
For high level, the second scan line output low level.
The present invention also provides for a kind of display floater, including OLED pixel drive circuit and above-mentioned GIP electricity
Road, described OLED pixel drive circuit uses the first scan line of described GIP circuit and the second scan line defeated
The signal gone out is as gate drive signal, and the LED control signal of described OLED pixel drive circuit is as institute
State the first launch-control line and the input signal of the first launch-control line of GIP circuit.
Compared with prior art, the GIP circuit that the present invention provides, by arranging the first electricity in the driving circuit
Road and second circuit, wherein, the second scan line in the first scan line in the first circuit and second circuit it
Between separate, thus avoid the occurrence of certain one-level abnormal signal and cause the abnormal situation of follow-up signal, additionally,
GIP circuit structure in the present invention is simple, it is possible to reduce the cabling in the number of transistor and circuit.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of GIP circuit in prior art；
Fig. 2 is the drive waveforms signal graph of GIP circuit in prior art；
Fig. 3 is the circuit diagram of GIP circuit of the present invention；
Fig. 4 is the drive waveforms signal graph of GIP circuit of the present invention.
Detailed description of the invention
Below in conjunction with schematic diagram, GIP circuit and the driving method thereof of the present invention are described in more detail,
Which show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can revise and be described herein
The present invention, and still realize the advantageous effects of the present invention.Therefore, description below be appreciated that for
Those skilled in the art's is widely known, and is not intended as limitation of the present invention.
Referring to the drawings the present invention the most more particularly described below in the following passage.According to following explanation and
Claims, advantages and features of the invention will be apparent from.It should be noted that, accompanying drawing all uses the simplest
The form changed and all use non-ratio accurately, only in order to convenient, aid in illustrating the embodiment of the present invention lucidly
Purpose.
The core concept of the present invention is, has OLED pixel drive circuit and GIP electricity in display floater
Road, the output signal in GIP circuit is as the gate drive signal of OLED pixel drive circuit, OLED
The LED control signal of pixel-driving circuit is as the input signal in GIP circuit.In GIP circuit first
The output signal of circuit and the input signal of second circuit are independent each other so that the first circuit and the second electricity
Do not affect between road, it is thus possible to improve GIP circuit and the reliability of pixel-driving circuit.
Further, during driving, between output signal and the input signal of GIP circuit, there is regular time relation,
The point screen effect making display floater is more preferable.
Below in conjunction with Fig. 3-Fig. 4, GIP circuit and the driving method thereof of the present invention are specifically described.
The present invention provides GIP circuit, and including drive circuit 1, described drive circuit 1 includes with the first circuit
10 and a second circuit 20.Described first circuit 10 include the first transistor T1, transistor seconds T2,
Three transistor T3 and one first electric capacity C1.Wherein, the first transistor T1 is connected to first grid polar curve Vgh
And between primary nodal point A, its grid is connected to the first launch-control line EM1；Transistor seconds T2 connects
Between described first grid polar curve Vgh and the first scan line Scan1, its grid is connected to described first and launches
Control line EM1；Third transistor T3 is connected to second gate line Vgl and described first scan line Scan1
Between, its grid is connected to described primary nodal point A；First electric capacity C1 is connected to the first clock cable XCK
And between described primary nodal point A.Wherein, the first transistor T1 and described transistor seconds T2 all passes through institute
Stating the first launch-control line EM1 to control, described third transistor T3 passes through described first clock cable XCK
Control.
Described second circuit 20 include the 4th transistor T4, the 5th transistor T5, the 6th transistor T6 and
Second electric capacity C2.Wherein, the 4th transistor T4 is connected between first grid polar curve Vgh and secondary nodal point B,
Its grid is connected to the second launch-control line EM2；5th transistor T5 is connected to described first grid polar curve Vgh
And between the second scan line Scan2, its grid is connected to described second launch-control line EM2；6th crystal
Pipe T6 is connected between second gate line Vgl and described second scan line Scan2, and its grid is connected to described
Secondary nodal point B；Second electric capacity C2 is connected between second clock holding wire CK and described secondary nodal point B.
Wherein, described 4th transistor T4 and the 5th transistor T5 is all controlled by described second launch-control line EM2
System, described 6th transistor T6 is controlled by described second clock holding wire CK.
It is understood that described GIP circuit includes multiple described drive circuit 1 repeated arrangement, respectively with
First grid polar curve Vgh, second gate line Vgl, the first clock cable XCK and second clock holding wire
CK connects.
With reference to shown in Fig. 4, as the another side of the present invention, the present invention also provides for the GIP that more than one are described
The driving method of circuit.In the driving method of the present invention, described first grid polar curve Vgh is constantly in high electricity
Flat, second gate line Vgl is constantly in low level.The scan period of the driving method of the present invention includes first
Time period t the 1, second time period t the 2, the 3rd time period t 3 and the 4th time period t 4.
Individually below the state of the first circuit 10 and each time period of second circuit 20 is described:
First circuit 10:
In first time period t1, the control signal that the first launch-control line EM1 provides is low level, now,
The first transistor T1 and transistor seconds T2 opens, and the output signal of first grid polar curve Vgh is brilliant by first
Body pipe T1 inputs primary nodal point A, and the grid voltage of third transistor T3 is high level, third transistor T3
Close, additionally, the first scan line scan1 directly turns on first grid polar curve Vgh, the first scan line scan1
Output high level；
In the second time period t 2, the control signal that the first launch-control line EM1 provides is become high from low level
Level, the first transistor T1 and transistor seconds T2 are turned off, first clock cable XCK provide time
Clock signal is high level, now, the first electric capacity C1 charging so that primary nodal point A keeps high level, the 3rd
The grid of transistor T3 is that high level is closed.In the second time period t 2, due to the first scan line scan1
The middle parasitic capacitance (for illustrating in figure) that exists makes the first scan line scan1 keep the shape of first time period t1
State and export high level.
In the 3rd time period t 3, the control signal that the first launch-control line EM1 provides is high level, first
Transistor T1 and transistor seconds T2 is turned off, and the clock signal that the first clock cable XCK provides is by height
Level saltus step is low level, first electric capacity C1 electric discharge so that the current potential of primary nodal point A down for low level,
The grid of third transistor T3 is that low level is opened, now, and the first scan line scan1 and second gate line
Vgl turns on and output low level.
In the 4th time period t 4, the control signal that the first launch-control line EM1 provides is low level, first
Transistor T1 and transistor seconds T2 opens, and the first scan line scan1 passes through the 5th transistor T2 and first
Gate line Vgh turns on and exports high level.In 4th time period t 4, the state and first of the first circuit 10
The state of time period t 1 is identical.
It is also preferred that the left between the 3rd time period t 3 and the 4th time period t 4, the driving method of the present invention also includes
One the 5th time period t 5, in the 5th time period t 5, the control signal that the first launch-control line EM1 provides is
High level, now the first transistor T1 and transistor seconds T2 closes, and the first clock cable XCK provides
Signal be high level by low transition, third transistor T3 close.First scan line scan1 exists
Parasitic capacitance (not shown) makes the first scan line scan1 keep the state of the 3rd time period t 3 to export
Low level.When entering the 4th time period t 4, the first launch-control line EM1 is low level by high level saltus step,
The first transistor T1 and transistor seconds T2 opens, the first scan line scan1 output high level.
Second circuit 20:
In first time period t1 and the second time period t 2, the control letter that the second launch-control line EM2 provides
Number being low level, the 4th transistor T4 and the 5th transistor T5 opens, and secondary nodal point B is high level, then
6th transistor T6 closes, the second scan line scan2 output high level.
In the 3rd time period t 3, the control signal that the second launch-control line EM2 provides is high level, the 4th
Transistor T4 and the 5th transistor T5 is turned off, and the clock signal that second clock holding wire CK provides is high
Level, the second electric capacity C2 charging so that secondary nodal point B keeps high level, the 6th transistor T6 to close.
It is understood that in the 3rd time period t 3, owing to the second scan line scan2 equally existing parasitic electricity
Holding (for illustrating in figure) makes the second scan line scan2 keep the state of the second time period t 2 to export high electricity
Flat.
In the 4th time period t 4, the control signal that the second launch-control line EM2 provides keeps high level, the
Four transistor T4 and the 5th transistor T5 close, and the clock signal that second clock holding wire CK provides is by height
Level saltus step is low level, the second electric capacity C2 electric discharge so that secondary nodal point B is low level, the 6th transistor
T6 opens, and the second scan line scan2 connects the low electricity of output by the 6th transistor T6 and second gate line Vgl
Flat.
It is also preferred that the left also include the 6th time period t 6 after the 4th time period t 4, in the 6th time inner segment t6,
The control signal that second launch-control line EM2 provides keeps high level, the 4th transistor T4 and the 5th crystal
Pipe T5 closes, and the signal that second clock holding wire CK provides is high level by low transition.Same,
In the 4th time period t 4, owing to parasitic capacitance makes the second scan line present in the second scan line scan2
Scan2 keeps the state of the 4th time period t 4 and output low level.And after the 6th time period t 6, second
The control signal that launch-control line EM2 provides is low level by high level saltus step, second clock holding wire CK
Keeping high level, the 4th transistor T4 and the 5th transistor T5 opens, and the 6th transistor T6 closes, and second
Scan line scan2 output high level.
The driving method of the second circuit 20 in GIP circuit and the driving method of the first circuit 10 are similar so that
GIP the first circuit 10 and second circuit 20 output signals to OLED pixel circuit.
It should be noted that the present invention uses the first circuit 10 all use three crystal with second circuit 20
Pipe and an electric capacity, relative to prior art, decrease the quantity of transistor, and decrease prior art
In the input cabling of SIN, reduce the area of chip so that can be realized by the GIP circuit of the present invention
The display floater of narrower frame.
General, display floater has OLED pixel drive circuit and GIP circuit, therefore, this
Bright also provide for a kind of display floater, the first scan line scan1 in GIP circuit and the second scan line scan2
Output signal as the gate drive signal in OLED pixel drive circuit, OLED pixel drive circuit
LED control signal is as the first emissioning controling signal EM1 in GIP circuit and the second emissioning controling signal
EM2.In the display floater of the present invention, the output signal and second of the first circuit 10 in described GIP circuit
The input signal of circuit 20 is independent each other, is independent of each other, thus improves GIP circuit and pixel is driven
The reliability on galvanic electricity road.
Additionally, the first launch-control line EM1 of GIP circuit and the first scan line scan1, the second emission control
There is regular time relation so that the some screen effect of display floater between line EM2 and the second scan line scan2
Fruit is more preferably.
It is understood that the GIP circuit of the present invention both may be used for display panels (Liquid Crystal
Display, LCD), it is also possible to for active-matrix organic light emitting diode (AMOLED) panel (Active Matrix/Organic
Light Emitting Diode, AMOLED), if the every one-level electricity that can realize in GIP circuit of the present invention
Separate between the signal on road it is independent of each other, improves reliability and the display effect of display floater, also exist
Within the thought range of present invention protection.
The first electricity in sum, in the GIP circuit of present invention offer and driving method thereof, in GIP circuit
The input signal of the output signal on road 10 and second circuit 20 is independent each other so that the first circuit 10 with
Do not affect between second circuit 20, it is thus possible to improve GIP circuit reliability.Further, originally
In the display floater that invention provides, there is between output signal and the input signal of GIP circuit regular time pass
System so that the some screen effect of display floater is more preferable.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a GIP circuit, it is characterised in that include that drive circuit, described drive circuit include one first
Circuit and a second circuit；
Described first circuit includes: the first transistor, is connected between first grid polar curve and primary nodal point, its
Grid is connected to the first launch-control line；Transistor seconds, is connected to described first grid polar curve and the first scanning
Between line, its grid is connected to described first launch-control line；Third transistor, is connected to second gate line
And between described first scan line, its grid is connected to described primary nodal point；And first electric capacity, it is connected to
Between first clock cable and described primary nodal point；
Described second circuit includes: the 4th transistor, is connected between described first grid polar curve and secondary nodal point,
Its grid is connected to the second launch-control line；5th transistor, is connected to described first grid polar curve and second and sweeps
Retouching between line, its grid is connected to described second launch-control line；6th transistor, is connected to described second
Between gate line and described second scan line, its grid is connected to described secondary nodal point；And second electric capacity,
It is connected between described secondary nodal point and second clock holding wire.
2. GIP circuit as claimed in claim 1, it is characterised in that described the first transistor to the most described the
Six transistors are P-type TFT.
3. GIP circuit as claimed in claim 1, it is characterised in that described the first transistor and described the
Two-transistor is all by described first emission control line traffic control, and described 4th transistor and the 5th transistor are the most logical
Cross described second emission control line traffic control.
4. GIP circuit as claimed in claim 1, it is characterised in that described third transistor is by described
First clock signal line traffic control, described 6th transistor is controlled by described second clock holding wire.
5. GIP circuit as claimed in claim 1, it is characterised in that described GIP circuit includes multiple institute
State drive circuit repeated arrangement, described each drive circuit respectively with first grid polar curve, second gate line,
One clock cable and second clock holding wire connect.
6. GIP circuit as claimed in claim 1, it is characterised in that the letter that described first grid polar curve provides
Number being high level, the signal that second gate line provides is low level.
7. the driving method of the GIP circuit as described in claim 1-6 any one, it is characterised in that
Scan period includes first time period, the second time period, the 3rd time period and the 4th time period, first grid
The signal that line provides is high level, and the signal that second gate line provides is low level, wherein,
In first circuit:
In first time period, the control signal that the first launch-control line provides is low level, the first transistor
Opening with transistor seconds, third transistor is closed, the first scan line output high level；
Within the second time period, the control signal that the first launch-control line provides is high level, the first transistor
Being turned off with transistor seconds, the clock signal that the first clock cable provides is high level, and the first electric capacity fills
Electricity so that primary nodal point keeps high level, third transistor is closed, the first scan line output high level；
Within the 3rd time period, the control signal that the first launch-control line provides is high level, the first transistor
Being turned off with transistor seconds, the clock signal that the first clock cable provides is low level, and the first electric capacity is put
Electricity so that primary nodal point is low level, and third transistor is opened, the first scan line output low level；
Within the 4th time period, the control signal that the first launch-control line provides is low level, the first transistor
Opening with transistor seconds, third transistor is closed, the first scan line output high level；
In second circuit:
In first time period with in the second time period, the control signal that the second launch-control line provides is low level,
4th transistor and the 5th transistor are opened, and the 6th transistor is closed, the second scan line output high level；
Within the 3rd time period, the control signal that the second launch-control line provides is high level, the 4th transistor
Being turned off with the 5th transistor, the clock signal that second clock holding wire provides is high level, and the second electric capacity fills
Electricity so that secondary nodal point keeps high level, the 6th transistor to close, the second scan line output high level；
Within the 4th time period, the control signal that the second launch-control line provides is high level, the 4th transistor
Being turned off with the 5th transistor, the clock signal that second clock holding wire provides is low level, and the second electric capacity is put
Electricity so that secondary nodal point is low level, and the 6th transistor is opened, the second scan line output low level.
8. the driving method of GIP circuit as claimed in claim 7, it is characterised in that in the 3rd time period
And also including for the 5th time period between the 4th time period, in the 5th time inner segment, the first launch-control line carries
The control signal of confession is high level, and the signal that the first clock cable provides is become high level from low level, the
Scan line output low level.
9. the driving method of GIP circuit as claimed in claim 7, it is characterised in that in the 4th time period
The most also included for the 6th time period, in the 6th time inner segment, the control signal that the second launch-control line provides
For high level, the signal that second clock holding wire provides is become high level from low level, the second scan line output
Low level.
10. a display floater, including OLED pixel drive circuit and such as claim 1-6 any one
Described GIP circuit, it is characterised in that described OLED pixel drive circuit uses described GIP circuit
The signal of the first scan line and the output of the second scan line is as gate drive signal, and described OLED pixel drives
The LED control signal of circuit is as the first launch-control line of described GIP circuit and the second launch-control line
Input signal.
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| CN106328040B (en) * | 2016-10-31 | 2019-06-28 | 昆山国显光电有限公司 | GIP circuit and its driving method and panel display apparatus |
| KR102490159B1 (en) * | 2016-10-31 | 2023-01-20 | 엘지디스플레이 주식회사 | Gate driving circuit and display device having in-cell touch sensor using the same |
| CN107871471B (en) * | 2017-12-08 | 2020-04-10 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving method thereof and display device |
| CN109147639B (en) * | 2018-08-09 | 2021-09-17 | 信利半导体有限公司 | Grid scanning circuit and scanning method, grid driving circuit and display panel |
| CN111540319A (en) * | 2020-04-23 | 2020-08-14 | 福建华佳彩有限公司 | Panel driving circuit, control method and panel |
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| TWI282081B (en) * | 2002-08-13 | 2007-06-01 | Au Optronics Corp | Shift register circuit |
| KR101107714B1 (en) * | 2005-04-22 | 2012-01-25 | 엘지디스플레이 주식회사 | A shift register and a method for driving the same |
| CN100489932C (en) * | 2006-01-17 | 2009-05-20 | 奇晶光电股份有限公司 | Panel display, drive device for display and shift temporary register |
| CN102650751B (en) * | 2011-09-22 | 2014-08-06 | 京东方科技集团股份有限公司 | GOA (Gate Driver on Array) circuit, array base plate and liquid crystal display device |
| CN104167192B (en) * | 2014-07-22 | 2017-01-18 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
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2014
- 2014-12-30 CN CN201410843334.5A patent/CN104464642B/en active Active
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| CN104464642A (en) | 2015-03-25 |
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