TWI319880B - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
TWI319880B
TWI319880B TW095134776A TW95134776A TWI319880B TW I319880 B TWI319880 B TW I319880B TW 095134776 A TW095134776 A TW 095134776A TW 95134776 A TW95134776 A TW 95134776A TW I319880 B TWI319880 B TW I319880B
Authority
TW
Taiwan
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Application number
TW095134776A
Other languages
Chinese (zh)
Other versions
TW200729224A (en
Inventor
Sung-Joo Ha
Ho-Youb Cho
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of TW200729224A publication Critical patent/TW200729224A/en
Application granted granted Critical
Publication of TWI319880B publication Critical patent/TWI319880B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
TW095134776A 2005-09-28 2006-09-20 Semiconductor memory device TWI319880B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050090841 2005-09-28
KR1020060037512A KR100772708B1 (en) 2005-09-28 2006-04-26 Semiconductor memory device

Publications (2)

Publication Number Publication Date
TW200729224A TW200729224A (en) 2007-08-01
TWI319880B true TWI319880B (en) 2010-01-21

Family

ID=37959243

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095134776A TWI319880B (en) 2005-09-28 2006-09-20 Semiconductor memory device

Country Status (3)

Country Link
KR (1) KR100772708B1 (en)
CN (1) CN1941181B (en)
TW (1) TWI319880B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101274204B1 (en) * 2007-08-08 2013-06-17 삼성전자주식회사 Precharge method of local input output line and semiconductor memory device for using the method
KR100893576B1 (en) * 2007-08-29 2009-04-17 주식회사 하이닉스반도체 Semiconductor memory device
KR101311455B1 (en) * 2007-08-31 2013-09-25 삼성전자주식회사 Semiconductor memory device and the method for layout thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3780580B2 (en) * 1995-10-16 2006-05-31 セイコーエプソン株式会社 Semiconductor memory device and electronic device using the same
US5828610A (en) * 1997-03-31 1998-10-27 Seiko Epson Corporation Low power memory including selective precharge circuit
KR100290286B1 (en) * 1999-02-05 2001-05-15 윤종용 A semiconductor memory device with fast input/output line precharge scheme and a method of precharging input/output lines thereof
KR100333642B1 (en) * 1999-06-30 2002-04-24 박종섭 Local databus precharge method for high speed operation of semiconductor memory device
KR100408716B1 (en) * 2001-06-29 2003-12-11 주식회사 하이닉스반도체 Autoprecharge apparatus having autoprecharge gapless function protect circuit in semiconductor memory device
US6661721B2 (en) * 2001-12-13 2003-12-09 Infineon Technologies Ag Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits
KR100939116B1 (en) * 2003-07-23 2010-01-28 주식회사 하이닉스반도체 Semiconductor memory device for reducing current consumption during precharge operation

Also Published As

Publication number Publication date
KR100772708B1 (en) 2007-11-02
CN1941181A (en) 2007-04-04
KR20070035937A (en) 2007-04-02
CN1941181B (en) 2010-12-08
TW200729224A (en) 2007-08-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees