KR100893576B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a circuit for controlling the continuous precharge operation with a relatively short time interval (within 2tck) in a semiconductor memory device having a plurality of banks, according to an aspect of the present invention, Banks; Precharge information signal generation means for generating a precharge information signal having information for precharging at least one of the plurality of banks in response to a precharge bank selection signal and a precharge command; And bank precharge signal generation means for generating a bank precharge signal in response to the precharge information signal received through a local line, and outputting the bank precharge signal to a plurality of global lines respectively connected to the plurality of banks. There is provided a semiconductor memory device having a.

Precharge, Bank

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a circuit for controlling precharge operation in a semiconductor memory device having a plurality of banks, and more particularly in a semiconductor memory device having a plurality of banks. The present invention relates to a circuit for controlling the continuous precharge operation over a short time interval (within 2 tck).

The reason for the existence of the semiconductor memory device is to store data. That is, the purpose is to store / update / use the information meant by data by reading or writing data stored in the semiconductor memory device.

In order to achieve this purpose, in the case of a semiconductor memory device, especially a DRAM, it is necessary to repeatedly read and write data in a cell.

First, a word line is selected by entering an active state in response to an active command. This means that data stored in a cell of the DRAM is ready to be transferred out of the cell.

In addition, a read or write operation is performed in response to a read or write command to read or write data from any one of a plurality of cells included in the word line.

Thereafter, the precharge operation is performed in response to the precharge command. This is an operation in which the DRAM returns to the state before the DRAM enters the active state and is returned to the initial state so that the DRAM may perform the read or write operation again.

1 is a block diagram illustrating a process of generating a bank precharge signal in a semiconductor memory device having a plurality of banks according to the related art.

Referring to FIG. 1, a process of generating a bank precharge signal in a semiconductor memory device having a plurality of banks may correspond to a precharge bank select signal (Precharge Bank Sel, All Bank Precharge) and a precharge command. A precharge information signal generator 10 for generating a precharge information signal PCGP6, PBANKT <0: 8>, ALL_PRE having information for precharging at least one bank among a plurality of banks, and a relatively long The bank precharge signal PRECHARGE <0: 7> is generated in response to the precharge information signals PCGP6, PBANKT <0: 8> and ALL_PRE received through the global line, and the bank precharge signal PRECHARGE <0: 7) is provided with a bank precharge signal generator 12 for delivering a plurality of banks through a relatively short local line.

Here, the precharge information signal generator 10 may decode the precharge command to generate a first signal PCGP6 of the precharge information signal for controlling the precharge operation. 100 and a second signal PBANKT <0: for selecting at least one bank to be precharged from among a plurality of banks in response to the first signal of the precharge bank selection signal (Precharge Bank Sel). 8) and a precharge information signal for controlling precharging all the banks in response to the second signal (All Bank Precharge) of the precharge bank selection signal. All bank precharge controllers 140 generating the third signal ALL_PRE are provided.

In addition, the bank precharge signal generation unit 12 may include a first charge of the precharge information signal to at least one bank selected in response to the second signal PBANKT <0: 8> of the precharge information signal among the plurality of banks. Output the bank precharge signal PRECHARGE <0: 7> generated in response to the signal PCGP6, or output the precharge information signal to all the plurality of banks in response to the third signal ALL_PRE of the precharge information signal. The bank precharge signal PRECHARGE <0: 7> generated in response to the one signal PCGP6 is output.

FIG. 2 is a block diagram showing a position where a circuit for generating a precharge information signal and a circuit for generating a bank precharge signal are disposed in a semiconductor memory device having a plurality of banks according to the related art.

Referring to FIG. 2, a precharge information signal PCGP6 and PBANKT <0: 8> in a semiconductor memory device including a plurality of banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 according to the related art. , Where the precharge information signal generator 10 for generating ALL_PRE and the bank precharge signal generator 12 for generating the bank precharge signals PRECHARGE <0: 7> are disposed. .

Specifically, the bank precharge signal generation unit 12 for generating the bank precharge signals PRECHARGE <0: 7> includes a plurality of banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7. In the drawing, one bank precharge signal generator 12 is disposed per two banks, which are shown for convenience of description, and thus the actual circuit may be different. -It can be seen that the arrangement.

On the other hand, the precharge information signal generator 10 for generating the precharge information signals PCGP6, PBANKT <0: 8>, ALL_PRE includes a plurality of banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, It can be seen that BANK6, BANK7) and the bank precharge signal generation unit 12 are located at the center of the semiconductor memory device that is not relatively close to each other.

The operation waveforms of the semiconductor memory device having the arrangement as described above are as follows.

3A is a timing diagram illustrating a waveform of a bank precharge signal generated when a precharge information signal is continuously input at intervals of 2 tck or more in a semiconductor memory device having a plurality of banks according to the related art.

Referring to FIG. 3A, in a semiconductor memory device having a plurality of banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 according to the related art, the first signal PCGP6 of the precharge information signal is 2 tck. Although the waveforms of the bank precharge signals PRECHARGE <0> and PRECHARGE <1>, which are generated when they are continuously input at the above intervals, are normally recognized, the first signal PCGP6 of the precharge information signal is relatively detected in the intermediate process. It can be seen that a lot of distortion is caused by noise while passing through a global line having a long section.

In detail, the first signal PCGP6 of the precharge information signal generated by the precharge information signal generator 10 has an ideal clean waveform. -In the actual circuit, it is more likely that the waveform is distorted more than the drawing. However, since the drawing is comparatively illustrated, a more ideal waveform is shown. -

Thus, when the first signal PCGP6 of the precharge information signal having the ideal clean waveform is input to the bank precharge signal generation unit 12 via the global line, the noise generated during the passage of the global line ( It is relatively crushed by noise.

However, the bank precharge signal generator 12 generates the bank precharge signals PRECHARGE <0> and PRECHARGE <1> because the bank precharge signal generator 12 reproduces and recognizes the waveform again. The bank precharge signals (PRECHARGE <0>, 0PRECHARGE <1>) generated by the D-types again have an ideal clean waveform.

However, in order for the operation waveform of the semiconductor memory device as described above, the first signal PCGP6 of the precharge information signal continuously generated by the precharge information signal generator 10 should have an interval of 2 tck or more. This is because the following problem occurs when the first signal PCGP6 of the precharge information signal continuously generated by the precharge information signal generation unit 10 has an interval of 2 tck or less.

3B is a timing diagram illustrating waveforms of bank precharge signals generated when the precharge information signals are continuously input at intervals of 2 tck or less in a semiconductor memory device having a plurality of banks according to the prior art.

Referring to FIG. 3B, in a semiconductor memory device including a plurality of banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 according to the related art, the first signal PCGP6 of the precharge information signal is 2 tck. It can be seen that the bank precharge signals PRECHARGE <0> and PRECHARGE <1>, which are generated when they are continuously input at the following intervals, are not normally recognized. That is, when the first signal PCGP6 of the precharge information signal is continuously input, the precharge operation should occur twice. The zero signal PRECHARGE <0> of the bank precharge signal corresponding to the zeroth bank BANK0 is generated. It can be seen that only the precharge operation occurs, and the precharge operation does not occur in the first signal PRECHARGE <1> of the bank precharge signal corresponding to the first bank BANK1.

In detail, the first signal PCGP6 of the precharge information signal generated by the precharge information signal generator 10 has an ideal clean waveform. -In the actual circuit, it is more likely that the waveform is distorted more than the drawing. However, since the drawing is comparatively illustrated, a more ideal waveform is shown. -

Thus, when the first signal PCGP6 of the precharge information signal having the ideal clean waveform is input to the bank precharge signal generation unit 12 via the global line, the noise generated during the passage of the global line ( It is relatively crushed by noise. At this time, the first signal PCGP6 of the consecutively input precharge information signal has a too short interval (2tck), and the first signal PCGP6 of the first precharge information signal and the second input prefree It is difficult to distinguish the first signal PCGP6 of the charge information signal.

Therefore, when the bank precharge signal generation unit 12 repeats the waveform again, the first signal PCGP6 of the precharge information signal is recognized as though it was input only once even though the signal was input twice in succession. This causes a problem of generating the bank precharge signals PRECHARGE <0> and PRECHARGE <1>.

Due to the problems described above, in the semiconductor memory device according to the related art, a minimum time, which is represented by 2 tck here, has to be kept when the precharge command is continuously inserted. This has made semiconductor memory devices unable to operate at higher speeds, which tend to operate at ever higher speeds.

The present invention is to solve the problems of the prior art as described above, and stably free even when a precharge command is continuously applied at a relatively short time interval (within 2 tck) in a semiconductor memory device having a plurality of banks. It is an object of the present invention to provide a semiconductor memory device capable of performing a charge operation.

According to an aspect of the present invention for achieving the above technical problem, a plurality of banks; Precharge information signal generation means for generating a precharge information signal having information for precharging at least one of the plurality of banks in response to a precharge bank selection signal and a precharge command; And bank precharge signal generation means for generating a bank precharge signal in response to the precharge information signal received through a local line, and outputting the bank precharge signal to a plurality of global lines respectively connected to the plurality of banks. There is provided a semiconductor memory device having a.

According to another aspect of the present invention for achieving the above technical problem, in a method of operating a semiconductor memory device having a plurality of banks, at least one of the plurality of banks in response to a precharge bank selection signal and a precharge command Generating a precharge information signal having information for precharging the above banks; And generating a bank precharge signal in response to the precharge information signal received through a local line, and outputting the bank precharge signal to a plurality of global lines connected to the plurality of banks, respectively. An operation method of is provided.

According to the present invention, when a precharge command is input to perform a precharge operation in a semiconductor memory device having a plurality of banks, the precharge command is continuously input at a relatively short time interval (within 2 tck). In addition, there is an effect of performing a stable precharge operation by changing the arrangement of the components of the semiconductor memory device so that the bank precharge signal generated in response to the precharge command is independently transmitted to each bank.

In addition, by reducing the number of bank precharge signals transmitted to each bank, there is an effect of reducing the number of global lines used to transfer the bank precharge signal, thereby reducing the area of the semiconductor memory device. There is.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is to make the disclosure of the present invention complete and to those of ordinary skill in the art It is provided to fully inform the category.

4 is a block diagram illustrating a process of generating a bank precharge signal of a semiconductor memory device having a plurality of banks according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a process of generating a bank precharge signal PRECHARGE <0: 7> of a semiconductor memory device having a plurality of banks according to an embodiment of the present invention may include a precharge bank selection signal Precharge Bank Sel. Generates precharge information signals PCGP6, PBANKT <0: 8>, ALL_PRE having information for precharging at least one or more banks of the plurality of banks in response to the All Bank Precharge and Precharge Commands The precharge information signal generator 40 and the bank precharge signal PRECAHRGE <0: 8 in response to the precharge information signals PCGP6, PBANKT <0: 8>, ALL_PRE received through a relatively short local line. Bank precharge signal generator 42 for generating &quot;) and outputting the bank precharge signals PRECAHRGE <0: 8> to a plurality of relatively long global lines respectively connected to the plurality of banks.

Here, the precharge information signal generator 40 may decode the precharge command to generate a first signal PCGP6 of the precharge information signal for controlling the precharge operation. 400 and a second signal PBANKT <0 for selecting at least one bank to be precharged among a plurality of banks in response to a first signal of the precharge bank selection signal (Precharge Bank Sel). And a precharge information signal for controlling precharging all the banks in response to the second signal (All Bank Precharge) of the precharge bank selection signal. And all bank precharge controllers 440 generating the third signal ALL_PRE.

In addition, the bank precharge signal generation unit 42 may perform at least one global line selected from the plurality of global lines in response to the second signal PBANKT4 <0: 7> of the precharge information signal. Precharge information is output to all the plurality of global lines by outputting the bank precharge signal PRECHARGE <0: 7> generated in response to the first signal PCGP6 or in response to the third signal ALL_PRE of the precharge information signal. The bank precharge signal PRECHARGE <0: 7> generated in response to the first signal PCGP6 of the signal is output.

FIG. 5 is a block diagram illustrating a position where a circuit for generating a precharge information signal and a circuit for generating a bank precharge signal are disposed in a semiconductor memory device having a plurality of banks according to an exemplary embodiment of the present invention.

Referring to FIG. 5, precharge information signals PCGP6 and PBANKT <0 are provided in a semiconductor memory device including a plurality of banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 according to an exemplary embodiment of the present invention. : 8>, a position where the precharge information signal generator 40 for generating ALL_PRE and the bank precharge signal generator 42 for generating the bank precharge signal PRECHARGE <0: 7> are disposed Able to know.

Specifically, the precharge information signal generator 40 for generating the precharge information signals PCGP6, PBANKT <0: 8>, ALL_PRE generates the bank precharge signals PRECHARGE <0: 7>. The bank precharge signal generator 42 is relatively close to the semiconductor memory device.

On the other hand, the plurality of banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7 are not relatively close to the precharge information signal generator 40 and the bank precharge signal generator 42. It can be seen that it is arranged.

That is, the precharge information signal generator 10 and the semiconductor memory device including the banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 according to the related art illustrated in FIG. 2 described above. A semiconductor memory having a plurality of banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 according to an exemplary embodiment of the present invention, compared to the bank precharge signal generation unit 12 disposed not to be adjacent to each other. In the device, the precharge information signal generator 40 and the bank precharge signal generator 42 are arranged in close proximity.

This is because a problem in the related art is relatively long in the process in which the first signal PCGP6 of the precharge information signal generated by the precharge information signal generator 10 is transferred to the bank precharge signal generator 12. This is because the first signal PCGP6 of the precharge information signal is damaged by the noise by using the global line.

Therefore, when looking at the operation waveform of the semiconductor memory device having the arrangement according to the embodiment of the present invention described above it can be seen that the problems of the prior art as follows.

FIG. 6 is a timing diagram illustrating waveforms of a bank precharge signal generated when a precharge information signal is continuously input at intervals of 2 tck or less in a semiconductor memory device having a plurality of banks according to an exemplary embodiment of the present invention. to be.

6, a first signal PCGP6 of a precharge information signal of a semiconductor memory device having a plurality of banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 according to an exemplary embodiment of the present invention. It can be seen that the waveforms of the bank precharge signals PRECHARGE <0> and PRECHARGE <1>, which are generated when) are continuously input at intervals of 2 tck or less, are normally recognized. At this time, although the bank precharge signals PRECHARGE <0> and PRECHARGE <1> are distorted by noise in the intermediate process transmitted through a relatively long global line, the bank precharge signals PRECHARGE <0> and PRECHARGE <1> Note that it does not correlate with the normal recognition of the waveform.

In detail, the first signal PCGP6 of the precharge information signal generated by the precharge information signal generator 40 has an ideal clean waveform. -In the actual circuit, it is more likely that the waveform is distorted more than the drawing. However, since the drawing is comparatively illustrated, a more ideal waveform is shown. -

In this manner, the first signal PCGP6 of the precharge information signal having the ideal clean waveform is formed by the bank precharge signal PRERECHARGE <0>, as shown by the adjacent bank precharge signal generation unit 42. PRECHARGE <1>) is generated.

Subsequently, when the bank precharge signals PRECHARGE <0> and PRECHARGE <1> having an ideal clean waveform shape are input to the plurality of banks BANK0 and BANK1 via a plurality of global lines having relatively long intervals, The noise generated while passing through the global line is relatively distorted.

However, since the bank precharge signals PRECHARGE <0> and PRECHARGE <1> are transferred to the banks BANK0 and BANK1 using different global lines, the bank precharge signals in the banks BANK0 and BANK1, respectively. There is no problem in performing the precharge operation by recognizing the input of (PRECHARGE <0>, PRECHARGE <1>).

Therefore, in the semiconductor memory device having the arrangement according to the embodiment of the present invention, even if the precharge command is continuously input within 2 tck, it is recognized by the plurality of banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7. It can be seen that it is possible to perform a precharge operation.

As described above, according to the embodiment of the present invention, when a precharge command is input to perform a precharge operation in a semiconductor memory device having a plurality of banks, a relatively short time interval (within 2 tck) is provided. Even when the precharge command is continuously inputted, a circuit for receiving the precharge command and generating the precharge information signals PCGP8, PBANKT4 <0: 7>, ALL_PRE and the precharge information signals PCGP8, PBANKT4 <0: 7>, circuits generating the bank precharge signals PRECHARGE <0: 7> in close proximity to each other in response to ALL_PRE may be used to stably perform precharge operations in a plurality of banks.

Further, in the prior art, the precharge information signals PCGP8, PBANKT4 <0: 7>, ALL_PRE are transferred to a plurality of banks through a relatively long global line, whereas in the embodiment of the present invention, the bank precharge signal PRECHARGE By passing <0: 7> to a plurality of banks through a relatively long global line, the number of global lines that must be used to perform the precharge operation can be reduced.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

1 is a block diagram illustrating a process of generating a bank precharge signal in a semiconductor memory device having a plurality of banks according to the prior art.

2 is a block diagram showing a position where a circuit for generating a precharge information signal and a circuit for generating a bank precharge signal are disposed in a semiconductor memory device having a plurality of banks according to the prior art;

3A is a timing diagram showing waveforms of bank precharge signals generated when a precharge information signal is continuously input at intervals of 2 tck or more in a semiconductor memory device having a plurality of banks according to the prior art;

3B is a timing diagram showing waveforms of bank precharge signals generated when the precharge information signals are continuously input at intervals of 2 tck or less in a semiconductor memory device having a plurality of banks according to the prior art;

4 is a block diagram illustrating a process of generating a bank precharge signal of a semiconductor memory device having a plurality of banks according to an exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing a position where a circuit for generating a precharge information signal and a circuit for generating a bank precharge signal are disposed in a semiconductor memory device having a plurality of banks according to an embodiment of the present invention; FIG.

FIG. 6 is a timing diagram illustrating waveforms of a bank precharge signal generated when a precharge information signal is continuously input at intervals of 2 tck or less in a semiconductor memory device having a plurality of banks according to an exemplary embodiment of the present invention. FIG.

* Explanation of symbols for main parts of the drawings

10, 40: precharge information signal generator

100, 400: precharge command decoding unit

120, 420: precharge bank selector

140, 440: all bank precharge control unit

12, 42: bank precharge signal generator

Claims (7)

Multiple banks; Precharge information signal generation means for generating a precharge information signal having information for precharging at least one of the plurality of banks in response to a precharge bank selection signal and a precharge command; And Bank precharge signal generating means for generating a bank precharge signal in response to the precharge information signal received through a local line, and outputting the bank precharge signal to a plurality of global lines respectively connected to the plurality of banks. A semiconductor memory device having a. The method of claim 1, The precharge information signal generating means, A precharge command decoding unit configured to decode the precharge command to generate a first signal of the precharge information signal for controlling a precharge operation; A precharge bank selector configured to generate a second signal of the precharge information signal for selecting at least one bank to be precharged among the plurality of banks in response to the first signal of the precharge bank select signal; And all bank precharge controllers for generating a third signal of the precharge information signal for controlling precharging all of the plurality of banks in response to the second signal of the precharge bank selection signal. Semiconductor memory device. The method of claim 2, The bank precharge signal generating means, Outputting the bank precharge signal generated in response to the first signal of the precharge information signal to at least one global line selected in response to the second signal of the precharge information signal among the plurality of global lines; A semiconductor memory device. The method of claim 2, The bank precharge signal generating means, And outputting the bank precharge signal generated in response to the first signal of the precharge information signal to all the plurality of global lines in response to the third signal of the precharge information signal. In the method of operating a semiconductor memory device having a plurality of banks, Generating a precharge information signal having information for precharging at least one of the plurality of banks in response to a precharge bank selection signal and a precharge command; And Generating a bank precharge signal in response to the precharge information signal received through a local line, and outputting the bank precharge signal to a plurality of global lines respectively connected to the plurality of banks Method of operating a semiconductor memory device comprising a. The method of claim 5, The generating of the precharge information signal may include: Decoding the precharge command to generate a first signal of the precharge information signal for controlling a precharge operation; Generating a second signal of the precharge information signal for selecting at least one bank to be precharged among the plurality of banks in response to the first signal of the precharge bank selection signal; And generating a third signal of the precharge information signal for controlling precharging all of the plurality of banks in response to the second signal of the precharge bank selection signal. How it works. The method of claim 6, The outputting of the bank precharge signal may include: Outputting the bank precharge signal generated in response to a first signal of the precharge information signal to at least one global line selected in response to a second signal of the precharge information signal among the plurality of global lines; And And outputting the bank precharge signal generated in response to the first signal of the precharge information signal to all of the plurality of global lines in response to the third signal of the precharge information signal. Method of operation of a memory device.

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