TWI318404B - Method of forming nonvolatile memory and nonvolatile floating gate memory array - Google Patents

Method of forming nonvolatile memory and nonvolatile floating gate memory array

Info

Publication number
TWI318404B
TWI318404B TW095148283A TW95148283A TWI318404B TW I318404 B TWI318404 B TW I318404B TW 095148283 A TW095148283 A TW 095148283A TW 95148283 A TW95148283 A TW 95148283A TW I318404 B TWI318404 B TW I318404B
Authority
TW
Taiwan
Prior art keywords
nonvolatile
floating gate
forming
memory
memory array
Prior art date
Application number
TW095148283A
Other languages
Chinese (zh)
Other versions
TW200733116A (en
Inventor
Masaaki Higashitani
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/316,474 external-priority patent/US7655536B2/en
Priority claimed from US11/316,654 external-priority patent/US7495294B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200733116A publication Critical patent/TW200733116A/en
Application granted granted Critical
Publication of TWI318404B publication Critical patent/TWI318404B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
TW095148283A 2005-12-21 2006-12-21 Method of forming nonvolatile memory and nonvolatile floating gate memory array TWI318404B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/316,474 US7655536B2 (en) 2005-12-21 2005-12-21 Methods of forming flash devices with shared word lines
US11/316,654 US7495294B2 (en) 2005-12-21 2005-12-21 Flash devices with shared word lines

Publications (2)

Publication Number Publication Date
TW200733116A TW200733116A (en) 2007-09-01
TWI318404B true TWI318404B (en) 2009-12-11

Family

ID=38256847

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095148283A TWI318404B (en) 2005-12-21 2006-12-21 Method of forming nonvolatile memory and nonvolatile floating gate memory array

Country Status (3)

Country Link
EP (1) EP1964170A2 (en)
TW (1) TWI318404B (en)
WO (1) WO2007081642A2 (en)

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1423449A (en) * 1973-07-27 1976-02-04 Standard Telephones Cables Ltd Semiconductor device
US4185319A (en) * 1978-10-04 1980-01-22 Rca Corp. Non-volatile memory device
US4651183A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation High density one device memory cell arrays
US5712179A (en) * 1995-10-31 1998-01-27 Sandisk Corporation Method of making triple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gates
US6063688A (en) * 1997-09-29 2000-05-16 Intel Corporation Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
JP2000228509A (en) * 1999-02-05 2000-08-15 Fujitsu Ltd Semiconductor device
KR100331563B1 (en) * 1999-12-10 2002-04-06 윤종용 NAND-type flash memory device and method for operating the same
JP2002198524A (en) * 2000-12-27 2002-07-12 Nec Microsystems Ltd Semiconductor device
DE10207131B4 (en) * 2002-02-20 2007-12-20 Infineon Technologies Ag Process for forming a hardmask in a layer on a flat disk
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US7221008B2 (en) * 2003-10-06 2007-05-22 Sandisk Corporation Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory
US7355237B2 (en) * 2004-02-13 2008-04-08 Sandisk Corporation Shield plate for limiting cross coupling between floating gates

Also Published As

Publication number Publication date
WO2007081642A2 (en) 2007-07-19
TW200733116A (en) 2007-09-01
WO2007081642A3 (en) 2008-03-13
EP1964170A2 (en) 2008-09-03

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees