TWI313899B - Chip package process - Google Patents
Chip package process Download PDFInfo
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- TWI313899B TWI313899B TW094147526A TW94147526A TWI313899B TW I313899 B TWI313899 B TW I313899B TW 094147526 A TW094147526 A TW 094147526A TW 94147526 A TW94147526 A TW 94147526A TW I313899 B TWI313899 B TW I313899B
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- substrate
- glue
- wafer
- holes
- sealant
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Links
- 238000000034 method Methods 0.000 title claims description 9
- 230000008569 process Effects 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 37
- 238000007789 sealing Methods 0.000 claims description 29
- 239000003292 glue Substances 0.000 claims description 28
- 239000000565 sealant Substances 0.000 claims description 22
- 238000012858 packaging process Methods 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 238000005538 encapsulation Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 18
- 239000008393 encapsulating agent Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000032798 delamination Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 244000007835 Cyamopsis tetragonoloba Species 0.000 description 1
- 108010010803 Gelatin Proteins 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000000499 gel Substances 0.000 description 1
- 239000008273 gelatin Substances 0.000 description 1
- 229920000159 gelatin Polymers 0.000 description 1
- 235000019322 gelatine Nutrition 0.000 description 1
- 235000011852 gelatine desserts Nutrition 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 230000002262 irrigation Effects 0.000 description 1
- 238000003973 irrigation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
Description
13138¾¾ 65twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種半導體製程（Semic〇nduct〇r 广广，卿是有關於1晶片封裝製131383⁄43⁄4 65twf.doc/006 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semiconductor process (Semic〇nduct〇r Guangguang, Qing is related to 1 chip packaging system)
Package Process) 〇 【先前技術】 ^年來^者電子技彳㈣日新月異以Package Process) 〇 【Previous Technology】 ^Years of Electronic Technology (4)
興起，使得更人性化、功能fv ^ J _ 力月匕更锃的電子產品不斷地推陳出 新，並朝向輕、薄、短、小的趨勢設計。在半導體產業中， 積體電路（Integrated Circuits，IC)的生產主要分為三個階The rise has made the electronic products that are more user-friendly and functional, and are increasingly designed to be light, thin, short and small. In the semiconductor industry, the production of integrated circuits (ICs) is mainly divided into three stages.
段.積體電路的設計、積體電路的製作及積體電路的封裝 (package),等。在積體電路的封裝中，裸晶片是經由晶圓 (wafer)製作、電路設計、光罩製作以及切割晶圓等步驟 而完成，而每-顆由晶圓切割所形成的裸晶片，經由裸晶 片上之焊塾（bonding _)與封裝基板（sub伽⑹電性 連接，再以封裝膠體（molding c〇mp〇und)將裸晶片加以 包覆，其目的在於防止裸晶片受到外界溼度影響及雜塵污 染，並提供裸晶片與外部電路之間電性連接的媒介，以構 成一晶片封裝結構。 然而，由於封裝膠體與封裝基板之間存在熱膨脹係數 (Coefficient of Thermal Expansion, CTE)的差異，尤其是大 尺寸的陣列基板更容易隨著封裝製程中工作溫度的變化而 變形，使得封裝膠體與封裝基板間的接合容易受到熱應力 (thermal stress)的破壞而造成翹曲變形（warpage)或脫層 (S、 5 13138¾ 5twf.doc/〇〇6 (delamination)的現象，進而降低晶片封裝結構之可靠度以 及使用壽命。 【發明内容】 - 本發明之目的疋知1供—種晶片封裝製程，以解決晶片 • 封裝製程中，封裝膠體與基板間之接合容易受到熱應^破 壞的問題。 本發明提出-種晶片封裝製程，其包括下列步驟。首 • 先，提供一基板，此基板具有至少一注膠口以及多個封膠 區，其中每-個封勝區向外設置有多個定膠孔，而這些定 膠孔是貫穿此基板。然後，配置多個晶片於這些封膠區 其中這些晶片疋電性連接於基板。接著，覆蓋一模具 chase)之模穴（m〇ld cavity)於這些封膠區及這些定膠孔 上，並填入-封膠於注膠口，使封膠流入模穴中二接著， 固化（curing)封谬，且封膠會於每一個定膠孔中 體’其中这些柱體是卡固於所對應之定膠孔中 ·=:封膠區以外的區域’以形成多個獨立分開i晶: -個實施例中’這些定膠孔例如是排列於每 在本發明之-實施例中 ' 口之兩侧。 —才勝區例如是位於注膠 • 林發明之1施例中，封膠此 個柱體之後，封膠更於這些定膠孔之^t疋孔中形成多 而卡合部是固定於所_之定佩+。端形成-卡合部， 1313899 17765twf.d〇c/〇〇6 在本發明之 'π…丫，你対膠/瓜八模穴_之步驟中， 更包括流入相鄰二封膠區之間的一流道，以形成一連接塊。 在本發明之一實施例中，晶片例如是以打線接合的大 式電性連接基板。 万 在本發明之-實施例中，這些定膠孔例如是 穿孔而形成的。 田、 本發明是設置多個貫穿基板之定膠孔於封膠區The design of the integrated circuit, the fabrication of the integrated circuit, and the packaging of the integrated circuit. In the package of the integrated circuit, the bare wafer is completed by steps of wafer fabrication, circuit design, mask fabrication, and wafer dicing, and each bare wafer formed by wafer dicing is via bare The bonding pad on the wafer is electrically connected to the package substrate (sub-gamma (6), and then the bare wafer is coated with a molding gel, the purpose of which is to prevent the bare wafer from being affected by external humidity and The dust is contaminated and provides a medium for electrically connecting the bare chip to the external circuit to form a chip package structure. However, due to the difference in coefficient of thermal expansion (CTE) between the package body and the package substrate, In particular, a large-sized array substrate is more easily deformed as the operating temperature changes in the packaging process, so that the joint between the encapsulant and the package substrate is easily damaged by thermal stress to cause warpage or dislocation. Layer (S, 5 131383⁄4 5twf.doc / 〇〇 6 (delamination) phenomenon, which in turn reduces the reliability and service life of the chip package structure. </ RTI> - The purpose of the present invention is to provide a chip packaging process to solve the problem that the bonding between the encapsulant and the substrate is susceptible to thermal damage during the wafer and packaging process. The present invention proposes a chip packaging process. The method includes the following steps: First, a substrate is provided, the substrate has at least one glue injection port and a plurality of glue sealing zones, wherein each of the sealing zones is provided with a plurality of fixing holes outward, and the fixing holes are The substrate is inserted through the substrate. Then, a plurality of wafers are disposed in the sealing regions, wherein the wafers are electrically connected to the substrate. Then, a mold cavity covering a mold is applied to the sealing regions and the sealing regions. On the glue hole, fill in the sealant at the glue injection port, so that the sealant flows into the cavity, and then cure, and the sealant will be in each of the fixed glue holes, wherein the cylinders are Clamping in the corresponding fixed glue hole ·=: the area outside the sealant zone' to form a plurality of independently separated i-crystals: - In these embodiments, 'these fixed glue holes are arranged, for example, in each of the present invention-implemented In the example, the two sides of the mouth. Injection molding • In the invention example of Lin invention, after sealing the cylinder, the sealant is formed more in the holes of the fixed glue holes, and the engaging portion is fixed at the fixed pin +. Forming-engaging portion, 1313899 17765twf.d〇c/〇〇6 In the step of 'π...丫, your gelatin/guar eight mold hole_ of the present invention, further includes flowing into the adjacent two sealant regions Preferably, in one embodiment of the invention, the wafer is, for example, a large electrical connection substrate bonded by wire bonding. In the embodiment of the invention, the glue holes are for example perforated. Forming. Tian, the invention is to set a plurality of fixed glue holes through the substrate in the sealing area
緣，使得進行封膠製程後之封膠區與定膠孔中分別形 裝膠體與柱體，其中封裝膠體與柱體是一體成型，而晶片 封裝結構即可藉由卡固於定膠孔巾之柱體來減低封裝^體 與基板間因減力破壞而發生之翹曲變形或脫層的現^肢 “為讓本發明之上述和其他目的、倾和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 ° 【實施方式】 圖1Α至圖1Ε是本發明較佳實施例之一種晶片封裝製 程的流程圖，圖2是圖1Α中之基板的上視圖。首先，^ 圖1Α與圖2所示，提供一基板110’例如是大尺寸的陣列 封裝基板。基板11〇具有一個或多個注膠口 112以及多個 封膠區114,其中每一個封膠區114向外設置有多個^穿 基板110的定膠孔〇1，而這些定膠孔〇1例如是排列於每 一個封膠區114之周圍，且封膠區114位於注膠口 112之 兩側。在本實施财’定耗01例如是應用雷射穿孔或 機械鑽孔而形成的。 13138¾¾ 65twf.d〇c/〇〇5 然後，如圖IB所示，配置多個晶片12〇於 120^^ 土板110。在本貫施例中，日日日4 12〇例如是藉 以打線接合的方式電性連接於基板110。當然，曰曰片 亦可以透過覆晶接合技術來電性連接於基板⑽。 ，著，如圖1C所示’利用模具200進行封膠製程。 模具200包括一上模具2〇2與一下模具2〇4，其中上 ，之模&210*覆蓋於這些封膠區114(請參考圖⑷2 這些定膠孔Q1上。同時’填人—封膠14()於注膠口⑴， 以使封膠14G流入模穴210中，其中封膠⑽例如是一膠 餅。在本實施例巾，例如是將封膠14〇填入灌部（⑽)⑽ 内’再藉由對封膠140施壓，以將封膠14〇經由注膠口 ιι2 注入模具200内，模穴21〇中即充滿封膠14〇。在上述之 封膠製程巾’基板11〇與_14〇進行預熱以使融 之封勝14〇可順利地注入模穴21〇中。此外，本實施例;; 模具2〇〇更包括多條流道（未繪示）。當基板11〇被上模具 202與下模具204夾持時，這些流道是位於相鄰之二封膠 區114之間，因此注入模穴21〇之封膠14〇可以藉由流道 而流至每一個模穴210中。 接著，如圖1D所示，固化封膠14〇，封膠14〇即分 別於每一個封膠區114(請參考圖1A)與定膠孔〇丨中形成 封裝膠體140a與柱體i40b，這些柱體140b並卡固於所對 應之定膠孔01中。其中，封裝膠體14〇a例如是包覆晶片 120、焊線130及部份之基板11〇，以提供保護的功能，而 Ι313899_/006 在流道中之封膠140則固化成連接相鄰兩封裝膠體14〇a 的一連結塊（未繪示）。The edge is formed into a colloid and a cylinder respectively in the sealing zone and the fixing hole after the sealing process, wherein the encapsulant and the cylinder are integrally formed, and the chip encapsulation structure can be stuck in the fixing burr The cylinder is used to reduce the warpage deformation or delamination of the package body and the substrate due to the reduction of force reduction. "To make the above and other objects, advantages and advantages of the present invention more obvious, the following DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, a detailed description will be given below. [Embodiment] FIG. 1A to FIG. 1A are flowcharts of a wafer packaging process according to a preferred embodiment of the present invention, and FIG. 2 is a diagram of FIG. A top view of the substrate. First, as shown in FIG. 1A and FIG. 2, a substrate 110' is provided, for example, a large-sized array package substrate. The substrate 11 has one or more glue injection ports 112 and a plurality of glue seal regions 114. Each of the sealing regions 114 is disposed outwardly with a plurality of fixing holes 穿1 of the substrate 110, and the fixing holes 例如1 are arranged, for example, around each of the sealing regions 114, and the sealing region 114 Located on both sides of the injection port 112. In this implementation, the 'consumption consumption 01, for example Formed by laser perforation or mechanical drilling. 131383⁄43⁄4 65twf.d〇c/〇〇5 Then, as shown in FIG. 1B, a plurality of wafers 12 are disposed on the 120^^ soil plate 110. In the present embodiment 4, 12, for example, is electrically connected to the substrate 110 by wire bonding. Of course, the cymbal can also be electrically connected to the substrate (10) through flip chip bonding technology. As shown in FIG. 1C, The mold 200 is subjected to a sealing process. The mold 200 includes an upper mold 2〇2 and a lower mold 2〇4, wherein the upper mold & 210* covers the sealant area 114 (please refer to Figure (4) 2 for these fixed glue holes Q1. At the same time, 'filling the sealant 14 () in the glue injection port (1), so that the sealant 14G flows into the cavity 210, wherein the sealant (10) is, for example, a rubber cake. In the present embodiment, for example, the sealant 14 〇 Fill the filling part ((10)) (10) and then press the sealing glue 140 to inject the sealing material 14 into the mold 200 through the injection opening ιι2, and the cavity 21〇 is filled with the sealing material 14〇. The above-mentioned sealing process towel 'substrate 11 〇 and _14 〇 are preheated so that the sealed seal 14 〇 can be smoothly injected into the cavity 21 。. In this embodiment, the mold 2 includes a plurality of flow paths (not shown). When the substrate 11 is clamped by the upper mold 202 and the lower mold 204, the flow paths are located in the adjacent two sealants 114. Therefore, the sealant 14 which is injected into the cavity 21 can be flowed into each of the cavities 210 by the flow path. Next, as shown in FIG. 1D, the sealant 14 is cured, and the sealant 14 is respectively Each of the sealing regions 114 (please refer to FIG. 1A) and the fixing holes 形成 form an encapsulating body 140a and a cylinder i40b, and the cylinders 140b are locked in the corresponding fixing holes 01. The encapsulant 14 is encapsulated therein. For example, the package 120, the bonding wire 130, and a portion of the substrate 11 are coated to provide a protective function, and the sealing member 140 of the crucible 313899_/006 is solidified to connect the adjacent two encapsulants 14a. A link block (not shown).
另外，本實施例之定膠孔例如是一倒T型之貫孔，而 在封膠140固化後，封膠140會於定膠孔〇1的末端固化 成* ^合部140b。如此一來，包覆晶片120之封裝膠體 140a即可藉由定膠孔〇1中之卡合部140b，緊密地附著於基 板110上。當然’本發明在此並不限定定膠孔〇1的形狀、 數量以及排列的方式。 值得一提的是，由於本實施例在封膠區114(請參考圖 1A)外緣設置有多個貫穿基板11〇的定膠孔〇1，且定膠孔 〇1中會形成與封裝膠體140a—體成型之柱體14%，因此 藉由柱體140b可使封裝膠體140a與基板11〇緊密地接 合，以防止封裝膠體140a與基板110間發生翹^變形 (warpage)或脫層（delamination)的現象。 之後，如圖1E所示，切除基板11〇之封膠區114(請 參考圖1A)以外的區域，以形成多觸立分開之晶 ^構300(圖1E中僅繪示1個）。在另—實施例中，亦可同、 裝賴UOa以及定膠孔〇1中的柱體雇於切 割後ί基板UG上’以形成尺梢大的晶片封裳結構。 穿其本發明是在每—個封龍外料置多個貫 丨:v (膠孔’使得進行封膠製程後之封膠區上盘定膠 ==，:=，其中物體與柱體C 柱#炎试# B曰片封裝、、、°構即可藉由卡固於定膠孔中之 減低封裝膠體與基《之熱應力破壞。詳細的說， 1313899 17765twf,doc/006In addition, the fixing hole of the embodiment is, for example, an inverted T-shaped through hole, and after the sealing agent 140 is cured, the sealing agent 140 is solidified at the end of the fixing hole 1 into a joint portion 140b. In this way, the encapsulant 140a covering the wafer 120 can be closely attached to the substrate 110 by the engaging portion 140b in the fixing hole 1. Of course, the invention does not limit the shape, number and arrangement of the glue holes 1 here. It is worth mentioning that, in this embodiment, a plurality of fixing holes 贯穿1 penetrating through the substrate 11 设置 are disposed on the outer edge of the sealing region 114 (please refer to FIG. 1A ), and the sealing colloid is formed in the fixing hole 〇 1 . The 140a-body-molded cylinder is 14%, so that the encapsulant 140a can be tightly bonded to the substrate 11 by the pillar 140b to prevent warpage or delamination between the encapsulant 140a and the substrate 110. )The phenomenon. Thereafter, as shown in Fig. 1E, the regions other than the encapsulation region 114 (please refer to Fig. 1A) of the substrate 11 are cut away to form a multi-contact separation crystal 300 (only one is shown in Fig. 1E). In another embodiment, the UUa and the cylinder in the fixed orifice 1 may be employed on the cutting substrate UG to form a wafer-like structure having a large tip. In the present invention, a plurality of passes are placed in each of the outer seals of the sealing dragon: v (the glue hole is used to make the glue on the sealing zone after the sealing process ==, :=, where the object and the cylinder C Column #炎试# B 曰 片 片 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,
當封裝製程之工作溫度變動時，卡固於定膠孔中之柱體可 大幅降低因封裝膠體之熱膨脹係數與基板之熱膨 L 匹配所產生的各種熱應力問題。如此，本發明即可增加晶 片封裝結構之可靠度以及使用壽命。 a θθ 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1Α至圖1Ε是本發明較佳實施例之一種晶片封 程的流程圖。 、衣 圖2是圖1Α中之基板的上視圖。 【主要元件符號說明】 110 基板 112 注膠口 114 封膠區 120 晶片 130 烊線 140 封膠 140a :封裝膠體 140b :柱體 140b ’：卡合部 200 ： 模具 210 ： 模穴 1313899 17765twf.doc/006 220 :灌部 01 :定膠孔When the operating temperature of the packaging process changes, the cylinders stuck in the fixing holes can greatly reduce various thermal stress problems caused by the thermal expansion coefficient of the encapsulant and the thermal expansion of the substrate. Thus, the present invention can increase the reliability and service life of the wafer package structure. a θθ Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 1 is a flow chart of a wafer package in accordance with a preferred embodiment of the present invention. Figure 2 is a top view of the substrate of Figure 1 . [Main component symbol description] 110 substrate 112 glue injection port 114 sealing area 120 wafer 130 twist line 140 sealant 140a: encapsulant 140b: cylinder 140b ': engaging portion 200: mold 210: cavity 1313899 17765twf.doc/ 006 220 : Irrigation part 01 : fixed glue hole
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