1313875 (1) 玖、發明說明 【發明所屬之技術領域】 本發明有關一種微電子裝置中所用的金屬箔晶片電阻 器的製造方法’特別是關於一種以精簡的程序製造出高精 密度之金屬泊晶片電阻器的方法。 【先前技術】 在微電子裝置製造技術中常用金屬箔〈片〉電阻器作 爲電路中的被動電路元件和/或承載電路元件。金屬箔電 阻器可被用於微電子製品中。 用於混合電路微電子製品之中時，通常是以本技藝習 用的方法，對絕緣基板，例如玻璃絕緣基板或陶瓷絕緣基 板’上黏合的金屬箔電阻材料覆蓋層以光蝕刻方式成型， 從而形成金屬箔電阻器，然後再將此等絕緣基板的各部份 分開，以形成分立的金屬箔晶片電阻器。 在一種習知金屬箔晶片電阻器的製造方法中，包括以 下步驟：（1 )提供一絕緣基板，（2 )將特定金屬箔黏合 於該基板的表面，（3 )以光蝕刻的方式使光阻膜形成電 阻線路，（4)使用鐳射燒蝕法或其他機械式加工法，更 改電阻線路的長度或面積以達到預定之電阻値，（5 )將 個別電阻器分離，（6 )將電阻層與導線焊接，（7 )覆蓋 上密封劑，（8 )外殼封裝，（9 )測試篩檢，（1 〇 )包裝 出貨。在上述的製程中，涉及多次的圖形化塗佈程序，需 要繁複的校正及加工，同時由於需要利用諸如鑽石刀片的 -4- I313875 (2) 切割方式將個別電阻器分離，並將導線與電阻層以焊接方 式結合以及需要以注模封裝的手續，亦使得製造的時間及 成本增加。 在現行的習知金屬箔晶片電阻器的製造方法中，常見 的尺寸爲6.3笔米長、3.2毫米寬的晶粒大小，右要再往 微小化發展，諸如2.0毫米長' 1.2毫米寬的金屬箔晶片 電阻器’則無法實現。 【發明內容】 針對上述習知技術的問題，本發明提供一種金屬箔晶 片電阻器的製造方法，可藉由精簡的製程，製出具備高精 密度之金屬箔電阻器。 本發明的一目的爲提供一種金屬箔晶片電阻器的製造 方法，可製成一系列的分立金屬箔晶片電阻器。 本發明的另一目的爲提供一種金屬箔晶片電阻器的製 造方法，可免於使用各種光蝕刻方法，材料和裝置。 本發明的另一目的爲提供一種金屬箔晶片電阻器的製 造方法，可不需使用焊線以及注模封裝設備。 本發明的另一目的爲提供一種金屬箔晶片電阻器的製 造方法，可製出一種易於分立的金屬箔晶片電阻器。 本發明的另一目的爲提供一種金屬箱晶片電阻器的製 造方法，此一製造方法可以往微小化發展達到〇 _ 6毫米 長、0.3毫米寬的金屬箔晶片電阻器。 -5- 1313875 (3) 【實施方式】 以下參照所附圖式， 的金屬箔晶片電阻器的製 圖1爲說明依照本發 法的一實施例的第一步驟 由絕緣性材料所製成，其 板。 基板1上具有多數條 2不僅限於例如橫向單一 向上亦有另一組彼此等距 面呈棋盤狀的溝槽分部。 圖2爲說明依照本發 一實施例的第二步驟的截 1經進一步加工後的結果 溝槽2 (圖形中所示之V 導體引線（電極）層3。 導體引線（電極）層3， (例如，網版印刷）所形 金，金，金合金，銅’銅 等之導體油墨群組中所選 乾燥及燒結而形成一連串 體油墨通常在攝氏150J 下，燒結5到1 5分鐘的闲 圖3爲說明依照本發 以一較佳實施例的形式對本發明 造方法做進一步的解釋。 明的金屬箔晶片電阻器的製造方 的截面圖。參照圖1，基板1係 作爲金屬箔晶片電阻器的製程基 互相平行且等距的溝槽2，溝槽 方向延伸，在垂直於此方向的縱 且平行的溝槽，使基板1的上表 明的金屬箔電阻器的製造方法的 面圖。其中所示者係圖1之基板 :從圖2中可看出於基板1上的 )反面位置上所形成的一連串下 在本發明之方法中，這一連串下 是採用一種非光蝕刻的塗佈法 成。網版印刷是將包括銀，銀合 合金；鈀，鈀合金；鎳，鎳合金 用的一種導體油墨，再經印刷， 下導體引線（電極）層3 ;該導 !1 900度（或更低）的溫度條件 F間。 明的金屬箔晶片電阻器的製造方 -6- 1313875 (4) 法的一實施例的第三步驟的截面圖；其係採用一種非光蝕 刻的塗佈法（例如，網版印刷）所形成，網版印刷是將接 著劑均勻塗佈於基板上。 圖4爲說明依照本發明的金屬箔晶片電阻器的製造方 法的一實施例的第四步驟的截面圖。見圖4之剖面圖，其 中所示者係圖3之基板1經進一步與金屬箔5貼合加工後 的結果；圖4是圖3所示基板1的一剖面圖，但在其表面 上另貼合一金屬箔電阻層5;該金屬箔電阻層5需預先製 成與絕緣基板的棋盤狀中心線一致的棋盤狀金屬箔網，以 便精準對位貼附在絕緣基板上，該金屬箔電阻層5可用金 屬箔電阻器製造技藝習知的其中任何一種電阻材料形成， 例如，鎳鉻合金電阻材料鎳鉻鋁合金電阻材料，錳銅合金 電阻材料，鎳銅合金電阻材料，以及較前述電阻合金材料 更高序數的合金；其厚度較宜在〇.〇5到0.2厘米之間。 圖5爲說明依照本發明的金屬箔晶片電阻器的製造方 法的一實施例的第五步驟的截面圖。參見圖5，一預先圖 形化的抗蝕劑隔離罩6被塗佈於金屬箔電阻層5之上。抗 蝕劑隔離罩6係由非金屬類材料經由塗佈形成，其整體呈 網狀結構，構成網結構的各金屬粒狀體的中心點間的距離 與各金屬箔電阻層5的中心線間的距離相等，以便抗蝕劑 隔離罩在精確對準下覆蓋於金屬箔電阻層5之上。 圖6爲說明依照本發明的金屬箔晶片電阻器的製造方 法的一實施例的第六步驟的截面圖·參見圖6之截面圖， 其中所示者爲圖5之基板1經過一步作業後所得的結果， -7- 1313875 (5) 藉由化學蝕刻的方式使金屬層遭化學藥劑之侵蝕’進一步 將金屬箔電阻線路成型7。 圖7爲說明依照本發明的金屬箔晶片電阻器的製造方 法的一實施例的第七步驟的截面圖。參見圖7之截面圖， 其中所示者爲圖6之基板1經進一步作業後所得的結果， 藉由將原本覆蓋在上導體線路層5之上的抗蝕劑隔離罩6 移除，由於抗蝕劑隔離罩6對於鹼性溶液並無抗侵蝕力， 將圖6之基板1置於鹼性溶液中即可使抗蝕劑隔離罩脫 離。 圖8爲說明依照本發明的金屬箔晶片電阻器的製造方 法的一實施例的第八步驟的截面圖。其中所示者係圖7之 基板1經進一步加工後的結果；從圖7中可看出於基板1 上的溝槽位置上所形成的一連串上導體引線（電極）層 8。在本發明之方法中，這一連串上導體引線（電極）層 8 ’是採用一種非光蝕刻的塗佈法（例如，網版印刷）所 形成。網版印刷是將包括銀，銀合金；金，金合金；銅， 銅合金；鈀，鈀合金；鎳，鎳合金等之導體油墨群組中所 選用的一種導體油墨再經印刷，乾燥及燒結而形成一連串 上導體引線（電極）層8;該導體油墨通常在攝氏150到 9 0 〇度（或更低）的溫度條件下，燒結5到15分鐘的時 間。 圖9爲說明依照本發明的金屬箔晶片電阻器的製造方 法的一實施例的第九步驟的截面圖。這種非光鈾刻的燒蝕 法較宜爲一種運用能量射束，例如鐳射光束，聚焦離子 -8 - (6)1313875 -蓋-RSliLQ迎及'處妻利_ $讀寒土^文說明書修正頁 东I日修(|0正眷類j 民國97年5月15日修正 L_„™„ 束，或聚焦電子束的非光Μ刻能量射束燒齡法；尤其，這 種非光鈾刻能量射束燒蝕法最好是運用鎳鉻鋁合金電阻材 料，锰銅合金電阻材料，鎳銅合金電阻材料一種波長在 236到1 064 n m之間，每平方公分投射光束尺寸之能量 密度在〇 · 0 5到1 0瓦之間；在將覆蓋之金屬箔電阻層5予 以成型而形成折線圖形的金屬箔電阻層系列時，燒蝕的寬 度較宜在10到100微米之間，另在修整這一連串成型金 屬箔電阻層而形成一連串修整和成型金屬箔電阻層5時， 光束直徑較宜在2到100微米之間。 圖1 〇爲說明依照本發明的金屬箔晶片電阻器的製造 方法的一實施例的第十步驟的截面圖。圖10之絕緣基板 1在其它方面均與圖9之基板1相同，但其整個表面形成 了一連串與修整和成型金屬箔電阻層5之一部份對應的較 大面積塗佈成型保護層10以便將該等修整和成型金屬箔 電阻層5的這些部份包封住。這些較大面積塗佈成型保護 層1 〇可用金屬箔晶片電阻器製造技藝中所常用的任何一 種密封材料予以形成，包括環氧樹酯密封劑，氨基甲酸酯 密封劑塑膠，和矽利康密封劑等；在本發明之較佳實施方 法中，與前述一連串上導體引線（電極）層8以及一連串 下導體引線（電極）層3相似’此等較大面積塗佈成型保 護層1 0亦可利用一種非光蝕刻塗佈的印刷方法，但較宜 (7) 1313875 用一種非光蝕刻網版印刷法予以形成；而供形成此種較大 面積塗佈成型保護層1 〇所用的密封劑材料，較宜選用在 進行後續如加印字碼之加工步驟，不易發生裂解作用與具 相容性的材料；尤其，該等較大面積塗佈式成型保護層 1 〇最好是以在基板1上用網版印刷方式印出的環氧密封 劑材料來形成，以便使該等較大面積塗佈方式成型保護層 10各具有20到40微米的厚度。 接著’進行金屬箔電阻單體分離的程序。由圖1〜1 〇 中可看出’基板1的上表面設有橫向縱向間隔句一的溝槽 2，利用其所具備的物理特性，在不需裁切基板1之下， 便能利用物理破裂方式將其分開而形成多數個條狀基板。 這種物理破裂方式，較宜先將基板1固定在一支半徑約2 到8公分的滾筒上，再於這滾筒上對絕緣基板1施加充分 的壓力，以致引起此種物理破裂，然而，其它可將基板 11分成基板條的方式，均可採用。 圖11爲依照本發明的金屬箔電阻器的製造方法所製 成的成品的截面視圖。圖1 1係圖1 〇之條狀基板再經一次 物理破裂成粒狀單體的剖面圖，但在這粒狀單體1 a的一 對相對邊緣中，於各邊緣之上均形成二連串共三道的導體 層，該二連串的三道式導體層包括：（1) 一對成型端子 橋接導體引線層1 1 a和1 1 b ’以供橋接到對應的上導體 引線（電極）層8 ’和對應的下導體引線（電極）層3 ’ (2 )於對應之成型端子橋接導體引線層1 1 a和11 b之 上形成的一對成型端子介質導體層12 a和12 b ;以及 -10- (8) 1313875 (3)於該對成型端子介質導體層12 3和12 ^之上形成 的一對成型端子焊接層1 3 a和1 3 b。該二連串的橋接導 體引線層11 a和11 b的形成方法可爲滾輪塗佈方式，塗 上與上導體引線（電極）層8和對應的下導體引線（電 極）層3相同系列的導體油墨或利用真空濺射法鍍上鎳鉻 系列的合金導體膜。前述那二連串之三道式導體層的各導 體層可用金屬箔晶片電阻器製造技藝習知的任一種方法與 材料形成。 同樣地’雖然成型端子介質導體層12 a和12 b，以 及成型端子焊接層13 a和13 b可用製造分立金屬箔晶片 電阻器時用以形成該等成型端子導體層和成型端子焊接層 的任何一種材料來形成’但就本發明之較佳實施方法而 g，較宜以銅或銅合金導體材料來形成成型端子介質導體 層1 2 a和1 2 b，另以錫合金焊接材料來形成成型焊接層 13 a和13 b。使用鎳或鎳合金材料來形成成型端子導體 層1 2 a和1 2 b，和使用錫合金焊接材料來形成成型端子 焊接層1 3 a和1 3 b ，通常會讓分立金屬箔電阻晶片在混 合電路微電子製品中具有最佳的耐触性和黏結性。同樣 地’雖然成型端子介質導體層12 a和12 b，以及成型端 子焊接層1 3 a和1 3 b可用製造分立金屬箔晶片電阻器時 能形成該等成型端子介質導體層和成型端子焊接層的任何 一種方法來形成’但較宜用電鍍法形成，以便能以最具效 率的方式讓成型端子介質導體層12 a和12 b，以及成型 端子焊接層13 a和13 b在混合電路微電子製品中具有最 1313875 (9) 佳的耐蝕性與黏結性。 雖然圖11中未予具體顯示出來，但基板1 a隨後通 常會被分開，以便從這條狀基板1 a形成一連串分立基板 晶片，且其上亦形成一連串如圖1 1所示的分立金屬箔電 阻器，因而形成一連串分立金屬箔電阻晶片。如同一基板 1被分成條狀基板1 a ，該等分立基板晶片也較宜採用類 似的方法由絕緣基板條1 a予以分成，尤其，不需裁切基 板條1 a ，較宜沿著其餘的橫向溝槽改用物理破裂方式將 這條狀基板1 a分成基板晶片。 雖然圖U中未予具體顯示出來，但條狀基板1 a可 被分成若干分立金屬箔電阻晶片，該等金屬箔電阻晶片又 包括若干分立的絕緣基板晶片，且其上也形成有若干分立 金屬箔晶片電阻器，此等金屬箔晶片電阻器是在絕緣基板 晶片1 a上形成成型端子介質導體層12 a和12b ，以及 成型端子焊接層13 a和13 b之前或之後所形成的。在本 發明之較佳實施方法中，較宜在利用電鍍法形成成型端子 介質導體層12 a和12 b以及成型端子焊接層13 a和 13 b之前，將絕緣條狀基板1 a分成一連串其上已形成 有一連串金屬箔晶片電阻器的絕緣基板晶片。 以上所舉實施例僅用以說明本發明而已，非用以卩艮制 本發明之範圍。舉凡嫻熟本技藝者不違本發明精神&彳足| 的種種變化和修改，倶屬本發明申請專利之範圍。 【圖式簡單說明】 -12- (10) 1313875 本發明的技術內容及特性將於下參照所附圖式，藉由 較佳實施例的方式作詳細的說明。 圖ί爲說明本發明的金屬箔晶片電阻器製造方法的一 實施例中的第一步驟的截面圖； 圖2爲說明本發明的金屬箔晶片電阻器製造方法的一 實施例中的第二步驟的截面圖； 圖3爲說明本發明的金屬箔晶片電阻器製造方法的一 實施例中的第三步驟的截面圖； 圖4爲說明本發明的金屬箔晶片電阻器製造方法的一 實施例中的第四步驟的截面圖； 圖5爲說明本發明的金屬箔晶片電阻器製造方法的一 實施例中的第五步驟的截面圖； 圖6爲說明本發明的金屬箔晶片電阻器製造方法的一 實施例中的第六步驟的截面圖； 圖7爲說明本發明的金屬箔晶片電阻器製造方法的一 實施例中的第七步驟的截面圖； 圖8爲說明本發明的金屬箔晶片電阻器製造方法的一實施 例中的第八步驟的截面圖； 圖9爲說明本發明的金屬箔晶片電阻器製造方法的一實施 例中的第九步驟的截面圖； 圖1 〇爲說明本發明的金屬箔晶片電阻器製造方法的 一實施例中的第十步驟的截面圖；及 圖1 1爲依照本發明的金屬箔晶片電阻器的製造方法 所製成的成品的截面視圖。 -13- (11) (11)1313875 主要元件對照表 1,1a 絕緣基板 2 溝槽 _ 3 下導體引線層 _ 4 接著劑 5 金屬箔電阻層 6 抗蝕劑隔離罩 φ 7 蝕刻成型線路 8 上導體引線層 9 鐳射切割線 10 保護層 1 la, 1 lb成型端子橋接導體層 12a, 12b成型端子介質導體層 13a, 13b成型端子焊接層 -14 -1313875 (1) BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a metal foil chip resistor used in a microelectronic device, particularly relating to a metal mold which is manufactured with high precision by a streamlined procedure. Chip resistor method. [Prior Art] Metal foil <sheet> resistors are commonly used in microelectronic device fabrication techniques as passive circuit components and/or carrier circuit components in circuits. Metal foil resistors can be used in microelectronics. When used in a hybrid circuit microelectronic article, a metal foil resistive material coating layer adhered to an insulating substrate such as a glass insulating substrate or a ceramic insulating substrate is usually photolithographically formed by a method of the prior art. Metal foil resistors are then separated from portions of the insulating substrate to form discrete metal foil wafer resistors. In a method of manufacturing a conventional metal foil chip resistor, the method comprises the steps of: (1) providing an insulating substrate, (2) bonding a specific metal foil to a surface of the substrate, and (3) photolithographically etching the light. The resist film forms a resistive line, (4) uses laser ablation or other mechanical processing methods to change the length or area of the resistive line to achieve a predetermined resistance 値, (5) separate individual resistors, and (6) resistive layers Soldering with wire, (7) covering the sealant, (8) housing package, (9) test screening, (1 〇) package shipping. In the above process, multiple graphic coating procedures are involved, which require complicated calibration and processing, and the separate resistors are separated by using the -4-I313875 (2) cutting method such as a diamond blade, and the wires are The combination of the resistive layer in a soldered manner and the need for an injection molded package also increases the time and cost of manufacturing. In the current manufacturing method of the conventional metal foil chip resistor, the common size is 6.3 meters long and 3.2 mm wide, and the right side is further miniaturized, such as a 2.0 mm long '1.2 mm wide metal foil. Chip resistors' are not possible. SUMMARY OF THE INVENTION In view of the above problems of the prior art, the present invention provides a method of manufacturing a metal foil wafer resistor, which can produce a metal foil resistor having high precision by a compact process. It is an object of the present invention to provide a method of fabricating a metal foil wafer resistor that can be fabricated into a series of discrete metal foil wafer resistors. Another object of the present invention is to provide a method of fabricating a metal foil wafer resistor that is free from the use of various photolithographic methods, materials and devices. Another object of the present invention is to provide a method of manufacturing a metal foil chip resistor which eliminates the need for wire bonding and injection molding equipment. Another object of the present invention is to provide a method of fabricating a metal foil wafer resistor which can produce a metal foil wafer resistor which is easy to separate. Another object of the present invention is to provide a method of manufacturing a metal box chip resistor which can be miniaturized to a metal foil chip resistor of _ 6 mm long and 0.3 mm wide. -5 - 1313875 (3) [Embodiment] Referring to the drawings, a drawing of a metal foil chip resistor is made of an insulating material according to a first step of an embodiment of the present invention. board. The plurality of strips 2 on the substrate 1 are not limited to, for example, a laterally single upward direction and another set of grooved portions which are equidistant from each other in a checkerboard shape. 2 is a view showing a result of a second step of the second step of the second embodiment of the present invention, after further processing, the trench 2 (the V conductor lead (electrode) layer 3 shown in the figure. The conductor lead (electrode) layer 3, ( For example, screen printing) is selected from the group of conductor inks of gold, gold, gold alloy, copper 'copper, etc., which are selected to be dried and sintered to form a series of inks, usually at 150J Celsius, and sintered for 5 to 15 minutes. 3 is a cross-sectional view showing the manufacturing method of the metal foil chip resistor according to a preferred embodiment of the present invention. Referring to FIG. 1, the substrate 1 is used as a metal foil chip resistor. The process bases are parallel and equidistant from each other, and the trenches extend in the direction of the trenches, and the longitudinal and parallel trenches perpendicular to the direction of the substrate, the surface of the substrate 1 shown in the method of manufacturing the metal foil resistor. The substrate shown in Figure 1 is shown in Figure 2 in a series of reversed positions on the substrate 1. In the method of the present invention, the series is coated by a non-photoetching method. to make. Screen printing is a conductor ink that will include silver, silver alloy, palladium, palladium alloy, nickel, nickel alloy, and then printed, lower conductor lead (electrode) layer 3; the guide! 1 900 degrees (or lower) ) The temperature condition is between F. A method of manufacturing a metal foil chip resistor according to the third step of an embodiment of the method of the invention, which is formed by a non-photolithographic coating method (for example, screen printing). Screen printing is the uniform application of an adhesive onto a substrate. Figure 4 is a cross-sectional view showing a fourth step of an embodiment of a method of fabricating a metal foil wafer resistor in accordance with the present invention. 4 is a cross-sectional view of the substrate 1 of FIG. 3 after further processing with the metal foil 5; FIG. 4 is a cross-sectional view of the substrate 1 of FIG. 3, but on the surface thereof Laminating a metal foil resistor layer 5; the metal foil resistor layer 5 is pre-formed into a checkerboard-shaped metal foil mesh conforming to the checkerboard centerline of the insulating substrate for precise alignment on the insulating substrate, the metal foil resistor The layer 5 may be formed of any one of the resistive materials known in the art of metal foil resistor manufacturing, for example, a nickel-chromium alloy resistive material, a nickel-chromium-aluminum alloy resistive material, a manganese-copper alloy resistive material, a nickel-copper alloy resistive material, and a resistive alloy as described above. A higher order number of alloys; the thickness of the alloy is preferably between 5 and 0.2 cm. Figure 5 is a cross-sectional view showing a fifth step of an embodiment of a method of fabricating a metal foil wafer resistor in accordance with the present invention. Referring to Figure 5, a pre-patterned resist spacer 6 is applied over the metal foil resistive layer 5. The resist spacer 6 is formed by coating a non-metal material, and has a mesh structure as a whole, and the distance between the center points of the metal granular bodies constituting the mesh structure and the center line of each metal foil resistance layer 5 The distances are equal so that the resist spacer covers the metal foil resistive layer 5 with precise alignment. Figure 6 is a cross-sectional view showing a sixth step of an embodiment of a method of manufacturing a metal foil wafer resistor in accordance with the present invention. Referring to Figure 6, there is shown a cross-sectional view of the substrate 1 of Figure 5 after a step operation. As a result, -7- 1313875 (5) The metal layer is chemically etched by chemical etching to further shape the metal foil resistance line. Figure 7 is a cross-sectional view showing a seventh step of an embodiment of a method of fabricating a metal foil wafer resistor in accordance with the present invention. Referring to the cross-sectional view of FIG. 7, the result obtained by further working the substrate 1 of FIG. 6 is shown by removing the resist spacer 6 originally covering the upper conductor wiring layer 5 due to the resistance. The etchant spacer 6 has no erosive resistance to the alkaline solution, and the substrate 1 of FIG. 6 is placed in an alkaline solution to detach the resist spacer. Figure 8 is a cross-sectional view showing an eighth step of an embodiment of a method of fabricating a metal foil wafer resistor in accordance with the present invention. The one shown therein is the result of further processing of the substrate 1 of Fig. 7; a series of upper conductor lead (electrode) layers 8 formed at the groove locations on the substrate 1 can be seen from Fig. 7. In the method of the present invention, the series of upper conductor lead (electrode) layers 8' are formed by a non-photolithographic coating method (e.g., screen printing). Screen printing is a kind of conductor ink selected from the group consisting of silver, silver alloy, gold, gold alloy, copper, copper alloy, palladium, palladium alloy, nickel, nickel alloy, etc., which is selected for printing, drying and sintering. A series of upper conductor lead (electrode) layers 8 are formed; the conductor ink is typically sintered for 5 to 15 minutes at a temperature of 150 to 90 degrees Celsius (or lower). Figure 9 is a cross-sectional view showing a ninth step of an embodiment of a method of fabricating a metal foil wafer resistor in accordance with the present invention. This non-photo uranium engraving method is more suitable for the use of an energy beam, such as a laser beam, focusing ion -8 - (6) 1313875 - cover - RSliLQ greets 'the wife's profit _ $ read cold soil ^ manual Amendment page East I daily repair (|0 眷 眷 j Republic of China May 15, 1997 revised L_„TM „ beam, or focused electron beam non-light engraved energy beam aging method; in particular, this non-photo uranium The engraved energy beam ablation method is preferably a nickel-chromium-aluminum alloy resistor material, a manganese-copper alloy resistor material, and a nickel-copper alloy resistor material having a wavelength between 236 and 1 064 nm, and the energy density per square centimeter of the projected beam size is 〇· 0 5 to 10 watts; in the metal foil resistor layer series in which the covered metal foil resistor layer 5 is formed to form a polygonal line pattern, the ablation width is preferably between 10 and 100 micrometers, and When trimming the series of formed metal foil resistor layers to form a series of trimmed and shaped metal foil resistive layers 5, the beam diameter is preferably between 2 and 100 microns. Figure 1 is a diagram illustrating a method of fabricating a metal foil wafer resistor in accordance with the present invention. A cross-sectional view of a tenth step of an embodiment. Figure 10 The edge substrate 1 is otherwise identical to the substrate 1 of FIG. 9, but the entire surface thereof forms a series of large-area coating-forming protective layers 10 corresponding to one portion of the trimmed and molded metal foil resistive layer 5 to facilitate such These portions of the trimmed and formed metal foil resistive layer 5 are encapsulated. These larger area coated forming protective layers 1 can be formed using any of the sealing materials commonly used in the art of metal foil chip resistor manufacturing, including epoxy trees. An ester sealant, a urethane sealant plastic, and a kelonic sealant, etc.; in a preferred embodiment of the invention, a series of upper conductor lead (electrode) layers 8 and a series of lower conductor lead (electrode) layers 3 Similarly, such a larger area coating forming protective layer 10 can also be formed by a non-photolithographic coating printing method, but preferably (7) 1313875 is formed by a non-photolithographic screen printing method; The sealant material used for coating a large area of the protective layer 1 is preferably used for subsequent processing steps such as printing, which is less prone to cracking and compatibility. Materials; in particular, the larger-area coated molding protective layer 1 is preferably formed by an epoxy sealant material printed on the substrate 1 by screen printing to coat the larger areas. The method of forming the protective layer 10 each has a thickness of 20 to 40 μm. Next, the procedure for separating the metal foil resistors is carried out. It can be seen from Fig. 1 to 1 that the upper surface of the substrate 1 is provided with a horizontally longitudinally spaced sentence. The trench 2, by virtue of its physical properties, can be separated by physical rupture to form a plurality of strip substrates without cutting the substrate 1. This physical rupture method preferably takes the substrate first. 1 is fixed on a roller having a radius of about 2 to 8 cm, and then applying sufficient pressure to the insulating substrate 1 on the roller to cause such physical cracking. However, other ways of dividing the substrate 11 into the substrate strip are Can be used. Figure 11 is a cross-sectional view showing a finished product produced by a method of manufacturing a metal foil resistor in accordance with the present invention. Figure 1 is a cross-sectional view of a strip substrate of Fig. 1 which is physically ruptured into a granular monomer, but in a pair of opposite edges of the granular monomer 1 a, two layers are formed on each edge. A series of three conductor layers, the two series of three-way conductor layers comprising: (1) a pair of shaped terminal bridge conductor lead layers 1 1 a and 1 1 b ' for bridging to corresponding upper conductor leads (electrodes a layer 8' and a corresponding lower conductor lead (electrode) layer 3' (2) formed on a pair of shaped terminal dielectric conductor layers 12a and 12b formed over the corresponding shaped terminal bridge conductor lead layers 1 1 a and 11 b And -10-(8) 1313875 (3) a pair of formed terminal solder layers 1 3 a and 1 3 b formed over the pair of formed terminal dielectric conductor layers 12 3 and 12 ^. The two series of bridging conductor lead layers 11a and 11b may be formed by a roller coating method, and coated with the same series of conductors as the upper conductor lead (electrode) layer 8 and the corresponding lower conductor lead (electrode) layer 3. The ink or the alloy conductor film of the nickel-chromium series is plated by vacuum sputtering. Each of the plurality of conductor layers of the series of three-way conductor layers can be formed by any of the methods and materials known in the art of metal foil chip resistor fabrication. Similarly, although the shaped terminal dielectric conductor layers 12a and 12b, and the shaped terminal soldering layers 13a and 13b can be used to form the discrete terminal metal foil chip resistors, any of the formed terminal conductor layers and the molded terminal soldering layers can be formed. A material is formed to form 'but in the preferred embodiment of the invention, g is preferably formed from a copper or copper alloy conductor material to form the terminal dielectric conductor layers 1 2 a and 1 2 b, and a tin alloy solder material is used to form the molding. Welding layers 13a and 13b. The use of a nickel or nickel alloy material to form the formed terminal conductor layers 1 2 a and 1 2 b, and the use of a tin alloy solder material to form the shaped terminal solder layers 1 3 a and 1 3 b typically results in a discrete metal foil resistor wafer being mixed The best resistance to contact and adhesion in circuit microelectronics. Similarly, although the molded terminal dielectric conductor layers 12a and 12b, and the molded terminal solder layers 1 3 a and 1 3 b can be used to form the discrete metal foil wafer resistors, the molded terminal dielectric conductor layers and the formed terminal solder layers can be formed. Any of the methods to form 'but is preferably formed by electroplating so that the terminal dielectric conductor layers 12a and 12b can be formed in the most efficient manner, and the terminal soldering layers 13a and 13b are formed in the hybrid circuit microelectronics. The product has the best corrosion resistance and adhesion of 1313875 (9). Although not specifically shown in FIG. 11, the substrate 1a is then generally separated to form a series of discrete substrate wafers from the strip substrate 1a, and a series of discrete metal foils as shown in FIG. The resistors thus form a series of discrete metal foil resistor wafers. If the same substrate 1 is divided into strip substrates 1 a , the discrete substrate wafers are also preferably divided into the insulating substrate strips 1 a by a similar method. In particular, it is not necessary to cut the substrate strips 1 a , preferably along the rest. The lateral groove is changed into a substrate wafer by physically breaking the strip substrate 1 a. Although not specifically shown in FIG. 7, the strip substrate 1a can be divided into discrete metal foil resistor wafers, which in turn comprise a plurality of discrete insulating substrate wafers, and a plurality of discrete metals are also formed thereon. A foil chip resistor formed by forming the terminal dielectric conductor layers 12a and 12b on the insulating substrate wafer 1a and before or after forming the terminal soldering layers 13a and 13b. In a preferred embodiment of the present invention, it is preferred to divide the insulating strip substrate 1 a into a series before forming the terminal dielectric conductor layers 12 a and 12 b and the terminal soldering layers 13 a and 13 b by electroplating. An insulating substrate wafer having a series of metal foil wafer resistors has been formed. The above embodiments are merely illustrative of the invention and are not intended to limit the scope of the invention. Any variation or modification of the present invention without departing from the spirit and scope of the present invention is within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The technical contents and characteristics of the present invention will be described in detail by way of preferred embodiments with reference to the accompanying drawings. Figure 1 is a cross-sectional view showing a first step in an embodiment of a method of manufacturing a metal foil chip resistor of the present invention; Figure 2 is a second step in an embodiment of a method of manufacturing a metal foil chip resistor of the present invention; 3 is a cross-sectional view illustrating a third step in an embodiment of a method of fabricating a metal foil wafer resistor of the present invention; and FIG. 4 is an embodiment illustrating a method of fabricating a metal foil wafer resistor of the present invention. FIG. 5 is a cross-sectional view showing a fifth step in an embodiment of the method for fabricating a metal foil chip resistor of the present invention; FIG. 6 is a view illustrating a method of manufacturing a metal foil chip resistor of the present invention; A cross-sectional view of a sixth step in an embodiment; FIG. 7 is a cross-sectional view showing a seventh step in an embodiment of the method for fabricating a metal foil chip resistor of the present invention; and FIG. 8 is a view showing a metal foil chip resistor of the present invention. FIG. 9 is a cross-sectional view showing a ninth step in an embodiment of a method of manufacturing a metal foil wafer resistor of the present invention; 1 is a cross-sectional view showing a tenth step in an embodiment of a method for manufacturing a metal foil chip resistor of the present invention; and FIG. 11 is a finished product produced by a method of manufacturing a metal foil chip resistor according to the present invention; Cross-sectional view. -13- (11) (11) 1313875 Main components comparison table 1, 1a Insulating substrate 2 Groove _ 3 Lower conductor wiring layer _ 4 Adhesive 5 Metal foil resistance layer 6 Resist isolation mask φ 7 Etching molding line 8 Conductor lead layer 9 laser cutting line 10 protective layer 1 la, 1 lb shaped terminal bridging conductor layer 12a, 12b shaped terminal dielectric conductor layer 13a, 13b shaped terminal soldering layer-14 -