1313510 九、發明說明： 【發明所屬之技術領域】 本發明係有關於用於非接觸式積體電路板的—積積體 電路晶片電源供應電路，尤指可降低整平電容之電容值， 且縮小積體電路晶片的一種積體電路晶片電源供應電路。 【先前技術】 非接觸式積體電路板的應用範圍相當廣泛。這種電路 板整合具有記憶功能與通訊功能的積體電路晶片，將其製 作在一片或一層基板材料上，並能與讀寫裝置(reader/writer) 交換無線資料。然而，除了一般的電子晶片卡（IC cards)和 電子標藏外(IC tags)，此處所稱的積體電路板尚包括通行紙 鈔、保安系統的與其它類似的整合式電子晶片。 一般情況下，積體電路板的積體電路晶片接收來自讀 寫裝置的無線電載波，並對此載波整流，以產生操作時的 電源供應電壓（其例子請參考日本專利文獻Japanese1313510 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit circuit chip power supply circuit for a non-contact integrated circuit board, in particular, a capacitance value of a leveling capacitor can be reduced, and An integrated circuit chip power supply circuit for reducing an integrated circuit chip. [Prior Art] The application range of the non-contact integrated circuit board is quite wide. The board integrates an integrated circuit chip with memory and communication functions, which is fabricated on one or a layer of substrate material and can exchange wireless data with a reader/writer. However, in addition to general IC cards and IC tags, the integrated circuit board referred to herein includes integrated electronic chips for the passage of paper money, security systems and the like. In general, the integrated circuit chip of the integrated circuit board receives the radio carrier from the reading and writing device, and rectifies the carrier to generate the power supply voltage during operation (for example, please refer to Japanese Patent Literature Japanese)
Patent Laid-open No. 2002-99886 )。 利用此習知技術時常見的問題是，若收來自讀寫裝置 的無線電載波之頻率較低，整平電容須有較大的電容值， 因此無法將整平電容設於積體電路晶片上。例如，若無線 電載波頻率為13.56百萬赫茲（MHz)，則整平電容的電容值 須為100微微法拉(pF)或更大，但物理上不可能將具有如 此大電容值的電容製作於邊長約僅05毫米（mm)的積體電 路晶片上。因此’針對上述習知技術的問題，本發明之一 1313510 目的為5提供用於非接觸式積體電路板的一種積體電路晶 片電源供應電路，其具有較小的整平電容之電容值，且可 容易地於製作在‘積體電路晶片上，即使來自讀寫裝置的無 線電載波之頻率較低。 【發明内容】 為達成上述目的’本發明之一種積體電路晶片電源供 應電路包括：一天線、對此天線的輸出電壓整流的二極體、 設於該二極體的輸出端之一串聯電晶體，與連設於串聯電 晶體的基極之一整平電容；連同一具有記憶功能與通訊功 能的主體部，該整平電容係以積體整合方式設於積體電路 晶片上。 上述整平電容之電容值可僅為數個微微法拉的數量 級，且可利用電路中的雜散電容實現之。 再者，可設一辅助電晶體作為串聯電晶體之一附屬物，係 可供應串聯電晶體的基極電流，該輔助電晶體可具限制電 壓之一限壓功能。 更再者，二極體之輸出端係連設於對一外接天線的輸 出電壓進行整流之另一二極體之輸出端。 於上述本發明之一種積體電路晶片電源供應電路中， 連設於此串聯電晶體之基極的整平電容電容值僅須為不使 用串聯電晶體時的1//5倍，其中石為串聯電晶體的增益係 數。若串聯電晶體的電流增益值為万，則整平電容的外顯 電容值（apparent)將乘上。也就是說，串聯電晶體增加了 1313510 整平電容的等效電容值(equivalent capacitance)，因此可充 分達成減小擾動的效果；當來自讀寫裝置的無線電載波之 頻率為13.56百萬赫茲，習用技術中要求的100微微法拉 或更大的整平電容之電容值可降至數個微微法拉的數量 級，使整平電容可輕易地以積體整方式製作於積體電路晶 片上。再者，如此低的整平電容之電容值可藉積體電路晶 片中電路系統的雜散來達成。 利用作為串聯電晶體的附屬物之一輔助電晶體，以供 應串聯電晶體的基極電流，且可增加整體操作的穩定性； 該輔助電晶體可具限制電壓之一限壓功能。經由限制相對 於一固定電壓的基極電壓，輔助電晶體亦可具有限壓的功 能。 若利用另一二極體對外接天線的輸出電壓進行整流， 亦可利用來自讀寫裝置的無線電載波作為操作電源供應電 壓，故可增加與讀寫裝置之通訊操作的許可距離。此外接 天線乃整合入基板材料中，且連設於積體電路晶片所設之 一電接頭。 【實施方式】 以下用圖式說明本發明。 本發明之一種用於非接觸式積體電路板的積體電路晶 片電源供應電路包括天線A、二極體D、串聯電晶體T 與三個整平電容C1、C2、C3 (第一圖），且以積體整 合方式，連同具有記憶功能與通訊功能的主體部1 2設於 !31351〇 積體電路晶片10上。天線八係 聯共振；天線Α未接地側的於電谷C，以形成並 電晶體丁之隹朽 Γ 糸經二極體D連設於串聯 —。二極體D的輪出端經端點TA連設於另 極體Da之輸出端，二極體 、Patent Laid-open No. 2002-99886 ). A common problem with this prior art technique is that if the frequency of the radio carrier from the reader/writer device is low, the leveling capacitor must have a large capacitance value, so the leveling capacitor cannot be placed on the integrated circuit chip. For example, if the radio carrier frequency is 13.56 megahertz (MHz), the capacitance of the leveling capacitor must be 100 picofarads (pF) or more, but it is physically impossible to make a capacitor with such a large capacitance. It is on a monolithic circuit wafer of only about 05 mm (mm). Therefore, in view of the above problems of the prior art, one of the 1313510 objects of the present invention provides an integrated circuit chip power supply circuit for a non-contact integrated circuit board having a capacitance value of a small leveling capacitor. And it can be easily fabricated on an 'integrated circuit chip, even if the frequency of the radio carrier from the read/write device is low. SUMMARY OF THE INVENTION In order to achieve the above object, an integrated circuit chip power supply circuit of the present invention includes: an antenna, a diode for rectifying an output voltage of the antenna, and a series connected to an output end of the diode. The crystal is connected to a body of a series connected to the base of the series transistor; and is connected to the main body portion having a memory function and a communication function, and the leveling capacitor is integrated on the integrated circuit chip in an integrated manner. The capacitance of the above-mentioned leveling capacitor can be only on the order of several picofarads and can be realized by stray capacitance in the circuit. Furthermore, an auxiliary transistor can be provided as an appendage of the series transistor, which can supply the base current of the series transistor, and the auxiliary transistor can have a voltage limiting function of the limiting voltage. Furthermore, the output of the diode is connected to the output of the other diode that rectifies the output voltage of an external antenna. In the above-mentioned integrated circuit chip power supply circuit of the present invention, the leveling capacitance value of the base connected to the series transistor must be only 1//5 times that of the case where the series transistor is not used, wherein The gain factor of the series transistor. If the current gain value of the series transistor is 10,000, the external capacitance of the leveling capacitor will be multiplied. That is to say, the series transistor increases the equivalent capacitance of the 1313510 leveling capacitor, so that the effect of reducing the disturbance can be fully achieved; when the frequency of the radio carrier from the reader/writer is 13.56 megahertz, the conventional use The capacitance value of the 100 picofarad or larger leveling capacitor required in the technology can be reduced to the order of several picofarads, so that the leveling capacitor can be easily fabricated on the integrated circuit wafer in an integrated manner. Moreover, the capacitance of such a low leveling capacitor can be achieved by the spurs of the circuitry in the integrated circuit chip. The auxiliary transistor is supplied as one of the appendages of the series transistor to supply the base current of the series transistor, and the stability of the overall operation can be increased; the auxiliary transistor can have a voltage limiting function of the limiting voltage. The auxiliary transistor can also have a voltage limiting function by limiting the base voltage relative to a fixed voltage. If the output voltage of the external antenna is rectified by the other diode, the radio carrier from the reader/writer device can be used as the operating power supply voltage, so that the permission distance for the communication operation with the read/write device can be increased. In addition, the antenna is integrated into the substrate material and connected to an electrical connector provided in the integrated circuit chip. [Embodiment] Hereinafter, the present invention will be described by way of drawings. An integrated circuit chip power supply circuit for a non-contact integrated circuit board of the present invention comprises an antenna A, a diode D, a series transistor T and three leveling capacitors C1, C2, C3 (first figure) And in the integrated manner, the main body portion 12 having the memory function and the communication function is provided on the !31351 plenum circuit wafer 10. The antenna is occluded in resonance; the antenna Α is not grounded on the electric valley C to form a parallel crystal 丁 糸 二 through the diode D is connected in series. The turn-out end of the diode D is connected to the output end of the other body Da via the terminal TA, the diode,
3未接^^ 一 a係連設於外接天線A #於虫1 —端’且與整平電容C 1相連。電阻R 1連 〇又；串聯電晶體丁的集極與基極之門敕巫带 於串聯電晶體丁的基極。串聯電曰體丁 =琶容C 2連設 極，係連設於整平電容c 3二曰體T的輸出端’亦即射 於主體部i 2。 聯電晶體丁的射極連設 -極體D與Da的輸入端經由耦合 且聯合連設於主體邱Ί 9 电丨尺R相連通， ^卩12。外接天線人3與電容^造 、，以形成並聯共振，外接天綠A '、 β連設於天線A之接地端。的接地端係經端點Τ3 is not connected to ^^ a is connected to the external antenna A #于虫1 - terminal ' and connected to the leveling capacitor C 1 . The resistor R 1 is connected again; the collector of the series transistor and the threshold of the base are connected to the base of the tandem transistor. The series electric 丁 body = 琶 C 2 connected pole is connected to the output end of the leveling capacitor c 3 曰 body T, that is, the main body i 2 . The emitter connection of the electro-optic crystal D-connected to the input end of the polar body D and Da via the coupling and the connection of the main body of the electric circuit R, ^卩12. The external antenna 3 and the capacitor are formed to form a parallel resonance, and the external sky green A ', β is connected to the ground end of the antenna A. The ground terminal is through the endpoint
垂當來自讀寫裝置的無線電载波（未顯示於圖示中）抵 達天線A與外接天線Aa或並中 }L h之輸出電厂歸經二極體D ^^線=外接天線 容後經整平電 的雪Mu τ ㈣電曰曰體Τ的等效整平電容 的電奋值為整平電容C 2電容值之万倍（万為串聯電晶體 增益係數），且與整平電容C 3並聯。因此，甚至 寫裝置的無線電載波之頻率為13 56百萬赫兹， :平2的電容值至多只須為數個微微法拉的數量 =Π整平電容“、。2、。3皆易於以積體電路 日日片1 0中的電路系統之雜散電容來 路晶片10上進行製作電容元件的特殊㈣:：= 1313510 可於串聯電晶體τ的輸出端產生充份穩定的操作電源供應 電壓V，以供應主體部1 2的電源。 如第一、第二圖所示，包括串聯電晶體Τ之電路1 1 中亦可加設一輔助電晶體Τ 1。輔助電晶體Τ 1的基極和 集極分別藉由電阻R 1、R 2連設於串聯電晶體Τ之集 極’且輔助電晶體Τ 1的基極係經由基納二極體Ζ接地。 輔助電晶體Τ 1的射極係連設於串聯電晶體Τ的基極。再 者，串聯電晶體Τ的集極與射極間連設有一保護二極體D 1 ° 輔助電晶體Τ1措基納二極體Ζ提供電壓之限壓功 能，更供應串聯電晶體Τ之基極電流，且因此能增加串聯 電晶體Τ之有效電流增益，並使操作更穩定。 如上所闡釋，外接天線A a與連設於端點Τ A、Τ Β 之電容C a能有效地擴展與讀寫裝置間的通訊距離。附加 外接天線A a與電容C a有其必要。 如上所述，本發明完全符合專利三要件：新穎性、進 步性和產業上的利用性。本發明在上文中已以較佳實施例 揭露，然熟習本項技術者應理解的是，該實施例僅用於描 繪本發明，而不應解讀為限制本發明之範圍。應注意的是， 舉凡與該實施例等效之變化與置換，均應設為涵蓋於本發 明之範疇内。因此，本發明之保護範圍當以下文之申請專 利範圍所界定者為準。 【圖式簡單說明】 1313510 第一圖係本發明之整體系統示意圖。 第二圖為一系統示意圖，係以另一種組態表示本發明之主 要部份。 【主要元件符號說明】 A 天線 A a 外接天線 D 二極體 D1 保護二極體 D a 另一二極體 Z 基納二極體 T 串聯電晶體 R 1 電阻 R 2 電阻 R 耦合電阻 R 耦合電阻 C 電容 C a 電容 C1 整平電容 C 2 整平電容 C 3 整平電容 V 操作電源供應電壓 T1 輔助電晶體 T A 端點 10 1313510 Τ Β 端點 11 包括串聯電晶體τ之電路 12 主體部 10 積體電路晶片The radio carrier (not shown) from the reader/writer device arrives at the antenna A and the external antenna Aa or in the middle of the output. The output power plant is returned to the diode D ^ ^ line = external antenna capacity The electric motor of the flat electric Mu τ (four) electric equivalent body of the equivalent leveling capacitor is 10,000 times the capacitance of the leveling capacitor C 2 (10,000 is the series transistor gain coefficient), and the leveling capacitor C 3 in parallel. Therefore, even the frequency of the radio carrier of the writing device is 13 56 megahertz, and the capacitance value of the flat 2 must be at most the number of picofarads = Π flattening capacitors ", . 2, . 3 are easy to be integrated circuits The stray capacitance of the circuit system in the solar chip 10 is made on the wafer 10 (4)::= 1313510 can generate a sufficiently stable operating power supply voltage V at the output of the series transistor τ, The power supply of the main body portion 12 is supplied. As shown in the first and second figures, an auxiliary transistor Τ 1 may be added to the circuit 1 1 including the series transistor 。. The base and collector of the auxiliary transistor Τ 1 The bases of the auxiliary transistor Τ 1 are connected to the collector of the series transistor 藉 1 by resistors R 1 and R 2 , respectively, and the base of the auxiliary transistor Ζ 1 is grounded via the kinetic diode 。 1 . The base of the series transistor 。. Furthermore, a series of diodes D 1 is connected between the collector and the emitter of the series transistor, and the auxiliary transistor Τ1 is provided with a voltage limiting function. , the base current of the series transistor 供应 is supplied, and thus the series transistor can be increased The effective current gain of Τ makes the operation more stable. As explained above, the external antenna A a and the capacitor C a connected to the terminals Τ A, Β 能 can effectively expand the communication distance between the read/write device. The antenna A a and the capacitor C a are necessary. As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial applicability. The present invention has been disclosed in the above preferred embodiments, but is familiar with It is to be understood by those skilled in the art that the present invention is not intended to limit the scope of the present invention. It should be noted that all variations and permutations equivalent to the embodiment should be The scope of the present invention is intended to be included in the scope of the present invention. Therefore, the scope of the present invention is defined by the scope of the following claims. [FIG. 131310] The first figure is a schematic diagram of the overall system of the present invention. For a system diagram, the main part of the invention is shown in another configuration. [Main component symbol description] A Antenna A a External antenna D Dipole D1 Protection diode D a Another diode Z base Diode T Series transistor R 1 Resistor R 2 Resistor R Coupling resistor R Coupling resistor C Capacitance C a Capacitor C1 Leveling capacitor C 2 Leveling capacitor C 3 Leveling capacitor V Operating power supply voltage T1 Auxiliary transistor TA end point 10 1313510 Τ Β End point 11 Circuit including series transistor τ 12 Body part 10 Integrated circuit chip