1312929 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體晶片設計，且特 片與封裝基板佈局的整合式偵錯方法。、 關於 【光鈿技術】 在傳統的科方法巾，W的設計 =的地方進行的。在設計階段未被注意的問 敢ί組裝程序中，當所有的零件集合以進行組裝; 矛現。這些問題包含電麼供應的差異、邏輯層面及= 相容。如果錯誤未在早期階段被發現則產: 由於晶片佈局與封裝基板佈局不 段常會出現錯誤及不符設計規則的情形 ==局與封裝基板佈局-直是個難二 在傳、“片製造程序上’封録板佈局設計— 設計者難以觸及的領域。傳統上乃是利用^表 =eadSheet)比對以檢查晶片與封裝基板佈局之間=連 是伟而:=極為容易出錯’因為大部分的試算表内容 以檢：ΐ:ί半導體晶片設計上需要改良的方法及系統 設ί規二;:裝基板細體是否有發咖 【發明内容】 0503-Α31608TWF/J〇seph 4 1312929 有鑑於此，本發明之目的在提供晶片與封裝基板佈 局的整合式偵錯方法及系統。 基於上述目的，本發明提供晶片佈局資料集合與封 裝基板佈局資料集合的整合式 <貞錯方法及系統。在本發 明一實施例中，封裝基板佈局資料集合從第一格式被轉 換成第二格式，其中晶片佈局資料集合以該第二格式呈 現。合併屬第二格式之上述晶片佈局資料集合及上述封 裝基板佈局資料集合，成為一合併資料集合。接著再檢 查上述合併資料集合有無錯誤或違反設計規則。 本發明的建構及操作方法，額外的目的及優點，從 以下特定實施例之說明並其附圖可獲得最佳的了解。 【實施方式】 弟1圖揭不本發明一貫施例之糸統的處理流程 100，而該系統以整合方式檢查晶片與封裝基板佈局是否 有發生佈局及圖式（layout vs. schematic, LVS)錯誤及違 反設計規則檢查（design-rule-checking, DRC)的情形。在 步驟102中，產生一對應檔案用以對應（mapping)—個或 一個以上的封裝基板層。上述對應檔案可以視為對應資 料集合(mapping dataset)，包含晶片與封裝基板的接腳層 (pin layer)、封裝基板的導體暨插塞層（conductor-and_via layer)、用以連接封裝基板之導體暨介模層的貫孔層（via drill hole layer)或稱為穿孑L層（through-via layer)。在步驟 104，產生第一格式的封裝基板佈局資料集合，該第一格 0503-A31608TWF/Joseph 5 1312929 式例如多晶片模組(multi-chip module, MCM)格式。上述 第一格式的封裝基板佈局資料集合以及上述對應檔案被 插入一軟體，例如 Cadence Chip I/O Planner (CIOP)或 Advance Package Designer (APD)，並在步驟 l〇6 被連串 輸出（streamed out)。輸出程序將上述對應檔案合併於上 述封裝基板佈局資料集合成為一單一資料集合。此處所 謂“合併”後的資料集合在步驟114受到另外的調整，其 座標（coordinate)被置換（flip)及移動（shift)以符合晶片佈 局資料集合之座標。最後在步驟116上述“合併”後的資 料集合被儲存在一第一資料庫，並轉換至第二格式，即 上述晶片佈局資料集合的格式。舉例來說，上述第二格 式是一種可以圖形瀏覽及編輯的圖形設計系統第二格式 (graphic design system II, GDSII)。換言之，步驟 1〇6、114 以及116之組合可以被視為一系列的轉換步驟，用以將 封裝基板佈局資料集合從第一格式轉換成第二格式。 步驟108之中，檢查輸出的封裝基板佈局資料集合 訊號接腳位置（pin-out location)，該訊號接腳位置定義封 裝排列（package alignment)及尺寸(dimemsion)以禮保封 裝基板佈局符合晶片佈局。在步驟110, 一旦產出訊號接 腳檔案（pin-out file) ’上述訊號接腳位置資料會被置換、 移動及轉換(translate)。此步驟在覆晶式（flip_chip)封裝的 情況中是必需的。在覆晶式封裝中，封裝基板佈局的座 標糸統通常不同於晶片佈局的座標系統。封裝基板佈局 的原點總是在佈局的中心，並且須以一預定的假想軸（例 0503-A31608TWF/Joseph 6 1312929 如Y軸）為準被鏡反射影。因此，需要調整以符合晶片佈 局的座標系統。在步驟112，產生一文字檔以引導上述軟 體執行錯誤檢查。此文字檔可以被視為一比對資料集 . 合。如第1圖所示，可以同時地執行上述步驟1〇8、11〇 以及112與步驟114及116。 提供類似的步驟以產生第二格式的晶片佈局資料集 合’例如GDSII格式。在步驟1 〇8中，利用上述晶片放 φ 置位置及線路配置（place and route, P&R)資料庫產生位 置及線路配置（p&R)資料集合，實質上為未經格式化的網 表（unf〇rmatte(i netlist)。須要了解的是上述位置及線路配 置資料庫包含晶片佈局資料。在步驟12〇進一步地輸出 並轉換上述位置及線路配置資料庫至上述GDSII，與轉 換後的封裝基板佈局資料集合之格式相同。在步驟122 儲存上述GDSII的晶片佈局資料集合於一第二資料庫。 步驟118、120及122之組合可以被視為將晶片佈局資料 φ 集合從一格式轉換至另一格式的方法，例如從一網表格 式至一 GDSII格式。 在可以進行錯誤檢查之前的最後一步驟，即步驟124 中，產生一命令播（command file)。此命令檔可以視為一 命令資料集合，用以指示一模型製造工具（modeling tool)，例如凱樂伯（Calibre) ’以合併封裝基板佈局資料集 合及晶片佈局資料集合，並執行各種的錯誤檢查及設計 規則不符等檢查，例如LVS檢查或DRC檢查。可以利用 LVS工具或DRC工具執行此檢查步驟。在步驟126中， 0503-A31608TWF/Joseph 7 1312929 接著合併GDSII的晶片佈局資料集合與GDSII的封裝基 板佈局資料集合。因此，在步驟126使用的模型製造工 具可以基於晶片佈局資料集合及封裝基板佈局資料集合 整體，以整合的方式檢查此合併資料集合以找出是否有 ' 錯誤或設計規則不符。這種方法對傳統上分別地檢查晶 ' 片與封裝基板佈局的技術提供了重大的改良。 第2圖顯示根據本發明一實施例之部分螢幕晝面 $ 200,其中顯示封裝基板佈局資料集合中的複數導體及介 層（via layer)。雖然上述導體可以熟習半導體封裝技術者 所知其它、的導電材質製成，在此實施例中，上述導體材 質為金屬銅。經由層層覆加數個導體暨插塞層以構成上 述封裝基板。對於每一導體層，典型上會有對應的介層 存在。這些插塞（via)不一定是以筆直地配置穿過導體 層。這些插塞可以起起浮浮的（jog)，使得一導體連接的 二個插塞（一個在該導體上的插塞及一個在該導體下的插 _ 塞）可以在垂直方向上互相對齊。 在此實施例中，五個模層由軟體定義如圖示：L01、 DRILL_01_02、L02、DRILL_02_03、以及 L03。上述介 層L01、L02及L03相似。上述模層DRILL_01_02為孔 層（drill layer)，用以將介層L01及L02連接在一起。孔 層DRILL_01_02與DRILL—02_03也類似。最後，三行最 右邊的欄位描述上述對應各層的尺寸，而上述尺寸定義 於複數列中。需要用這些模層的定義資訊以產生封裝基 板佈局資料集合。 0503-A31608TWF/Joseph 8 1312929 第3A圖顯示六層（six-layer)封裝基板之剖面圖 300，其中包含導體暨插塞層以及孔層（亦稱為“穿孔 層”）。每一層被賦與一號碼、一類別以及一子類別。模層 L01包含晶片接合凸塊（chip landing bumps)、導體暨插塞 層。接下來的數層，除了模層L06以外，只含導體及插 塞。最後一層，即模層L06，包含導體、插塞以及封裝設 定凸塊（package setting bumps)。孔層 drill_01_02 及 drill_05_06連接模層L01至L06全部。雖然此實施例僅 例舉六層，須要了解的是一封裝基板可以較少或較多的 模層構成。第3B圖有模層命名慣例較詳細的解釋。 第3B圖顯示對應第3A圖中之六層封裝基板的一對 應檔案（mapping file)306。對應檔案306中層集合資料 (layer set data)包含導體、插塞、貫孔（drill via holes，又 稱為穿孔(through-vias))至少一資料集合。在第一層集合 (layer set)中，上述導體資料命名為模層“1”並對應子類別 “L01”，上述插塞資料命名為模層“101”並對應子類別 “L01”，而貫孔資料命名為模層“201”並對應一特別的子 類別“drill_01_02”。採用上述貫孔資料子類別的命名慣例 是為了方便表示上述貫孔層與哪二層連接。上述層集合2 至5類似於上述層集合1。上述第一及最後一個模層為包 含晶片接合凸塊及封裝設定凸塊的特別模層。照慣例而 言，命名為模層“0”並對應子類別“L01”，而上述晶片接 合凸塊對應第3A圖中剖面圖300之第一層。包含封裝設 定凸塊的最後一層通常被給與下一個可用的百位數字。 0503-A31608TWF/Joseph 9 1312929 在此情況中，上述導體命名為模層“6”並對應子類別 “L06”，上述模層“6”對應剖面圖300之最後一層。再者， 封裝設定凸塊命名為模層“300”並對應子類別“L06”。 如參照第1圖所作的說明，對應檔案306將被併入 封裝基板佈局資料集合，其中該封裝基板佈局資料集合 將被轉換並進一步合併於晶片佈局資料集合。為了要消 除封裝基板模層及晶片模層的模層號碼中任何碼號重複 情形，以一補償值調整封裝基板模層的模層號碼。因此， 當模型製造工具檢查上述合併資料集合是否有錯誤時， 這樣可以避免重複編號的問題。 第4圖顯示根據本發明一實施例之一命令檔案 (command file)400之部分文字結構，該命令檔案對應第1 圖的步驟124。當一模型製造工具（例如Calibre)能夠讀取 輸入的複數檔案時，它必需被命令這樣運作。明確來說， 為了要執行二個GDSII檔案的LVS檢查，此二個GDSII 檔案的上層（top level)單元（cell)名及檔名須被特定化。舉 例來說，命令檔案400的前三行定義晶片GDSII檔案， 即第一檔案。Line 1指定名稱，而Line 2指定檔案路徑。 Line 3是一命令行用以指定該檔案是一 GDSII檔案。命 令檔案400的接下來三行定義封裝GDSII檔案，即第二 檔案。封裝GDSII檔案的模層號碼會以定義的補償值移 動（shift)。舉例來說，在Line 4的STR1是GDSII的預設 元件名稱。並且，Line 7指出一補償值800會加到封裝 GDSII檔案的模層號碼。如果上述封裝基板具有多於8 0503-A31608TWF/Joseph 10 131-2929 的層上述模型裝造工具將會加入下一個可用的百 位數位至上述封| GDSII _。加人鋪償值至上述封 裝GDSII棺案是為了要確保在Lvs檢查中，封裝基板佈 局資料集合被視為不同的實體來處理。須要了解的是雖 然基於GDSII格式的一個命令檔被用來解釋此實施例， 此命令㈣可以屬於不同的資料結構以相容於上述模型 製造工具所接受的檔案格式。 • 第5A_5C圖顯示根據本發明各種實施例之一命令檔 案之一部分，即模層定義檔，之各個段落502、504、506、 508及510。在檢查（如LVS或DRC檢查）可進行之前， 須修改上述封裝基板佈局資料集合。上述模層定義檔案 可以被視為已格式化網表的修改後版本。以下列出部分 需進行的修改。段落502定義凸塊至輸入輸出 (bump-to-1/O)之路徑的一個或一個以上的模層。此步驟定 義上述封裝基板的_訊號接腳位置（pin_〇ut)的最後位置及 φ 間隔。必須這麼做以確保封裝的凸塊佈局符合晶片I/O 接腳。明確而言’ Line 1至6指出不同的導體層如何連 接在一起。Line 1及2指出導體層及介層，而Line 3指 出這二層之間的連接。Line 4、5及6代表如Line 1、2 及3所示的類似的結構。 段落504定義複數模層及對應（mapping)。此段落類 似第3B圖。Line 1定義晶片接合凸塊。Line 2定義導體 層。Line 3 定義製造層（production layer)，而 Line4 定義 介層。Line 5 至 Line 9 類似 Line 2 至 Line 4。Line 20 定 0503-A31608TWF/Joseph 11 1312929 義封裝設定凸塊。如圖示，Line 1以“800”為始，即先前 所定義的補償值。 段落506定義模層間的連接，亦即用以將導體及介 層連接在一起的模層。Line 2以封裝插塞1指出封裝層1 及封裝層2之間的連接。Line 3至6類似Line 2，而Line 1指出開頭的封裝層1，由於其中被定義的凸塊而不同於 其它的模層。 段落508定義封裝的晶片接合凸塊至晶片凸塊之間 的連接。類似地，段落510定義封裝設定凸塊至印刷電 路板(printed circuit board)之間的連接0 第6圖顯示本發明一實施例之一文字檔602的實 例。文字檔602對應至第1圖的步驟112。如先前所解釋 的，文字槽602指示模型製造工具如何合併封裝基板佈 局資料集合及晶片佈局資料集合。明確而言，所有封裝 連接物（例如焊接球（solder ball))的位置及網名（net name) 可以從軟體（例如CI0P或APD)輸入文字檔，典型上為 ASCn檔案。在置換及移動座標後，上述文字檔可以自動 執行檔（script)轉換為上述模型製造工具可以接受的格式 以識別埠位置。段落604包含加入上述命令檔案的額外 的數行使文字檔602經過語法分析（parse)。 此發明提出一新的方法及系統以整合方式檢查封裝 基板佈局資料集合及晶片佈局資料集合以確認是否有 LVS錯誤及DRC不符情形。這些檢查可以經由合併二個 資料集合成為一個來同時進行。此發明的優點包含更快 0503-A31608TWF/Joseph 12 1312929 速的單晶片系統（system on chip, SoC)製造、較少的LVS 及DRC錯誤以及較便宜的製造成本。 使用者以一軟體定義合併資料集合之模層。這定義 包含封裝的介層及導體層，以及從晶片到封裝基板之各 ' 層之間的連接。如果所有模層已被定義，則可以識別出 ' LVS以及DRC的錯誤。可以沿用比對試算表的方式以識 別封裝基板及晶片的凸塊圖樣配對上的微小錯誤。雖然 I 這些配對上的錯誤（misalignment)不會造成LVS或DRC 的差錯，但是它會損害封裝的產量。 上述舉例說明提供許多不同的實施例或實作本發明 不同特徵的實施例。描述元件及處理程序的特定實施例 是為了要使本發明清楚明白。當然這些只是實施例而非 用以從以下的申請專利範圍中限定本發明。 雖然本發明已以一個或一個以上的較佳實例揭露如 上，然其詳細說明並非用以限定本發明，在不脫離本發 I 明之精神、在申請專利範圍的均等物的範圍内，當可作 各種之更動與結構上的變更。因此，後附之申請專利範 圍應從寬解讀並與本發明之範圍一致，如以下申請專利 範圍所示。 0503-A31608TWF/Joseph 13 1312929 【圖式簡單說明】 第1圖顯示根據本發明一實施例之可以整合方式檢 查晶片與封裝基板佈局是否有發生錯誤及違反設計規則 的情形的系統之處理流程。 第2圖顯示根據本發明一實施例之部分螢幕晝面， ' 其中顯示各種導體層及介層（via layer)。 第3A圖顯示根據本發明一實施例之封裝基板之剖 • 面圖。 第3B圖顯示根據本發明一實施例對應第3A圖中之 剖面圖的一對應檔案（mapping file)之部分文字結構。 第4圖顯示根據本發明一實施例之一命令檔案 (command file)之部分文字結構，該命令槽案用以指導一 模型製造工具在晶片與封裝基板佈局上執行檢查是否有 發生錯誤及違反設計規則的情形。 第5A-5C圖顯示根據本發明一實施例之一命令檔案 φ (command file)的各個段落。 第6圖顯示本發明一實施例之一模型製造工具的文 字檔。 【主要元件符號說明】 100〜處理流程； 102-126〜步驟； 200〜螢幕畫面； 300〜封裝基板之剖面圖； 306〜對應檔案； 400〜命令檔案； 502、504、506、508 及 510〜段落； 602〜文字檔； 604〜段落。 0503-A31608TWF/Joseph 141312929 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an integrated debug method for semiconductor wafer design and special package and package substrate layout. It is carried out in the place of the design of the W. In the design phase, unattended, in the assembly process, when all the parts are assembled for assembly; These issues include differences in the supply of electricity, logical aspects, and = compatibility. If the error is not found at an early stage, the production is due to the fact that the layout of the wafer and the layout of the package substrate are often inconsistent and inconsistent with the design rules == Bureau and package substrate layout - it is difficult to pass, "chip manufacturing program" The layout of the layout board - the area that the designer can hardly touch. Traditionally, using ^ table = eadSheet) to check the layout between the wafer and the package substrate = even the wei: and = extremely error-prone 'because most of the trial The content of the table is checked: ΐ: ί semiconductor wafer design needs to be improved method and system design ; 2;: whether the substrate is finer or not [invention content] 0503-Α31608TWF/J〇seph 4 1312929 In view of this, this SUMMARY OF THE INVENTION The present invention provides an integrated error detection method and system for wafer and package substrate layout. Based on the above objects, the present invention provides an integrated < error method and system for a wafer layout data set and a package substrate layout data set. In one embodiment, the package substrate layout data set is converted from the first format to the second format, wherein the wafer layout data set is presented in the second format Combining the above-mentioned wafer layout data set of the second format and the above-mentioned package substrate layout data set into a combined data set, and then checking whether the merged data set has an error or violates a design rule. The construction and operation method of the present invention, additional purposes Advantages and advantages of the present invention will be obtained from the following description of the specific embodiments and the accompanying drawings. [Embodiment] FIG. 1 illustrates a process flow 100 of a consistent embodiment of the present invention, and the system is inspected in an integrated manner. Whether the layout of the wafer and the package substrate has a layout vs. schematic (LVS) error and a design-rule-checking (DRC) violation. In step 102, a corresponding file is generated to correspond. Mapping—one or more package substrate layers. The corresponding file can be regarded as a corresponding data set, including a pin layer of the wafer and the package substrate, and a conductor and plug layer of the package substrate ( a conductor-and-via layer), a via drill hole layer for connecting a conductor and a die layer of the package substrate or In order to pass through the through-via layer, in step 104, a package substrate layout data set of a first format is generated, the first cell 0503-A31608TWF/Joseph 5 1312929 type, for example, a multi-chip module (multi-chip module, MCM) format. The package substrate layout data set of the first format and the corresponding file are inserted into a software, such as Cadence Chip I/O Planner (CIOP) or Advance Package Designer (APD), and are serialized in step l〇6. Streamed out. The output program merges the corresponding files into the package substrate layout data set to become a single data set. The "merged" data set referred to herein is additionally adjusted in step 114, with its coordinates being flipped and shifted to conform to the coordinates of the wafer layout data set. Finally, in step 116, the "merged" data set is stored in a first database and converted to a second format, i.e., the format of the above-described wafer layout data set. For example, the second format described above is a graphic design system II (GDSII) that can be graphically viewed and edited. In other words, the combination of steps 1, 6, 114, and 116 can be viewed as a series of conversion steps for converting the package substrate layout data set from the first format to the second format. In step 108, the output package substrate layout data set pin-out location is checked, and the signal pin position defines a package alignment and a dimemsion to ensure that the package substrate layout conforms to the wafer layout. . At step 110, once the output signal pin location data (pin-out file) is replaced, moved and translated. This step is necessary in the case of a flip-chip package. In a flip chip package, the coordinate system of the package substrate layout is typically different from the coordinate system of the wafer layout. The origin of the package substrate layout is always at the center of the layout and must be mirrored by a predetermined imaginary axis (eg 0503-A31608TWF/Joseph 6 1312929 such as the Y axis). Therefore, adjustments are needed to match the coordinate system of the wafer layout. At step 112, a text file is generated to direct the software to perform an error check. This text file can be viewed as a comparison data set. As shown in Fig. 1, the above steps 1〇8, 11〇 and 112 and steps 114 and 116 can be performed simultaneously. Similar steps are provided to produce a wafer layout data set of the second format, e.g., the GDSII format. In step 1 〇8, the position and route configuration (p&R) data set is generated by using the above-mentioned wafer placement position and route configuration (P&R) database, which is essentially an unformatted network. Table (unf〇rmatte(i netlist). It is necessary to understand that the above location and line configuration database contains the wafer layout data. In step 12, the location and line configuration database is further output and converted to the above GDSII, and the converted The format of the package substrate layout data set is the same. The chip layout data of the GDSII is stored in a second database in step 122. The combination of steps 118, 120 and 122 can be regarded as converting the wafer layout data φ set from one format to Another format method, for example, from a netlist format to a GDSII format. In the last step before the error check can be performed, step 124, a command file is generated. This command file can be regarded as a command. a collection of data to indicate a modeling tool, such as Calibre, to merge package substrate layout data sets And the set of wafer layout data, and perform various error check and design rule inconsistency checks, such as LVS check or DRC check. This check step can be performed using the LVS tool or DRC tool. In step 126, 0503-A31608TWF/Joseph 7 1312929 The GDSII wafer layout data set and the GDSII package substrate layout data set are then merged. Therefore, the model manufacturing tool used in step 126 can check the merged data set in an integrated manner based on the wafer layout data set and the package substrate layout data set as a whole. To find out if there is a 'error or design rule discrepancy. This method provides a significant improvement over the technology that traditionally checks the layout of the wafer and package substrate separately. Figure 2 shows a portion of the screen according to an embodiment of the invention. A surface of $200, wherein the plurality of conductors and via layers in the package substrate layout data set are displayed. Although the conductors are made of other conductive materials known to those skilled in the semiconductor package, in the embodiment, the conductors The material is metal copper. It is layered with several conductors and plug layers. The above package substrate is formed. For each conductor layer, there is typically a corresponding intervening layer. These vias are not necessarily arranged straight through the conductor layer. These plugs can float up (jog The two plugs that connect one conductor (one plug on the conductor and one plug under the conductor) can be aligned with each other in the vertical direction. In this embodiment, five mold layers are The software definition is as shown: L01, DRILL_01_02, L02, DRILL_02_03, and L03. The above layers L01, L02 and L03 are similar. The above-mentioned mold layer DRILL_01_02 is a drill layer for connecting the layers L01 and L02 together. The hole layer DRILL_01_02 is similar to DRILL_02_03. Finally, the rightmost field of the three rows describes the dimensions of the corresponding layers described above, and the above dimensions are defined in the plural columns. The definition information of these dies is needed to produce a package substrate layout data set. 0503-A31608TWF/Joseph 8 1312929 Figure 3A shows a cross-sectional view 300 of a six-layer package substrate including a conductor and plug layer and a hole layer (also referred to as a "perforated layer"). Each layer is assigned a number, a category, and a subcategory. The mold layer L01 includes a chip landing bumps, a conductor and a plug layer. The next few layers, except the mold layer L06, contain only conductors and plugs. The last layer, the mold layer L06, contains conductors, plugs, and package settings bumps. The hole layers drill_01_02 and drill_05_06 are connected to all of the mold layers L01 to L06. Although this embodiment exemplifies only six layers, it is to be understood that a package substrate can be constructed with fewer or more mold layers. Figure 3B has a more detailed explanation of the modeling naming convention. Fig. 3B shows a pair of mapping files 306 corresponding to the six-layer package substrate in Fig. 3A. The layer set data of the corresponding file 306 includes at least one data set of conductors, plugs, and through-vias. In the first layer set, the conductor data is named as the layer "1" and corresponds to the sub-category "L01", and the plug data is named as the layer "101" and corresponds to the sub-category "L01". The hole data is named "201" and corresponds to a special sub-category "drill_01_02". The naming convention of the above-mentioned through-hole data sub-category is to facilitate the connection between the above-mentioned through-hole layers and which two layers. The above layer sets 2 to 5 are similar to the above layer set 1. The first and last mold layers are special mold layers including wafer bond bumps and package set bumps. Conventionally, the layer "0" is named and corresponds to the sub-category "L01", and the above-mentioned wafer bonding bump corresponds to the first layer of the cross-sectional view 300 in Fig. 3A. The last layer containing the package set bumps is usually given the next available hundred digits. 0503-A31608TWF/Joseph 9 1312929 In this case, the above conductor is named as the mold layer "6" and corresponds to the sub-category "L06", and the above-mentioned mold layer "6" corresponds to the last layer of the cross-sectional view 300. Furthermore, the package setting bump is named as the template layer "300" and corresponds to the sub-category "L06". As illustrated with reference to Figure 1, the corresponding file 306 will be incorporated into a package substrate layout data set, wherein the package substrate layout data set will be converted and further incorporated into the wafer layout data set. In order to eliminate any code number repetition in the mold layer number of the package substrate mold layer and the wafer mold layer, the mold layer number of the package substrate mold layer is adjusted with a compensation value. Therefore, when the model manufacturing tool checks whether there is an error in the above merged data set, this avoids the problem of repeated numbering. Figure 4 shows a partial text structure of a command file 400 in accordance with an embodiment of the present invention, the command file corresponding to step 124 of Figure 1. When a model making tool (such as Calibre) can read the input plural file, it must be commanded to do so. Specifically, in order to perform an LVS check of two GDSII files, the top level cell name and file name of the two GDSII files must be specified. For example, the first three lines of the command file 400 define the wafer GDSII file, the first file. Line 1 specifies the name, and Line 2 specifies the file path. Line 3 is a command line used to specify that the file is a GDSII file. The next three lines of the command file 400 define the package GDSII file, the second file. The module number that encapsulates the GDSII file is shifted by the defined offset value. For example, STR1 in Line 4 is the default component name for GDSII. Also, Line 7 indicates that a compensation value of 800 will be added to the module number of the packaged GDSII file. If the above package substrate has more than 8 0503-A31608TWF/Joseph 10 131-2929, the above model building tool will add the next available hundred digits to the above seal | GDSII _. The addition of the compensation to the above-mentioned packaged GDSII case is to ensure that the package substrate layout data set is treated as a different entity in the Lvs inspection. It is to be understood that although a command file based on the GDSII format is used to interpret this embodiment, the command (4) may belong to different data structures to be compatible with the file format accepted by the model manufacturing tool described above. • Figure 5A-5C shows a portion of a command file, i.e., a template definition file, for each of the paragraphs 502, 504, 506, 508, and 510, in accordance with various embodiments of the present invention. The above package substrate layout data set must be modified before inspection (such as LVS or DRC inspection) can be performed. The above-mentioned template definition file can be regarded as a modified version of the formatted netlist. Some of the changes that need to be made are listed below. Paragraph 502 defines one or more dies of bumps to the path of the input-output (bump-to-1/O). This step defines the last position of the _ signal pin position (pin_〇ut) of the above package substrate and the φ interval. This must be done to ensure that the bump layout of the package conforms to the wafer I/O pins. Specifically, 'Lines 1 through 6 indicate how different conductor layers are connected together. Lines 1 and 2 indicate the conductor layer and the dielectric layer, while Line 3 indicates the connection between the two layers. Lines 4, 5 and 6 represent similar structures as shown in Lines 1, 2 and 3. Paragraph 504 defines a complex modular layer and mapping. This paragraph is similar to Figure 3B. Line 1 defines the wafer bond bumps. Line 2 defines the conductor layer. Line 3 defines the production layer and Line4 defines the layer. Line 5 to Line 9 are similar to Line 2 to Line 4. Line 20 0503-A31608TWF/Joseph 11 1312929 Meaning package setting bump. As shown, Line 1 starts with “800”, which is the previously defined compensation value. Paragraph 506 defines the connections between the mold layers, i.e., the mold layers used to join the conductors and the layers together. Line 2 indicates the connection between the encapsulation layer 1 and the encapsulation layer 2 by the package plug 1. Lines 3 through 6 are similar to Line 2, while Line 1 indicates that the first package layer 1 differs from the other mold layers due to the defined bumps therein. Paragraph 508 defines the connection between the packaged wafer bond bumps to the wafer bumps. Similarly, paragraph 510 defines the connection between the package setting bumps to the printed circuit board. FIG. 6 shows an example of a text file 602 in accordance with one embodiment of the present invention. The text file 602 corresponds to step 112 of FIG. As previously explained, the text slot 602 indicates how the model fabrication tool merges the package substrate layout data set and the wafer layout data set. Specifically, the location and net name of all package connectors (such as solder balls) can be entered from a software (such as CIOP or APD), typically an ASCn file. After the displacement and movement of the coordinates, the above text file can be automatically converted into a format acceptable to the model manufacturing tool to identify the position. Paragraph 604 includes an additional number of exercise text files 602 that are added to the above command file for parsing. The invention proposes a new method and system for inspecting the package substrate layout data set and the wafer layout data set in an integrated manner to confirm whether there is an LVS error and a DRC discrepancy. These checks can be performed simultaneously by combining two sets of data into one. The advantages of this invention include faster 0503-A31608TWF/Joseph 12 1312929 speed system on chip (SoC) fabrication, less LVS and DRC errors, and less expensive manufacturing costs. The user defines the template layer of the merged data set in a software. This defines the interposer and conductor layers of the package, as well as the connections between the layers from the wafer to the package substrate. If all the layers have been defined, the 'LVS and DRC errors can be identified. A comparison of the spreadsheets can be used to identify minor errors in the package pattern and the bump pattern pairing of the wafer. Although the misalignment of these pairings does not cause an LVS or DRC error, it can impair the yield of the package. The above examples illustrate embodiments that provide many different embodiments or implement different features of the invention. The specific embodiments of the described components and processing procedures are intended to be illustrative of the invention. Of course, these are only examples and are not intended to limit the invention from the scope of the following claims. The present invention has been described above with reference to one or more preferred embodiments thereof, and the detailed description is not intended to limit the scope of the present invention. Various changes and structural changes. Therefore, the scope of the appended claims should be interpreted broadly and in accordance with the scope of the invention, as shown in the following claims. 0503-A31608TWF/Joseph 13 1312929 [Simple Description of the Drawings] Fig. 1 shows a processing flow of a system in which the layout of the wafer and the package substrate can be inspected in an integrated manner and the design rules are violated in an integrated manner according to an embodiment of the present invention. Figure 2 shows a portion of a screen surface, 'where various conductor layers and via layers are shown, in accordance with an embodiment of the present invention. Fig. 3A is a cross-sectional view showing a package substrate in accordance with an embodiment of the present invention. Figure 3B shows a partial text structure of a corresponding mapping file corresponding to the cross-sectional view of Figure 3A, in accordance with an embodiment of the present invention. 4 is a partial text structure of a command file for guiding a model manufacturing tool to perform an inspection on a wafer and a package substrate layout to check whether an error has occurred and a design violation is in accordance with an embodiment of the present invention. The situation of the rules. Figures 5A-5C show various paragraphs of a command file φ (command file) in accordance with one embodiment of the present invention. Fig. 6 is a view showing a character file of a model manufacturing tool according to an embodiment of the present invention. [Main component symbol description] 100~ processing flow; 102-126~step; 200~screen screen; 300~ package substrate sectional view; 306~ corresponding file; 400~ command file; 502, 504, 506, 508 and 510~ Paragraph; 602 ~ text file; 604 ~ paragraph. 0503-A31608TWF/Joseph 14