KR20240035626A - Automatic redistribution layer via generation - Google Patents

Abstract

A system and method are described for automatically generating via placement within a redistribution layer of a semiconductor package. In various implementations, the user defines properties to be used for automatic via creation in the redistribution layer of the semiconductor package 702. Processor circuitry of the computing device used by the user executes the instructions of the automatic redistribution layer (RDL) via generator 704. The automatic via generator uses attributes, data representing the RDL netlist of signal roots within the RDL, and RDL mask layout data representing the signal masks of metal layers within the RDL. The processor generates via placement for the RDL based on the properties and identification of the overlapping areas between metal layers.

Description

Automatic redistribution layer via generation

Cross-reference to related applications

This application claims priority to Provisional Patent Application Serial No. 63/228,552, entitled “Via Generation for Silicon Layout,” filed August 2, 2021, the entire contents of which are incorporated herein by reference. .

Related technical description

There is increasing demand for semiconductor packages that provide communication between one or more integrated circuits within a chip package and external components on a motherboard located outside the chip package. Electronics associated with mobile computing, wearable electronics, and the Internet of Things (IoT) are driving demand for small packages that utilize vertical signal interconnects. Examples of chip packages used in this product include Ball Grid Array (BGA), Chip Scale Package (CSP), and System in Package (SiP).

Semiconductor packages utilize controlled collapse chip connection (C4) interconnection, also referred to as flip chip interconnection. For example, the C4 bump connects to a vertical through silicon via (TSV) formed in a silicon package substrate that is connected to a printed circuit board using a bump pad. A group of TSVs formed across a silicon bus serves as an interconnection between the base die, one or more additional integrated circuits, and routing on a printed circuit board (PCB) such as a motherboard or card. Demand for SiP and more signal interconnects between integrated circuits and printed circuit boards (PCBs) also increases the demand for package substrates and interposers.

The package substrate is the part of the chip package that provides mechanical base support as well as electrical interfaces for signal interconnects. An interposer is an intermediate layer between one or more integrated circuits and flip chip bumps or other interconnects and the package substrate. When used, the interposer provides an electrical interface for signal interconnections between a die assembled thereon (die-to-die interconnect) and a package substrate (die-to-package interconnect). Depending on the implementation, the terms package substrate and interposer are used interchangeably.

One or more integrated circuits within a semiconductor package have signal routes connected between the motherboard (or printed circuit board) and the integrated circuit using a redistribution layer. The signal route of the redistribution layer is a signal route located between a micro bump in contact with a pad of the integrated circuit and a through-type silicon via (TSV) of the silicon package substrate.

Although innovations provide improvements, design challenges still arise with modern processing techniques and integrated circuit designs that limit the potential benefits. One problem is that one or more integrated circuits may have tens of thousands of nodes to receive one or more power supply voltage reference levels and one or more ground reference voltage levels, and simultaneously hundreds of nodes to transmit these voltage reference levels from the TSV. . Routing of these power connections through the redistribution layer becomes complex. Additionally, manually placing vias in a masked layout representation of these signal routes before performing verification checks and subsequent fabrication can take weeks or months.

In view of the above, an efficient method and system for creating vias for power connections within a redistribution layer is desired.

1 is a schematic diagram of a computing system.
2 is a schematic diagram of a cross-sectional view of a semiconductor package metal layer scheme.
3 is a schematic diagram of the metal layer of the redistribution layer.
Figure 4 is a schematic diagram of the metal layer of the redistribution layer.
Figure 5 is a schematic diagram of the metal layer of the redistribution layer.
Figure 6 is a schematic diagram of the graphical user interface.
7 is a schematic diagram of one embodiment of a method for automatic via creation in a redistribution layer.
8 is a schematic diagram of one embodiment of a method for automatic via creation in a redistribution layer.
9 is a general diagram of a computing system.
While the invention is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are herein described in detail. However, the drawings and their detailed description are not intended to limit the invention to the specific form disclosed, but on the contrary, the invention is intended to be open to all modifications, equivalents and substitutes falling within the scope of the invention as defined in the appended claims. It should be understood as covering.

In the following description, numerous specific details are set forth to provide a thorough understanding of the invention. However, one skilled in the art should recognize that the present invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the invention. Additionally, for simplicity and clarity of illustration, it will be appreciated that elements depicted in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated compared to others.

Systems and methods for automatically creating vias within a redistribution layer are contemplated. As used herein, the terms “automated generation” or “automatically generating” refers to having the ability to perform a generation or perform a generation step without user intervention. As disclosed herein, a user defines properties to be used for automatic via creation in a redistribution layer of a semiconductor package. In one implementation, a user provides properties through a graphical user interface (GUI). In other implementations, users provide properties through a text file or executable file written in one of a variety of scripting languages. The computing device used by the user includes hardware such as processor circuitry for executing instructions of the automatic via generator. The automatic via generator generates attributes, a copy of the redistribution layer (RDL) netlist of the signal roots in the redistribution layer (RDL), and RDL mask layout data representing the signal masks of the metal layers in the RDL. Use a copy.

When the computing device's processor executes the instructions of the automatic via generator, the processor identifies areas of metal overlap between the metal layers of the RDL. The metal overlap region is also referred to as a metal overlap bond zone or overlap bond zone. In some implementations, the metal overlap region is between adjacent metal layers of an RDL, such as metal layers RDL1 and RDL2. In another implementation, the metal overlap region is between two non-adjacent metal layers of an RDL, such as a through hole via (RDL1 and RDL4). In another implementation, the metal overlap region is between the fins of the surface mount device (SMD) fin layer and the metal layer of the RDL. In another implementation, the metal overlap region is between the metal layer of the RDL and the under-bump metallurgy (UBM) layer that provides the electrical connection to the C4 bump. In some examples, the metal overlap area has a square or rectangular shape, such as the metal overlap area between two metal layers of an RDL. In another example, the metal overlap area has a circular shape, such as the metal overlap area between the metal layer of the RDL and the fins of the SMD pin layer. For valid via creation, the metal overlap area between two metal layers is greater than or equal to the minimum overlap joint area threshold. In some implementations, based on the received attributes, the processor splits the overlap region in half such that the via layer is placed both above and below the overlap region. Based on the attributes received from the user, the processor places different types of via layers in overlapping areas.

The processor creates vias based on the sequence order indicated in the received attributes. The sequence order determines which via layer will be used to initiate automatic via creation and which of each subsequent via layer will be selected for further automatic via creation. Vias are placed based on their size and pitch corresponding to the currently selected via layer to satisfy the DRC rules. Additionally, the processor does not change the metal layer dimensions of the signal route during via placement. If multiple sequences for a given via layer are specified in the received attribute, the processor places additional vias in the via layer if possible. In some cases via redundancy already exists, but the automatic via generator continues to increase the via count when possible. The processor then generates a report. The processor maintains log files during automatic via creation and uses the corresponding information to provide summarized results in a report. In various implementations, the processor creates a file located at a known destination.

In the following description, a computing system for supporting the development of hardware products using a semiconductor package substrate is shown in FIG. 1. The computing system supports automatic creation of vias in the redistribution layer. 2 illustrates components of a semiconductor package, such as a redistribution layer, using flip chip technology. 3-5 illustrate metal overlap areas between adjacent metal layers of a redistribution layer. An example of a graphical user interface for providing attributes from the user to be utilized during automatic creation of vias in the redistribution layer is shown in Figure 6. 7-8 provide method steps to support automatic creation of vias in a redistribution layer. An example of a fabricated chip package containing automatically created vias in a redistribution layer, within a computing system, is shown in FIG. 9 .

1, a generalized block diagram of one embodiment of computing system 100 is shown. In the illustrated implementation, computing system 100 includes client computing devices 150, servers 120A-120D including hardware to execute software and support organization center 110, network 140, and organization center 110. and a data storage device 130 containing one or more data stores supported and used by center 110. Although a single client computing device 150 is shown, any number of client computing devices may utilize organization center 110 over network 140. Client computing device 150, also referred to as client device 150, includes hardware, such as circuitry of a processor, to execute instructions of redistribution layer (RDL) automatic via generator 160. The RDL automatic via generator 160 (or via generator 160) uses a copy of the data stored in data storage 130 and attributes 166 provided by the user. In an implementation, a user provides properties 166 through a graphical user interface (GUI) 162. Examples of data used by via generator 160 are copies of at least a portion of RDL mask layout data 132, RDL netlist, and design rule check (DRC) 136.

Client device 150 includes a desktop computer or a mobile computing device such as a laptop, tablet computer, etc. Client device 150 includes hardware circuitry, such as processing unit 170, for processing instructions of a computer program. In some implementations, processing unit 170 includes one or more homogeneous cores of a processor. In another embodiment, the processing unit includes heterogeneous cores, such as parallel processing architecture cores and general purpose cores used in a central processing unit (CPU). The parallel architecture core may be a graphics processing unit (GPU), a digital signal processing unit (DSP), etc.

Client device 150 includes a network interface (not shown) that supports one or more communication protocols for transferring data and messages over network 140. Network 140 includes multiple switches, routers, cables, wireless transmitters, and the Internet for transmitting messages and data. Accordingly, the network interface of organization center 110 and client device 150 supports at least Hypertext Transfer Protocol (HTTP) for communication over the World Wide Web. In addition to communicating with client device 150 over network 140, organization center 110 also communicates with data storage 130 to store and retrieve data.

In various implementations, organization center 110 is an infrastructure for vendors that produce one or more hardware products. Organization center 110 includes an intranet network that provides a private network accessible only to employees of the organization. Intranet portals are used to provide access to resources through user-friendly interfaces such as graphical user interfaces (GUIs) and dashboards. Information and services made available by organization center 110 are not available to the general public through direct access. Through user authentication, employees can access resources through the organization center 110 to communicate with other employees, collaborate on projects, monitor product development, update products, documents, and tools stored in a central repository, etc. can do.

Servers 120A-120D used to support organization center 110 and resources accessed through organization center 110 include various server types such as database servers, computing servers, application servers, file servers, mail servers, etc. do. In various implementations, servers 120A-120D and client devices 150 operate in a client-server architecture model.

Client device 150 includes a copy of a particular version of a given software product or tool, such as via generator 160. In some implementations, the version of via generator 160 is based at least on the operating system and processor(s) used by client device 150. Via generator 160 includes an engine 164 that, when executed by processor 170, causes processor 170 to automatically generate vias in a layout mask representation of a signal route in a redistribution layer. The signal route of the redistribution layer is a signal route located between the integrated circuit and the printed circuit board. For example, the signal route of the redistribution layer is the signal route located between the micro bump contacting the pad of the integrated circuit and the through silicon via (TSV) of the silicon package substrate. The redistribution layer facilitates chip-to-chip bonding by eliminating the need for a set of input/output (I/O) pads to be wire-bonded to the package pins.

As previously described, organization center 110 is an infrastructure for vendors that produce one or more hardware products. An integrated circuit is one of many different types of integrated circuits being developed for production. With tens of thousands of metal layers potentially used to provide signal routes for redistribution layers, manually placing vias in these metal layers takes weeks or months. Via generator 160 performs this placement in a more efficient manner. Although the redistribution layer includes a control signal route and a data signal route, in an implementation, via generator 160 is a redistribution layer that provides either a power supply voltage reference level or a ground reference voltage level used by the integrated circuit. Provides automatic via creation for signal routes. To this end, via generator 160 uses attributes 166 provided by the user.

In one implementation, a user provides properties 166 to via generator 160 via graphical user interface (GUI) 162. In another implementation, a user provides properties 166 to via generator 160 via a text file or executable file written in one of a variety of scripting languages. In an implementation, when processor 170 executes the code of engine 164 of via generator 160, processor 170 automatically generates vias in the order of the sequence specified by attribute 166. Each sequence identifies a pair of adjacent metal layers in the redistribution layer. Via generator 160 further uses a copy of RDL mask layout data 132 and RDL netlist 134 to identify the placement of metal layers in the redistribution layer. Via generator 160 also uses DRC 136 to verify that the placement of vias does not violate design rules for the layout. The via generator 160 or other tool also performs a layout versus schematic (LVS) check. If the placement of vias passes the DRC and LVS checks, one or more copies of the updated version of RDL mask layout data 132 are stored in client device 150 and data storage 130. The semiconductor chip tape out process is then performed on the integrated circuit under development, and the semiconductor manufacturing process provides the hardware for the integrated circuit to be tested.

2, a generalized block diagram of a semiconductor package metal layer scheme 200 (or metal layer scheme 200) is shown that provides a signal route between an integrated circuit and a printed circuit board. As shown, the metal layer approach 200 utilizes a controlled collapse chip connection (C4) interconnection, also referred to as a flip chip interconnection. The two integrated circuits 210 and 212 have signal routes connected between them and the motherboard (or printed circuit board), which are not shown for ease of illustration. The interconnect may be connected to a vertical through-glass via formed in a silicon package substrate that is connected to a printed circuit board using bump pads. In addition to the signal route between the motherboard and integrated circuits 210 and 212 via interconnect 240, signal routes to and from integrated circuits 210 and 212 are routed through redistribution layer 230. In some implementations, metal layer approach 200 adds a separate interposer (not shown) between redistribution layer 230 and interconnect 240 (e.g., under-bump metallurgy (UBM)). Included as. In an implementation, the interposer includes through-silicon vias, while the redistribution layer 230 does not include TSVs. In another implementation, interposer and redistribution layer 230 each includes one or more TSVs. In another implementation, a separate interposer is not used, as shown in Figure 2.

Here, the integrated circuit is SoC (System on a Chip). As shown, one SOC is used for hardware products. However, other examples of integrated circuits are possible and contemplated, such as one or more of a CPU, GPU, multimedia engine, application specific integrated circuit (ASIC), digital signal processor (DSP), etc. Interconnect 240 provides a connection between multiple redistribution layers (RDLs) 1 through 4 and the package substrate and motherboard. In some implementations, it is common to have hundreds of UBM layers and C4 bumps. Additionally, four metal layers (RDL 1-4) are used in the redistribution layer 230, although in other implementations, different numbers of metal layers are used. Between adjacent metal layers (RDL 1-4) of redistribution layer 230 there are layers of vias labeled Via2 through Via4, which provide physical connections between adjacent layers of redistribution layer 230. The redistribution layer 230 also includes a via in the Via1 layer between the pin of the SMD pin layer and the metal layer (RDL1). As shown, the redistribution layer 230 further includes a via of the Via5 layer between the metal layer RDL4 and the interconnection 240.

SoC 210 may have signals routed to and from both other SOCs (not shown) and a motherboard (printed circuit board), at least via interconnect 240 . The signal is routed through the metal layers of redistribution layer 230, such as the metal layer designated redistribution layer 1 (RDL1) and the metal layer designated redistribution layer 4 (RDL4). These metal layers are also referred to as conductor 1 and conductor 4, respectively. In addition to the metal layers (RDL1 to RDL4) of the redistribution layer 230, signals are also routed through the pin and via layers (Via1 to Via5) of the surface mount device (SMD) pin layer. Although redistribution layer 230 includes a control signal route and a data signal route, the signal route shown here is one of the power supply voltage reference level and the ground reference voltage level used by SoC 210 and SoC 212. Wire the above. SoC 210 and SoC 212 may each use one or more power supply voltage reference levels and one or more ground reference voltage levels. In some cases, SoC 210 and SoC 212 each have tens of thousands of nodes that use pads 220 to receive a power supply voltage reference level and one or more ground reference levels. There are hundreds of UBMs for transmitting . Routing of these signals becomes complex. In some cases, layout mask data for signal routes within metal layers (RDL1 through RDL4) is already available, but manually placing vias in these metal layers takes weeks or months.

To make via placement more efficient, the processor's circuitry executes instructions in a software tool that follows an algorithm developed by a software programmer to automatically create vias based on attributes provided by the user. The tool, also referred to as the RDL automatic via generator (or automatic via generator), uses a copy of the RDL mask layout data and the RDL netlist to identify the placement of metal layers in the redistribution layer. The automatic via generator also uses properties supplied by the user. In various implementations, the automatic via generator takes into account design rule checks (eg, spacing, etc.). In some embodiments, these other tools perform DRC and LVS checks. After passing inspection, the semiconductor chip tapeout process is performed on the integrated circuit under development, and the semiconductor fabrication process provides the hardware for the integrated circuit to be tested.

3, a generalized block diagram of metal layer 300 is shown. As shown, the two horizontal signal routes of metal layer (RDL1) 302 are connected by a vertical signal route of metal layer (RDL2) 304. Cross sections of Side A and Side B are also provided to help view the three-dimensional layout. The metal layer of RDL1 (302) is physically connected to the metal layer of RDL2 (304) through via placement in the Via2 layer (306). Due to the width of the metal layer of RDL2 (304), a single row of two vias in Via2 layer (306) is placed. Therefore, each of the two metal layers (RDL1) 302 and the metal layer (RDL2) 304 is physically connected. In various implementations, these metal layers 302 and 304 provide a power supply voltage reference level or a ground reference voltage level used by the corresponding integrated circuit.

Although the orientations are described as horizontal and vertical, it is understood that the semiconductor package may rotate and the redistribution layer may rotate. Current orientation is used to describe the relationship between metal layers and vias. Here, the metal layer (RDL2) 304 is placed above the metal layer (RDL1) 302, so that the SoC or other integrated circuit is placed on the page of this diagram, while the UBM and silicon package substrate are placed outside the page of this diagram. is located. For this discussion, the integrated circuit is positioned on the page, although reverse orientations are possible and contemplated.

4, a generalized block diagram of metal layer 400 is shown. Materials and structures previously described are numbered identically. As shown, the two horizontal signal routes of metal layer (RDL1) 302 are connected by a vertical signal route of metal layer (RDL2) 304. Cross sections of Side A and Side B are also provided to help view the three-dimensional layout. The metal layer of RDL1 (302) is physically connected to the metal layer of RDL2 (304) through via placement in the Via2 layer (306). Due to the larger width of the metal layer of RDL2 (304), two rows of two vias of Via2 layer (306) are placed.

5, a generalized block diagram of metal layer 500 is shown. Materials and structures previously described are numbered identically. As shown, the two horizontal signal routes of metal layer (RDL1) 302 are connected by a vertical signal route of metal layer (RDL2) 304. Cross sections of Side A and Side B are also provided to help view the three-dimensional layout. The metal layer of RDL1 (302) is physically connected to the metal layer of RDL2 (304) through via placement in the Via2 layer (306). A cut in the top metal layer (RDL3) 502 shows the placement of a single row of two vias in the Via2 layer 306. Additionally, two horizontal signal routes in metal layer (RDL3) 502 are connected by the same vertical signal route in metal layer (RDL2) 304. Metal layer (RDL3) 502 is positioned over metal layer (RDL2) 304 using the previous orientation for metal layers 300-500 (FIGS. 3 and 4). Therefore, each of the two metal layers (RDL1) 302, the single metal layer (RDL2) 304, and the two metal layers (RDL3) 502 are physically connected.

In various implementations, these metal layers 302, 304, and 502 provide a power supply voltage reference level or a ground reference voltage level used by the corresponding integrated circuit. The metal layer of RDL3 (502) is physically connected to the metal layer of RDL2 (304) through via placement in the Via3 layer (504). Due to the width of the metal layer in RDL2 (304) and the area required for vias in Via2 layer (306), a single row of two vias in Via3 layer (504) is used by each of the metal layers in RDL3 (502). Note that the vias in the Via2 layer 306 and Via3 layer 504 have physical connections with only two adjacent layers, not three adjacent layers. In various implementations, design rule checking (DRC) does not allow a physical connection to the third metal layer. Therefore, as shown, the vias in Via2 layer 306 are placed between the metal layers of RDL1 (302) and RDL2 (304), but the vias in Via2 layer 306 are not physically connected to the metal layers of RDL3 (502). To be connected, they are not continuous in the vertical direction. Similarly, the vias in Via3 layer 504 are placed between the metal layers of RDL2 (304) and RDL3 (502), but the vias in Via3 layer (504) are vertical to physically connect with the metal layers of RDL1 (302). It is not continuous in direction. However, in other implementations, DRC allows the use of through-hole vias formed through three or more metal layers.

Note that in the above example illustrated in Figures 3-5, the metal overlap region is between the metal layers of the RDL and has a rectangular shape. However, in another example, the metal overlap region is between the fins of the surface mount device (SMD) fin layer and the metal layer of the RDL. It is possible and contemplated that the metal overlap area has a circular shape in these examples. In another example, the metal overlap region is between the metal layer of the RDL and the under-bump metallurgy (UBM) layer that provides the electrical connection to the C4 bump.

6, a generalized block diagram of a graphical user interface (GUI) 600 is shown. As shown, GUI 600 includes multiple selections to customize multiple attributes used for automatic via creation in the redistribution layer. The user can provide selection for multiple attributes using one or more of the provided dropdown menus, input boxes to receive text, checkboxes that change color to indicate selection, or other shapes. Box 602 allows the user to select a geographic region in the redistribution layer for automatic via creation. For example, users can draw a shape with boundaries that define areas for automatic via creation. Alternatively, the user can select an existing design outline.

In some implementations, a table is provided with multiple fields. Field 604 indicates the adjacent layer to be customized for automatic via creation. As shown, the first row represents the metal layer (RDL1) and the SMD fin layer. The Via1 layer is between these two layers (RDL1 and SMD pins). The second row represents the metal layer (RDL1) and the metal layer (RDL2). The Via2 layer is between these two metal layers (RDL1 and RDL2). The third and fourth rows follow the same convention for identifying via layers. The last row shows the UBM and metal layer (RDL4) physically connected to the C4 bump. The Via5 layer is between these two layers (RDL4 and UBM). Field 606 represents the via pad stack for each via layer. A via pad stack includes features that describe a single via definition or multiple via definitions, such as a metal layer at the end of the via opening(s) in a dielectric. The pad stack definition also describes the holes (via openings) in the redistribution layer used to create the vias. These characteristics include whether the hole is plated or not. Additionally, these characteristics indicate the size of the hole (diameter), the size of the finished hole, the size of the pads formed in the inner and outer layers, and the size of the gap around the hole. The user indicates the via pitch in field 608.

The field 610 describing via placement includes three subfields. The first subfield represents the reference metal. For example, the Via2 layer is between two metal layers (RDL1 and RDL2). The user selects one of these metal layers (RDL1 and RDL2) as the reference metal to be used to describe the placement of vias in the metal overlap region of the RDL1 and RDL2 layers. The user selects the starting point with the second subfield. The starting point refers to the selected reference metal and also indicates that the edges of the selected reference metal will be automatically via placed. As an example, briefly referring back to metal layer 500 (FIG. 5) for the Via2 layer, the user selects “top” as the reference metal to represent metal layer RDL2. The user selects “rail right edge” as the starting point, and the user selects “vertical” as the direction, which is the third subfield. The vertical and horizontal directions are used to determine the pad stack placement of multiple vias placed in the metal overlap area. Examples of placing multiple vias in metal overlap regions are provided in Figures 3-5.

In various implementations, one of the subfields of field 610 or another field of GUI 600 (not shown) includes an indication that allows the user to specify the hole type and the corresponding via type. For example, the user can determine whether the hole in the via is a through-hole via, a hole of multiple holes in a microvia stack, a hole in a blind microvia, a hole in a buried hole, or a hole in a copper-filled microvia. You can specify. In other implementations, selection of hole types and corresponding via types is not permitted by the user. Rather, the semiconductor fabrication process already defines the hole types and corresponding via types between the metal layers of the RDL. This information is provided by another file that is accessed by the RDL automatic via generator when generating vias based on properties provided by the user.

Note that in some implementations, a row of the table identifies one or more via layers that skip a metal layer. In one example, rows (not shown) represent metal layers (RDL2 and RDL4). One or more vias are between two metal layers (RDL2 and RDL4), but do not pass through the metal layer (RDL3). As previously explained, the hole types and corresponding via types between the metal layers of the RDL are either specified by the user or pre-specified by the semiconductor fabrication process. Other fields or other indicators indicate the absence of a metal layer (RDL3) in this particular overlapping region. Therefore, in this particular overlap region, only the dielectric exists without the metal of the metal layer (RDL3) between RDL2 and RDL4. In some implementations, one or more fields of the GUI 600 table include a cross-section definition of a via layer that identifies the thickness (depth) of a corresponding via between corresponding metal layers. The pad stack definition provides the diameter of the via as previously described. Additionally, in some implementations, fields in the GUI 600 table allow via stacking rules such as vias in the Via1 layer and Via3 layer to be placed (stacked) in the same vertically aligned overlap area, while Via2 layer has the same Indicates that it is not allowed to be placed in a vertically aligned overlapping area.

Field 620 indicates the sequence order to be used for automatic via creation in the redistribution layer. It is not necessary to traverse the via layers in a continuous adjacent manner. Users can customize the order of via layers used by the automatic via generator. Note that in some cases, the automatic via generator defaults to using the maximum number of vias in the Via1 layer to fit inside the pin area of the SMD pin layer while still satisfying the DRC using the pitch of the Via1 layer. In various implementations, the fins in the SMD fin layer are much larger than the vias in the Via1 layer.

Also, note that more than one via layer (one or more rows of the table) has multiple sequence numbers indicating that a repetition occurs for that particular via layer. For example, briefly referring back to metal layers 400-500 (FIGS. 4 and 5), the first pass of the Via2 layer is a single row of vias of the Via2 layer at the right edge of the vertical metal layer RDL2. Add only For the portion of the redistribution layer that also has metal layer RDL3 overlapping with metal layer RDL1 as shown in metal layer 500, placement of vias in layer Via2 has been completed. However, for the portion of the redistribution layer that does not have the metal layer RDL3 overlapping the metal layer RDL1 as shown in the metal layer 400, it is possible to add more vias of the Via2 layer.

Field 630 allows the user to indicate whether to allow DRC violations. For example, the user wants to stagger vias in two different layers, such as vias in the Via1 layer and Via3 layer. Therefore, more vias are installed in a specific area while still satisfying the DRC spacing in the same via layer. Field 630 also allows the user to indicate whether a report is generated by providing information about the results of automatic via generation using attributes provided in a number of fields of GUI 600.

Referring now to Figure 7, one embodiment of a method 700 for automatic via creation in a redistribution layer is shown. For illustrative purposes, the steps of this embodiment (and FIG. 8) are shown in sequential order. However, in other embodiments, some steps occur in a different order than shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are omitted.

The user selects properties to customize automatic via creation in the redistribution layer (block 702). In one implementation, a user provides properties to the automatic via generator through a graphical user interface (GUI). GUI 600 (Figure 6) is one example. In another implementation, a user provides properties to the automatic via generator through a text file or executable file written in one of a variety of scripting languages. The user initiates execution of the automatic via generator and the processor of the corresponding computing device performs automatic via generation in the redistribution layer based on the attributes (block 704). In one implementation, this automatic generation includes receiving properties such as reference metal identification, starting point, direction, and sequence. Additionally, overlapping areas are identified as described above. Based on this information, data is generated representing the placement of one or more vias between metal layers. Additionally, the properties may include pitch and size information for a given layer, which is used to determine spacing between vias. Additionally, as discussed above, in implementations, the automated process is configured to split the overlapping region in half and place vias both above and below the overlapping region. Subsequently, the user executes one or more tools to perform design rule checking (DRC) verification and layout versus schematic (LVS) verification (block 706).

Users determine whether the results of automatic via generation meet design requirements such as via redundancy measure and equivalent via resistance measure in specific regions of the redistribution layer. If the result does not meet the design requirements (“No” branch of condition block 708), control flow of method 700 returns to block 702 where the user selects an attribute. If the results meet the design requirements (“Yes” branch of condition block 708), the design of the semiconductor package is taped out and fabricated (block 710).

If a potential is not applied to the first node of the semiconductor package's integrated circuit (“No” branch of condition block 712), the semiconductor package waits until powered on (block 714). However, when a potential is applied to the first node to create a potential difference (“Yes” branch of condition block 710), the automatically created metal layers and vias in the redistribution layer carry current between the integrated circuit and the motherboard. Do (block 716).

8, one embodiment of a method 800 for automatic via creation in a redistribution layer is shown. The user defines the properties of the automatic via generator to be used for automatic via creation in the redistribution layer. In one implementation, a user provides properties to the automatic via generator through a graphical user interface (GUI). GUI 600 (FIG. 6). In another implementation, a user provides properties to the automatic via generator through a text file or executable file written in one of a variety of scripting languages. When the processor executes the instructions of the automatic via generator, the processor defines a pad at the distal end of the redistribution layer (block 802). For example, the user defines the pitch to be used inside the pad. In one example, the user defines the pitch of vias in the Via1 layer to connect to pins of the SMD pin layer. The user selects the pitch both to satisfy existing DRC rules and to maximize the number of vias in the Via1 layer that are physically connected to corresponding pins in the SMD pin layer. Based on the properties entered by the user, the processor defines the pins of the SMD pin layer at the top of the redistribution layer stack and the vias of the Via5 layer at the bottom of the redistribution layer stack, where the top and bottom are oriented. represents.

The processor calculates the metal overlap area (block 804). An example of a metal overlap region between metal layers RDL1 and RDL2 is shown in metal layers 300-500 (FIGS. 3-5). An example of a metal overlap region between metal layers RDL2 and RDL3 is shown in metal layer 500 (FIG. 5). In another example, the processor calculates the metal overlap area between the pins of the SMD pin layer and the metal layer of the RDL. In another example, the processor calculates the metal overlap area between the metal layer of the RDL and the under-bump metallurgy (UBM) layer that provides the electrical connection to the C4 bump. The shape of the metal overlap area is square, rectangular, or circular based on the top and bottom layers that define the metal overlap area. In some implementations, based on the received attributes, the processor splits the overlap region in half such that the via layer is placed both above and below the overlap region. An example of this type of via placement is shown in metal layer 500 (Figure 5). Based on the properties indicating the reference metal, starting point, and direction, the processor places vias of different via layer types (e.g., Via2, Via3) in the overlapping region. In some implementations, if the top (top) via is already in place in the divided region, the bottom (bottom) via is placed in the other half. If the overlap area of two adjacent layers is not in the same location, the overlap area is fully utilized by the bottom via, and vice versa (for example, RDL1 and RDL3 are not in the same plane). This approach can be used when DRC constraints do not allow stacking of vias.

The processor creates a via based on the indicated sequence (block 806). The displayed sequence is assigned to the attributes received from the user. The sequence order determines which via layer will be used to initiate automatic via creation and which each subsequent via layer will be selected for further automatic via creation. Vias are placed based on the size and pitch corresponding to the currently selected via layer to satisfy the DRC rules. Additionally, the processor does not change the metal layer dimensions of the signal root. If multiple sequences for a given via layer are specified in the received attribute, the processor places additional vias in the via layer if possible. In some cases via redundancy already exists, but the automatic via generator continues to increase the via count when possible. The processor generates a report (block 808). The processor maintains log files during automatic via creation and uses the corresponding information to provide summarized results in a report. In various implementations, the processor creates a file located at a known destination.

9, one implementation of a computing system 900 is shown that utilizes a redistribution layer with automatically placed vias. Computing system 900 utilizes a chip package 940 that includes automatically created vias in a redistribution layer. Chip package 940 uses one of a Ball Grid Array (BGA) surface mount package, a Chip Scale Package (CSP), and a System in Package (SiP) that communicates with other components on a motherboard (or printed circuit board). . In an implementation, computing system 900 includes processor 910 and memory 930 in a chip package 940. In another implementation, only one of processor 910 and memory 930 is included in chip package 940. Interfaces such as memory controllers, buses or communication fabrics, one or more phase locked loops (PLLs) and other clock generation circuitry, power management units, etc. are not shown for ease of illustration. Additionally, in the illustrated implementation, chip package 940 is coupled to disk memory 954 via memory bus 950, an input/output (I/O) controller, and bus 952.

In other implementations, it is understood that computing system 900 includes one or more other processors of the same or different type as processor 910, one or more peripheral devices, a network interface, one or more other memory devices, etc. In some implementations, the functionality of computing system 900 is integrated into a system on a chip (SoC). In another implementation, the functionality of computing system 900 is integrated into a peripheral card inserted into the motherboard. Computing system 900 is used in any of a variety of computing devices, such as desktop computers, tablet computers, laptops, smartphones, smartwatches, game consoles, personal assistant devices, and the like.

The processor 910 includes hardware such as circuitry. In various implementations, processor 910 includes one or more processing units. In some implementations, each processing unit includes one or more processor cores capable of general-purpose data processing, and an associated cache memory subsystem. In this implementation, processor 910 is a central processing unit (CPU). In another implementation, the processing cores are computing units with a highly parallel data microarchitecture, each having multiple parallel execution lanes and associated data storage buffers. In this implementation, the processor 910 is a graphics processing unit (GPU), a digital signal processor (DSP), or the like.

In some implementations, memory 930 includes one of various types of dynamic random access memory (DRAM). Memory 930 stores at least a portion of an operating system (OS) 932, one or more applications represented by code 934, and at least source data 936. In various implementations, memory 930 stores copies of these software components 932, 934, and 936 with copies of the originals stored in disk memory 954. Memory 930 may also store intermediate and final result data generated by processor 910 when executing certain applications of code 934.

In various implementations, off-chip disk memory 954 includes one or more hard disk drives (HDDs) and solid-state disks (SSDs) that include flash memory banks. I/O controller and bus 952 supports communication protocols with off-chip disk memory 954. Although a single operating system 932 and a single instance of code 934 and source data 936 are shown, in other implementations, different numbers of such software components may be stored in memory 930 and disk memory 954. do. Operating system 932 includes instructions to initiate booting of processor 910, assign tasks to hardware circuitry, manage resources of computing system 900, and host one or more virtual environments.

Note that one or more of the embodiments described above include software. In such embodiments, program instructions implementing the methods and/or mechanisms are transmitted or stored in a computer-readable medium. Many types of media configured to store program instructions are available and include hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROM (PROM), random access memory (RAM), and various other forms of volatile or non-volatile media. Includes volatile storage. Generally speaking, computer-accessible storage media includes any storage media that can be accessed by a computer during use to provide instructions and/or data to the computer. For example, a computer-accessible storage medium is any storage medium, such as magnetic or optical media, such as disks (stationary or removable), tape, CD-ROM or DVD-ROM, CD-R, CD-RW, DVD-R. , DVD-RW or Blu-ray. Storage media can be RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low-power DDR (LPDDR2, etc.), SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc. ), ROM, flash memory, non-volatile memory (e.g., flash memory) accessible through a peripheral interface such as a USB (Universal Serial Bus) interface, and the like. The storage medium may be MEMS (MEMS). Microelectromechanical Systems), and storage media accessible through communication media such as networks and/or wireless links.

Additionally, in various embodiments, program instructions are register transfers or operation-level descriptions of hardware functions in a high-level programming language such as C, a design language (HDL) such as Verilog, VHDL, or a database format such as the GDS II stream format (GDSII). Includes level (RTL) description. In some cases, the descriptions are read with a synthesis tool that synthesizes the descriptions to generate a netlist containing the gate list of the synthesis library. The netlist also contains a set of gates that represent the functionality of the hardware containing the system. The netlist is then placed and routed to create a data set that describes the geometry to be applied to the mask. The mask is then used in various semiconductor fabrication steps to create the semiconductor circuit or circuits corresponding to the system. Alternatively, the instructions on the computer accessible storage medium are a netlist (with or without a synthesis library) or a data set, as desired. Additionally, the instructions are utilized for emulation purposes by hardware-based type emulators from such vendors as Cadence®, EVE®, and Mentor Graphics®.

Although the above embodiments have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be construed to include all such variations and modifications.

Claims (20)

In the processor,
comprising circuitry, wherein the circuitry includes:
receive a plurality of attributes corresponding to a plurality of via arrangements between adjacent metal layers among the plurality of metal layers;
The processor is configured to generate data representative of placement of the plurality of vias between adjacent metal layers based at least in part on the nature and identification of overlapping areas of the adjacent metal layers. The processor of claim 1, wherein the attributes include one or more of reference metal identification, starting point, direction, and sequence. 3. The processor of claim 2, wherein the circuitry is further configured to determine placement of the via based at least in part on the size and pitch of the currently selected via layer. 4. The processor of claim 3, wherein the circuitry is further configured to determine a spacing between the plurality of vias disposed in the overlapping region based at least in part on the size and pitch. The processor of claim 1, wherein the circuitry is further configured to split the overlapping area in half and place vias both above and below the overlapping area. The processor of claim 1, wherein the circuitry is further configured to generate the placement of the plurality of vias in an order of sequences specified by the plurality of attributes, each sequence identifying a pair of metal layers. The processor of claim 1, wherein the plurality of levels of metal layers are a redistribution layer between an integrated circuit and a printed circuit board. In the method,
Receiving a plurality of attributes corresponding to a plurality of via placements between adjacent metal layers of the plurality of metal layers; and
A method comprising generating data representative of placement of the plurality of vias between adjacent metal layers based at least in part on the nature and identification of overlapping areas of the adjacent metal layers. 9. The method of claim 8, wherein the attributes include one or more of reference metal identification, starting point, direction, and sequence. 10. The method of claim 9, further comprising determining placement of the via based at least in part on the size and pitch of the currently selected via layer. 9. The method of claim 8, further comprising generating the placement of the plurality of vias in an order of sequences specified by the plurality of attributes, each sequence identifying a pair of metal layers. 12. The method of claim 11, wherein the plurality of metal layer levels are a redistribution layer between an integrated circuit and a printed circuit board. 12. The method of claim 11, wherein the one or more signal types include one or more of a power supply voltage reference level or a ground reference voltage level used by the integrated circuit. 12. The method of claim 11, further comprising receiving the plurality of properties via a graphical user interface. A non-transitory storage medium configured to store program instructions, wherein the program instructions include:
receive data including a plurality of attributes corresponding to a plurality of via placements between adjacent metal layers among the plurality of metal layers;
A non-transitory storage medium executable to generate data representative of placement of the plurality of vias between adjacent metal layers based at least in part on the nature and identification of overlapping areas of the adjacent metal layers. 16. The non-transitory storage medium of claim 15, wherein the attributes include one or more of reference metal identification, starting point, direction, and sequence. 17. The non-transitory storage medium of claim 16, wherein the program instructions are executable to determine placement of the via based at least in part on the size and pitch of the currently selected via layer. 18. The non-transitory storage medium of claim 17, wherein the program instructions are executable to determine spacing between a plurality of vias disposed in the overlapping region based at least in part on the size and pitch. 16. The non-transitory storage medium of claim 15, wherein the program instructions are executable to split the overlapping area in half and place vias both above and below the overlapping area. 16. The non-transitory storage of claim 15, wherein the program instructions are executable to generate the arrangement of the plurality of vias in an order of sequences specified by the plurality of attributes, each sequence identifying a pair of metal layers. media.

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