TWI312927B - Method for setting power management status of device and power-saving method of the same - Google Patents

Description

1312927 • Nine, invention description: * [Technical jaw region to which the invention belongs] The present invention generally relates to a device power management state setting method in a computer system and a power consumption saving method thereof. More specifically, it relates to an advanced configuration and power supply interface. (ACPI) Power Management Standard Computer System 'Method of setting the low power P state of the device according to the relationship between the processor and the device controller and the power saving method of the device. [First Technology] _ Computer system is one of the most important hardware infrastructures in the modern information society. In addition to the pursuit of performance, modern computer systems must also pay attention to the reduction of energy consumption. Therefore, modern computer manufacturers have also reduced energy consumption as one of the focuses of computer system development. • Southern configuration and power interface (Advanced Configuration and

Power interface (ACPI) is a kind of power management standard jointly developed by Yangdale, Microsoft and Toshiba. Its intention is to let the system, not BI〇s, fully control the electricity. Power saving. As a bridge between the BIOS and the operating system, the Acpi sets a number of different power/performance states for different objects, such as for all systems: all system states GX, sleep state 1312927 SX for global sleep state G1, for GO; } In the large state of the central processing unit (c state CX, and the state of failure for the device. Where 乂 is the number of the original original 2 '3, etc., representing different power / performance states, when, 0 1 'normal working state. , correcting the processing in which ACPI will be in all system states (9) = under-state CX is defined as the startup state (execution instruction) or sleep port = order::CX includes C0, cl, C2, C3...CnQC (^, rational ☆ The power-on state of the execution command is awake. Cl to C η is the sleep state of different levels of the processor, energy saving _ C1, C2, C3, C4, 曰 狄 曰 曰丨 曰丨 曰丨 序 序疋C4. The processor does not execute any instructions while the processor is in a sleep state. Each processor sleep state has a delay time to enter and exit the corresponding state 'power saving for a sleep state that typically has a long entry/exit delay time Cheng It is large. Further, in the C0 state, but also through the ACn Cloth I Lang flow state (throttling state) '' COt and by turn, find a plurality of performance states (P state) to change the performance of the processor.

AcpI defines the device power saving state as do, Dl, D2, and D3. The DO is the power-on and running state of the device. The power of the device is completely removed in the D3 state. Therefore, the next time the power is supplied again, the operating system needs to be set again. D1 and D2 are energy-saving states, and the D2 state is more energy-efficient than the pi state. The D1 and D2 states are determined by the device itself, and some devices cannot enter the D1 and D2 states, but all devices can enter the d3 state. (The above can be found in the ACPI Technical Specifications). 1312927 Typically, when the processor goes to sleep, the device is in normal operation and can perform its work independently. However, in most cases the peripherals have no work to handle but wait for the processor to wake up', which undoubtedly increases the energy consumption of the computer system. Therefore, we wish to provide a mechanism for the device to enter a sleep state or a throttling state after the processor has entered a sleep state to further save power in the computer system. ~All [Invention] The purpose of this month is to provide a method for setting the power management status of the device according to the relationship between the processor and the controller, and a power saving method for the power consumption, which (4) is in compliance with the advanced configuration and (Advanced Configuration and Power Interface; ACPl^^ = management standard computer system reduces power during normal state: According to an aspect of the invention, a method for providing a device_tube setting is applied to have a power supply f Unit (pM ^ computer system, which includes the steps of: providing -PMU module, the second: the group can obtain a plurality of different electrical states of the computer system processor, and according to the obtained processing in the PMU module" According to an aspect of the present invention, the power management state of the Lvyuan management state setting device provides a device power consumption 8 1312927

The method is applied to a power management unit (PMU) module. The method includes the following steps: the hetero-PMU touches the pMU to obtain a plurality of different power management states of the computer system processor, corresponding to different power management of the processor. The state of the corresponding power management state of the state setting device, and the provision of "device control", check whether there is a power failure status, and if so, the control device enters the corresponding device power management state. According to another aspect of the present invention, a method for saving power consumption of a device is applied to a computer system conforming to the ACPI specification, which includes the steps of: identifying the source management state of the J-resource, and according to the identified power source. The management management state is the power management state corresponding to the power management state of the control device. Through the above method, the device of the computer system can automatically enter the corresponding power management state according to the identified identification number of the PMU module corresponding to the different power management state settings of the processor, thereby reducing the power consumption of the computer system during normal operation. [Embodiment] According to the (Advanced Configuration and Power Interface; ACPI) technical specification, the power management state of the CPU (Cpu) includes: a normal operating state C〇 and sleep states ci, C2, C3, and C4. When the CPU temperature is too high, the CPU can enter the Throttling state COt to reduce the power consumption of the CPU. ACP][The power supply 1312927 is also defined as the device status D〇, d Bu D2 and D3, where D0 helmet D3 and TD〇 are in normal operation state, and 4: HD1*D2_ can be customized. In the case of p>4—(10) or in the sleep state, the device is in the computer system platform that can only wait for the CPU to wake up to the management standard after working. Usually, the ACPI power supply CPTT is provided in the south bridge chipset.

a power management unit that is connected to the circuit of the device (P

tfMU knows where to enter the alpha state: his pen source management state, ie co, C0t, C2, cuc4 state. 1 The device of the electric (four) system using the method of the invention can also enter the corresponding provincial state, that is, the D1 and D2 states according to the signals of different power management states in which the CPU of the PMU module is located, thereby further reducing the computer system. The overall energy consumption. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Referring to the first figure, it is a schematic diagram of a power management state method for a setting device of a PMU module for a south bridge wafer or a north-south bridge integrated chip of a computer system according to an embodiment of the present invention. The PMU module first determines whether the CPU is in a normal operation, and if it is not, then the power management state method of the setting device of the present invention is started. In the PMU module, in step S10, it is checked whether the CPU is in the COt state. If yes, step S5 is performed to set the PMU_D〇t signal to cause the device controller to control the device to enter the first power state. If not, proceed to step S20. In the present invention, the first power state of the device is defined as the DOt state defined by the ACPI specification. Referring to steps S501 and S502 'after setting PMUj' 〇t signal, when detecting that the CPU is transferred to the C0 state of 10 1312927 active operation, the PMU module will clear the PMU_DOt signal and cause the device controller to control the device to exit. - Power status, otherwise -^ is in special (four). Normally, when the CPU's Wenlin's setting value %' CPU will be transferred from the throttle state CGt state to the normal operating state c〇. < In step S20, the pMU module checks if the CPU is in the C2 state or the C3 state. If the CPU is in the C2 state or the c3 state, the PMUJ)1 signal of the mu module is set in step S60 to enter the second power state by the device control device. In the present invention, the second power state of the device is the D1 state of the ACH specification (4). = 'Go to step S90, the pMU module determines whether the cpu is about to leave: month; 』C2 or C3 state 'if ', then step S120 is executed to clear PMU_D1 - money to cause the device controller control device to exit the m state, otherwise = Waiting state. If the result in step S2 is not in any of the states, the process proceeds to step S30. In step S30, the hall module checks whether the cpu is in the C4 state, and if so, sets the PMU D2 signal of the PMU module in step S7, so that the device controller controls the skirt to enter the second power state. In the present invention, the third power state of the device/device is the D2 state defined by the ACPI specification. Then, the process proceeds to step sl, and it is judged whether the coffee is awakened by the C4, and if so, the step §13〇 is executed, and the signal of the still-d2 is cleared and ended, otherwise it is in a waiting state. The device controller exits the D2 state after checking that the PMU-D2 signal is cleared. If the PMU module detects that the CPU is not in the state, then perform step (10) to clear the pMU-D〇t, pMU-m, pMu-signals of the PMU module and 11 1312927 ends. - wherein, after the pMu_m, p_ melon signals are set in steps S60 and S70, only the CPU is taken from C2, c -

If the occurrence of the (4) awakening event occurs, the PMU-m and PMU numbers of the PMU module are cleared, and the _ is in a special state. In this way, the CPU and the device can be controlled to wake up by waking up which processing event to wake up, thereby exiting the current power management state. ^ See the "-" as a representation of a device power saving method for a device controller of a computer system in accordance with an embodiment of the present invention. When the device completes its work in step S1_, it proceeds to S100. In the device controller, in step S200, the device controller checks whether the U-module is set to the UI_D0t signal, and if so, executes step S500 to cause the device controller to control the device to enter the (10) state. When the split controller control device enters the DOt state, the action timer in the device (behavi〇r operates with a larger set value _. When the action timer is in the count state, the peripheral device does not work, and when the action timer Timeout, the peripheral device works - the predetermined time 'and resets the action timer to the state of the material. In the D 01 state, the device controller controls the device to operate in an intermittent throttling state. , thereby reducing the working time of the device. Then 'go to step S510, waiting for the PMU-D (clearing of the signal). When it is known in step S510 that the PMU_D〇t signal is cleared, step S520 is performed to enable the device to control If the PMU-D〇t signal is not set, the process proceeds to step S3. 12 1312927 Τ P=: If the = check_module is set to the person m (four) 22, the binding step S600, The control device is placed into a large sleep type. After the device is controlled and the control device is set to enter m, the device controller stops the timer of the device, and stops the power consumption of the device, and the device is in the form of m== less than Power consumption in the state of bile in

Whether the signal is cleared, if yes, if the controller is not equipped with the TM signal, then the step is leaked, and it is checked whether the PMU module has set the curry 2 'Right 疋", then step S700 is executed to enable the device controller to control Device-like evil. In particular, in the present invention, when the device controller controls the f-set sleep state, the device controller stops the timing factory of the device, and the pLL in the device (Phased system L〇) 〇P) Phase-locked loop circuit. Obviously, the power consumption of the device in the see state is less than the power consumption in the D1 state. In the case of the step, the device controller mu-D2 signal is cleared, and if so, the CPU step S72G' is executed to cause the device controller control device to exit the D2 sleep state and end 'otherwise' or otherwise wait. If the pMU-D2 signal is not set, it ends and performs other work normally. The specific settings of the DOt and Db D2 states in steps S500, S600, and S700 are merely examples, and each device can refer to the PMU-DX signal, that is, according to the management state of the CPU, its own and upper 13 1312927 are defined. Different specific DOt, D1, D2 states are described. After the device completes normal operation, the device controller controls the device to stop some or all of its clock signals or stop the operation of its PLL circuit according to the corresponding signal of the PMU module and monitors the clearing of the PMU_D0t, PMU-D1, and PMU-D2 signals. . The device described in the above system may be a peripheral device connected by a bus, such as USB, SATA, IDE, or PCIE.

According to the method shown in the above two embodiments of the present invention, since the pMu module can recognize the power management state in which the CPU is located and can set the corresponding power management state of the skirt according to the different power management states of the obtained CPU. The identification signal, f CPU enters sleep or section (four) large = when the device controller can complete the operation, the device can control the device to enter the corresponding sleep or throttle state according to the identification signal given by the PMU module. And the CPU and the device control device can be woken up by waking up the processing event of the CPU, thereby causing the device to exit the current power management state. The degree of sleep or throttling of the silk can be set according to whether the CPU is not __ or the recording state. Such a result can be: positive; at different levels of sleep or throttling to reduce the power consumption of the device, while further reducing the power consumption of the system during normal operation. The present invention has been disclosed in the preferred embodiments as described above, and it is intended that the scope of the present invention, the scope of the present invention, and the scope of the present invention are within the scope of the scope of the present invention. [Simplified description of the description] 14 1312927 This case can be further understood by the following drawings and detailed description: The first figure is a computer system according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a device power consumption saving method for a device controller of a computer system according to an embodiment of the present invention. FIG. [Main component symbol description]

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Claims (1)

1312927 X. Patent application scope: 1. A device power management state setting method is applied to a computer system having a power management unit (PMU) module, which comprises the following steps: ^ for a PMU module, the PMU The module can obtain a plurality of different power management states of the computer system processing person; and f the corresponding power management state of the PMU module according to different power management modes of the obtained processor Identification signal. 2. The method for setting the power management state of the device according to Item 1 of the patent scope further includes the following steps: / After the identification signal of the power management state of the device is set in the =PMU, when the processing shifts its power management state Clear the identification signal of the set power management status of the device. 3 The power management state setting state of the device as described in the first item of the patent range is 'go'. The power management state of the processor available to the ^PMU module includes the cot, C2, C3, and C4 states. The method for setting the power management status of the device described in the third paragraph of the patent scope includes the following steps: The PMU group of the Tianhai computer knows that the PMU DOt signal is set when the processor is in the cot state, and the ga H# _ shame The clothes are placed according to the PMUJDOt signal, and when the PMU掇4TM is in the first state, and the KNOW processor is in the C2 or C3 state, the PMU D1 signal is set, and the twisting is performed on the NMU. The PMU_D1 signal enters a second power state; and when the PMU 桓钿Α, if the HOLD controller is in the C4 state, the 16 1312927 PMU-D4 signal is set according to the PMU- Enter a second power state. . <1. The method of setting a power management state of a device according to claim 1, wherein the power management state of the device is included. A device power saving method for a computer system having an electrical unit (PMU) module, comprising the steps of: providing a PMU module, the PMU module obtaining the a plurality of different power management state dimensions of the computer system processor, corresponding to the identification signals of the respective power management states of the different power management state setting devices of the processor; and providing a device controller to check whether the The power management state identification signal 'if any', the control device enters the corresponding device power management state, and can be used. 7. The device power consumption saving method according to claim 6, wherein the PMU module can obtain processing The power management state of the device includes a pan, c2, C3, and C4 state. 8. The device power saving method according to claim 7, wherein the method further includes the following steps: when the PMU module knows that the processor is in the COt In the state, the PMU-DOt signal is set, and the device enters the first power state according to the PMU-D〇t signal; when the PMU module knows that the processor is in the C2 or C3 state, the PMU_D is set. 1 signal, the device enters the second power state according to the PMU-D1 signal; and when the PMU module knows that the processor is in the C4 state, the 1312927 pMU~D4 signal is set, and the device enters the first source according to the PMUJD4 signal. The power consumption saving method of the device according to claim 8, wherein the second power state of the device saves more power than the first power state, and the third power state ratio is The second power state saves more power. The device power saving method as described in claim 6, wherein the power management state of the device includes DOt, D1, and D2 states. The device power saving method according to item 8, wherein the system device is a USB, SATA, IDE, PCIE computer peripheral device. The power consumption saving method of the device is applied to meet the advanced configuration and power supply (ACPI) ) - the computer system, which includes the following steps: Screening the power management status of the processor; and crying 2 according to the _ job wire ^ wire, difficult to continue into the Lu Li ", the source management state corresponding to the power management shape At the same time, as described in item 12 of the patent application scope, the method of identifying the power consumption of the 帝 饰 & amp amp amp amp 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一14. As defined in the patent application, the following steps are included in the thirteenth patent application: k is the power consumption of the clothing, and when the processor is in the C_ state, the control device enters the first processor and is in the C3 state. Strong power supply, state; and / heart, control device into the second power field processing state is in (^4 state - 15 · If the application of the dung brake system into the third power state. The device power saving method of claim 14, wherein the second power state described in 18 1312927 saves more power than the first power state, and the third power state is lower than the second power source The state saves more power. 19