1312557 98-3-16 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種微影製程(Photolithography)，且 特別是有關於一種應用於罩幕式唯讀記憶體編碼佈植 (Code Implantation)之微影製程。 【先前技術】 一般罩幕式唯讀記憶體的結構包括數條位元線（Bit Line，BL)以及橫跨於位元線上之數條多晶矽字元線(Word Line，WL)。而位於字元線下方以及兩相鄰位元線之間的區 域則是記憶胞之通道區。對某些罩幕式唯讀記憶體而言， 其程式化之方法係利用於通道中植入離子與否，來儲存資 料「〇」或「1」。而此種將離子植入於特定的通道區域之製 程又稱爲編碼佈植製程。 通常罩幕式唯讀記憶體之編碼佈植製程，係首先利用 一光罩將形成於基底上之光阻層圖案化，而暴露欲編碼之 通道區。接著，再以此圖案化之光阻層爲罩幕進行一離子 植入製程，以將離子植入於預定編碼之通道域中。然而， 罩幕式唯讀記憶體之編碼佈植製程中用來作爲編碼罩幕的 光罩，通常會因電路設計之需求而在同一光罩上形成單一 (Isolated)圖案區與密集(Dense)圖案區。然而，在進行圖案 轉移之曝光步驟時，由於單一圖案區之曝光的光強度較密 集圖案區之曝光的光強度爲強，因此容易使密集圖案區與 單一圖案區中之曝光圖案因爲光學鄰近效應（Optical Proximity Effect，ΟΡΕ)，而使關鍵尺寸產生偏差。如此， 4 1312557 98-3-16 將會使罩幕式唯讀記憶體在進行通道離子植入步驟時，導 致離子植入區塊的位置發生對不準（Misalignment)的現 象，進而造成唯讀記憶體記憶胞內的資料錯誤，影響記憶 體的操作性能，使產品的可靠性降低。 習知方法中，爲了解決罩幕式唯讀記憶體之編碼罩幕 的密集圖案區與單一圖案區之曝光圖案的關鍵尺寸不一致 之問題，大多是利用光學鄰近校正法（Optical Proximity Correction，OPC)或是相移式光罩(Phase Shift Mask，PSM) 技術等等。其中，光學鄰近校正法是利用輔助圖案之設計 以消除鄰近效應所造成的關鍵尺寸偏差現象。然而，此種 方式必須設計具有特殊圖案之光罩。因此，其除了光罩製 作較爲費時之外，更提高了製造光罩的困難度與製造成 本。此外，在光罩製造完成之後，要進行光罩圖案之缺陷 改良(Debug)也極爲不易。 【發明内容】 因此，本發明的目的就是在提供一種應用於罩幕式唯 讀記憶體編碼佈植之微影製程，以使其能同時在記憶胞陣 列的拾集圖案區與單一圖案區中形成相同尺寸之開口，避 免關鍵尺寸產生偏差。 本發明的另一目的是提供一種微影製程，在不需光學 鄰近校正法以及相移式光罩技術之前提下，便能避免關鍵 尺寸產生偏差。 本發明提出一種應用於罩幕式唯讀記憶體編碼佈植之 微影製程’其係首先提供一基底，其中基底上已形成有呈 4 ,1312557 98-3-16 陣列排列之複數個記憶胞。接著，在基底上形成一光阻層， 覆蓋住記憶胞。之後，將一光罩設置在光阻層之上方，且 此光罩上具有複數個編碼開口與複數個擬開口，其中光罩 上之編碼開口係封應於一預定編碼佈植之通道區，而光罩 上之擬開口係對應於其餘預定不編碼佈植之通道區。在 此，擬開口之尺寸係小於一臨界尺寸，以使擬開口在後續 微影製程中無法轉移至光阻層上。在本發明中，擬開口之 尺寸係小於0.12微米，較佳的是小於〇.〇9微米，而編碼開 口之尺寸較佳的是0.18微米至0.20微米。繼之，進行—微 影製程，以將光罩上之編碼開口轉移至光阻層上。在此微 影製程中所使用之一曝光光源係爲一波長爲248nm之光 源。在進行微影製程而將光阻層圖案化之後，便可直接利 用此圖案化之光阻層做爲一編碼罩幕層進行一編碼佈植步 驟，以在預定編碼佈植之通道區中植入一編碼離子，而完 成一罩幕式唯讀記憶體之編碼佈植製程。 本發明提出一種微影製程，其係首先在一基底上形成 一光阻層。之後，將一光罩設置在光阻層之上方，且此光 罩上具有複數個第一開口與複數個第二開口，其中光罩上 之第一開口係對應於一預定成像區，而光罩上之第二開口 係對應於一預定不成像區。在此，第二開口之尺寸係小於 一臨界尺寸’以使第二開口在後續微影製程中無法轉移至 光阻層上。在本發明中，第二開口之尺寸係小於0.12微米， 較佳的是小於0.09微米，而第一開口之尺寸較佳的是0.18 微米至〇.2〇微米。繼之，進行一微影製程，以將光罩上之 5 > 1312557 98-3-16 第一開口轉移至光阻層上。在此微影製程中所使用之一曝 光光源係爲一波長爲248nm之光源。在進行微影製程而將 光阻層圖案化之後，便可直接利用此圖案化之光阻層作爲 一蝕刻罩幕或者是一離子植入罩幕，以在基底之特定區域 中蝕刻出開口，或是在基底之特定區域中植入離子。 本發明之微影製程，由於其係利用於光罩上設計均勻 分佈的開口，並將對應於預定不成像區之開口作小，而僅 讓光阻層上預定成像區之處能順利成像。如此一來，藉由 均勻分佈的開口便能避免曝光製程因鄰近效應而會產生有 單一圖案區與密集圖案區之關鍵尺寸偏差之問題。 本發明之應用於罩幕式唯讀記憶體編碼佈植之微影製 程’由於在圖案化編碼罩幕層時不需使用光學鄰近校正法 或相移式光罩技術，即可避免單一圖案區與密集圖案區之 關鍵尺寸產生偏差，因此可大幅降低元件之製造成本。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 第1A圖至第1D圖所示’其繪示爲依照本發明一較佳 實施例之罩幕式唯讀記憶體之編碼佈植製程之流程剖面示 意圖。 請參照第1A圖’一罩幕式唯讀記憶體係由複數個陣列 排列之記憶胞所構成，其包括配置在基底100.中之複數條 埋入式位元線102’以及橫跨於埋入式位元線1〇2上方之複 數條多晶砂字元線108。其中，字元線1〇8與埋入式位元線 6 1312557 98-3-16 102以及基底100之間，係藉由一絕緣結構106以及一閘氧 化層104而電性隔離。其中，位於字元線ι〇8下方且在兩 相鄰埋入式位元線102之間之區域係爲記憶胞之通道區。 緊接著，利用一編碼佈植製程以將此罩幕式唯讀記憶 體程式化。其詳細說明如下。 請參照第1B圖，在基底100上方形成一光阻層110， 覆蓋住字元線108。之後，將一光罩200設置在光阻層110 之上方。在本發明中，此光罩200上具有複數個編碼開口 202與複數個擬開口 204。其中，光罩200上之編碼開口 202 係對應於一預定編碼佈植之通道區120,而光罩200上之擬 開口 204係對應於其他預定不編碼佈植之通道區130。請同 時篸照第2圖，其係爲光罩200之上視圖。 在光罩200上具有複數個編碼開口 202與複數個擬開 口 204。其中，擬開口 204之尺寸係小於一臨界尺寸，以使 擬開口 204在後續微影製程中無法轉移至光阻層110上。 在本實施例中，擬開口 204之尺寸較佳的是小於0.12微米， 更佳的是小於〇.〇9微米。而編碼開口 202之尺寸例如是介 於0.22微米至0.26微米之間，較佳的是介於0.18微米至 0.20微米。 然後，請參照第1C圖，進行一曝光製程206並緊接著 進行一顯影製程，以將光罩200上之編碼開口 2〇2轉移至 光阻層11〇上。此曝光製程206之曝光光源波長例如是介 於230nm至270nm微米之間。在本實施例中，在曝光製程 206所使用之一曝光光源係爲一波長爲248nm之光源。 1312557 98-3-16 値得注意的是，在本發明中，所使用之光阻層110可 依據光阻材質之Dill照射參數而選擇適合的光阻劑，以使 其在曝光製程206過程中，對應於光罩200上之擬開口 204 處之光阻層110所吸收之能量不足而無法成像，並且使對 應於光罩200上之編碼開口 202處之光阻層110所吸收之 能量足夠而能夠成像。 在本實施例中，由於光罩200上之擬開口 204之尺寸 係小於0.12微米，因此在使用248nm光源的曝光製程206 中因曝光解析度之限制，擬開口 204並不會被轉移至光阻 層110上。換言之，由於擬開口 204之尺寸太小，大部分 通過擬開口 204的光線都會散射掉。而且，也由於擬開口 204之面積太小，因此光線通過擬開口 204而到達光阻層 110的能量並不足夠，因此對應有擬開口 204處之光阻層 110並不會成像，如此一來，在後續顯影製程之後對應有擬 開口 204處之光阻層110就不會形成有開口。 同理，由於編碼開口 202之尺寸足夠大，因此通過編 碼開口 202之光線而到達光阻層110之能量足夠，以使對 應有編碼開口 202處之光阻層110可以順利成像，如此一 來，在後續顯影製程之後對應有編碼開口 202處之光阻層 110便會形成有開口。 特別値得一提的是，本發明之光罩200除了具有編碼 開口 202之外，在光罩200上之對應預定不編碼佈植之通 道區之處皆設計有擬開口 204,因此光罩200上具有均勻散 佈的複數個開口。如此一來，利用此光罩200以進行曝光 1312557 98-3-16 製程時，就不會產生有單一圖案區與密集圖案區之關鍵尺 寸產生偏差之問題。 繼之，請參照第1D圖，在將光阻層110圖案化之後， 以光阻層110爲一編碼罩幕進行一編碼佈植步驟II2,以在 預定編碼佈植之通道區120中植入一編碼離子，而完成一 罩幕式唯讀記憶體之編碼佈植製程。 在本發明中，由於其係利用於光罩上設計均勻分佈的 開口，並將對應於預定不編碼佈植之通道區之開口作小， 以使其在曝光製程中無法於光阻層中成像，而僅讓對應於 預定編碼佈植之通道區之開口能轉移至光阻層。因此本發 明藉由於光罩上設計均勻分佈的開口可避免習知方法中會 產生有單一圖案區與密集圖案區之關鍵尺寸不一致之問 題。 另外，由於本發明不需使用光學鄰近校正法或相移式 光罩技術，即可避免單一圖案區與密集圖案區之關鍵尺寸 產生偏差，因此可大幅降低罩幕式唯讀記憶體元件之製造 成本。 本實施例係以罩幕罩唯讀記憶體之編碼佈植製程爲例 以詳細說明之’但並非限定本發明之微影製程僅能應用在 罩幕罩唯讀記憶體之編碼佈植製程。本發明可應用在其他 任何適用元件之微影製程中，例如形成接觸窗之微影製程 等等。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 9 .1312557 98-3-16 和範圍內，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 第1A圖至第1D圖爲依照本發明一較佳實施例之罩幕 式唯讀記憶體之編碼佈植製程之流程剖面示意圖；以及. 第2圖是依照本發明一較佳實施例之用於罩幕式唯讀 記憶體之編碼佈植製程之一光罩上視圖。 【主要元件符號說明】 100 :基底 102 :埋入式位元線 104 :閘氧化層 106 :絕緣結構 108 :字元線 110 :光阻層 112 :編碼佈植步驟 120 ·預疋編碼佈植之通道區 130 :預定不編碼佈植之通道區 200 :光罩 202 :編碼開口 204 :擬開口 206 :曝光步驟 101312557 98-3-16 VI. Description of the Invention: [Technical Field] The present invention relates to a photolithography, and in particular to a mask-type read-only memory coded implant ( Code Implantation) lithography process. [Prior Art] The structure of a general mask-type read-only memory includes a plurality of bit lines (BL) and a plurality of polyline lines (Word Lines, WLs) across the bit lines. The area below the word line and between the two adjacent bit lines is the channel area of the memory cell. For some mask-type read-only memory, the stylized method is to use the implanted ions in the channel to store the data "〇" or "1". This process of implanting ions into a particular channel region is also known as a coded implant process. In general, the masking process of the mask-type read-only memory is to first pattern the photoresist layer formed on the substrate by using a mask to expose the channel region to be encoded. Then, the patterned photoresist layer is used as an mask for an ion implantation process to implant ions into a predetermined coded channel domain. However, the mask used as the coded mask in the coded implant process of the mask-type read-only memory usually forms a single pattern area and dense on the same mask due to the needs of the circuit design. Pattern area. However, in the exposure step of pattern transfer, since the light intensity of the exposure of the single pattern region is stronger than that of the dense pattern region, the exposure pattern in the dense pattern region and the single pattern region is easily caused by the optical proximity effect. (Optical Proximity Effect, ΟΡΕ), which causes deviations in key dimensions. Thus, 4 1312557 98-3-16 will cause the mask-type read-only memory to cause misalignment of the position of the ion implantation block during the channel ion implantation step, thereby causing only read-only The data in the memory of the memory is wrong, which affects the operational performance of the memory and reduces the reliability of the product. In the conventional method, in order to solve the problem that the dense pattern area of the mask mask of the mask-type read-only memory is inconsistent with the key size of the exposure pattern of the single pattern area, most of the optical proximity correction (OPC) is used. Or Phase Shift Mask (PSM) technology and so on. Among them, the optical proximity correction method uses the design of the auxiliary pattern to eliminate the key dimensional deviation caused by the proximity effect. However, in this way it is necessary to design a reticle with a special pattern. Therefore, in addition to the time consuming production of the mask, the difficulty in manufacturing the mask and the manufacturing cost are further improved. In addition, after the reticle is manufactured, it is extremely difficult to perform defragmentation of the reticle pattern. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a lithography process for use in a mask-type read-only memory coded implant such that it can be simultaneously in a pick-up pattern area and a single pattern area of a memory cell array. Form openings of the same size to avoid deviations in critical dimensions. Another object of the present invention is to provide a lithography process that avoids deviations in critical dimensions without the need for optical proximity correction and phase shift masking techniques. The invention provides a lithography process for mask-type read-only memory coded implants, which first provides a substrate on which a plurality of memory cells arranged in an array of 4, 1312557 98-3-16 are formed on the substrate. . Next, a photoresist layer is formed on the substrate to cover the memory cells. Thereafter, a reticle is disposed above the photoresist layer, and the reticle has a plurality of code openings and a plurality of pseudo openings, wherein the coded opening on the reticle is sealed in a channel region of a predetermined coded implant. The pseudo opening on the reticle corresponds to the remaining channel area that is not intended to encode the implant. Here, the size of the intended opening is less than a critical dimension so that the intended opening cannot be transferred to the photoresist layer in the subsequent lithography process. In the present invention, the size of the intended opening is less than 0.12 μm, preferably less than 〇.〇9 μm, and the size of the coded opening is preferably 0.18 μm to 0.20 μm. Following this, a lithography process is performed to transfer the coded openings on the reticle to the photoresist layer. One of the exposure sources used in this lithography process is a light source having a wavelength of 248 nm. After the lithography process is performed to pattern the photoresist layer, the patterned photoresist layer can be directly used as a coded mask layer for a coding step to be implanted in the channel region of the predetermined coded implant. Enter a coded ion to complete a masked read-only memory coded implant process. The present invention provides a lithography process which first forms a photoresist layer on a substrate. Thereafter, a reticle is disposed above the photoresist layer, and the reticle has a plurality of first openings and a plurality of second openings, wherein the first openings on the reticle correspond to a predetermined imaging area, and the light The second opening on the cover corresponds to a predetermined unimaged area. Here, the size of the second opening is less than a critical dimension ′ such that the second opening cannot be transferred to the photoresist layer in a subsequent lithography process. In the present invention, the size of the second opening is less than 0.12 micrometers, preferably less than 0.09 micrometers, and the size of the first opening is preferably from 0.18 micrometers to 1.2 micrometers. Next, a lithography process is performed to transfer the first opening of the 5 > 1312557 98-3-16 on the photomask to the photoresist layer. One of the exposure sources used in this lithography process is a light source having a wavelength of 248 nm. After the lithography process is performed to pattern the photoresist layer, the patterned photoresist layer can be directly used as an etch mask or an ion implantation mask to etch openings in specific regions of the substrate. Or implant ions in specific areas of the substrate. The lithography process of the present invention utilizes an evenly distributed opening on the reticle and minimizes the opening corresponding to the predetermined unimaged area, and allows only a smooth imaging of the predetermined imaging area on the photoresist layer. In this way, by uniformly distributing the openings, it is possible to avoid the problem that the exposure process has a critical dimension deviation between the single pattern region and the dense pattern region due to the proximity effect. The lithography process of the present invention for mask-type read-only memory coded implants can avoid single pattern regions by eliminating the need for optical proximity correction or phase shift mask technology when patterning the mask layer Deviation from the critical dimensions of the dense pattern area can greatly reduce the manufacturing cost of the component. The above and other objects, features, and advantages of the present invention will become more apparent and understood. 1D is a schematic cross-sectional view showing a process of a coded implant process for a mask-type read-only memory in accordance with a preferred embodiment of the present invention. Referring to FIG. 1A, a mask-type read-only memory system is composed of a plurality of memory cells arranged in an array, and includes a plurality of buried bit lines 102' disposed in the substrate 100. A plurality of polycrystalline sand word lines 108 above the bit line 1〇2. The word line 1〇8 and the buried bit line 6 1312557 98-3-16 102 and the substrate 100 are electrically isolated by an insulating structure 106 and a gate oxide layer 104. The area below the word line ι 8 and between the two adjacent buried bit lines 102 is the channel area of the memory cell. Next, a coded implant process is used to program this masked read-only memory. The details are as follows. Referring to FIG. 1B, a photoresist layer 110 is formed over the substrate 100 to cover the word line 108. Thereafter, a photomask 200 is disposed over the photoresist layer 110. In the present invention, the reticle 200 has a plurality of code openings 202 and a plurality of dummy openings 204. The code opening 202 on the reticle 200 corresponds to a channel region 120 of a predetermined coded implant, and the dummy opening 204 on the reticle 200 corresponds to other channel regions 130 that are not coded. Please also refer to Figure 2, which is a top view of the reticle 200. There are a plurality of code openings 202 and a plurality of open ports 204 on the reticle 200. The size of the dummy opening 204 is less than a critical dimension, so that the dummy opening 204 cannot be transferred to the photoresist layer 110 in the subsequent lithography process. In the present embodiment, the size of the dummy opening 204 is preferably less than 0.12 μm, more preferably less than 〇.〇9 μm. The size of the code opening 202 is, for example, between 0.22 microns and 0.26 microns, preferably between 0.18 microns and 0.20 microns. Then, referring to Fig. 1C, an exposure process 206 is performed and a development process is performed to transfer the code opening 2 〇 2 on the reticle 200 onto the photoresist layer 11 。. The exposure source wavelength of this exposure process 206 is, for example, between 230 nm and 270 nm microns. In the present embodiment, one of the exposure sources used in the exposure process 206 is a light source having a wavelength of 248 nm. 1312557 98-3-16 It should be noted that in the present invention, the photoresist layer 110 used can select a suitable photoresist according to the Dill illumination parameter of the photoresist material, so that it is in the process of the exposure process 206. Corresponding to the insufficient energy absorbed by the photoresist layer 110 at the dummy opening 204 on the mask 200, the image is not imaged, and the energy absorbed by the photoresist layer 110 corresponding to the coded opening 202 on the mask 200 is sufficient. Ability to image. In the present embodiment, since the size of the dummy opening 204 on the reticle 200 is less than 0.12 micrometers, the pseudo opening 204 is not transferred to the photoresist due to the limitation of the exposure resolution in the exposure process 206 using the 248 nm light source. On layer 110. In other words, since the size of the pseudo opening 204 is too small, most of the light passing through the pseudo opening 204 is scattered. Moreover, since the area of the quasi-opening 204 is too small, the energy of the light reaching the photoresist layer 110 through the quasi-opening 204 is not sufficient, so that the photoresist layer 110 corresponding to the quasi-opening 204 is not imaged, thus The photoresist layer 110 corresponding to the dummy opening 204 after the subsequent development process is not formed with an opening. Similarly, since the size of the encoding opening 202 is sufficiently large, the energy reaching the photoresist layer 110 by the light of the encoding opening 202 is sufficient, so that the photoresist layer 110 corresponding to the encoding opening 202 can be smoothly imaged, thus, An opening is formed in the photoresist layer 110 corresponding to the code opening 202 after the subsequent development process. In particular, the photomask 200 of the present invention has a quasi-opening 204 in the channel region of the photomask 200 corresponding to a predetermined uncoded implant, in addition to the encoding opening 202. There are a plurality of openings that are evenly spread. As a result, when the mask 200 is used for the exposure 1312557 98-3-16 process, there is no problem that the critical size of the single pattern region and the dense pattern region are deviated. Then, referring to FIG. 1D, after patterning the photoresist layer 110, a coded implantation step II2 is performed with the photoresist layer 110 as a coding mask to be implanted in the channel region 120 of the predetermined coded implant. A coded ion is used to complete a masked read-only memory encoding process. In the present invention, since it is designed to uniformly distribute the opening on the reticle, and the opening corresponding to the channel region of the predetermined uncoded implant is made small, so that it cannot be imaged in the photoresist layer during the exposure process. Only the opening corresponding to the channel region of the predetermined coded implant can be transferred to the photoresist layer. Therefore, the present invention avoids the problem that the unique size of the single pattern area and the dense pattern area may be inconsistent in the conventional method due to the uniform distribution of the openings on the mask. In addition, since the invention does not need to use the optical proximity correction method or the phase shift mask technology, the deviation between the key pattern area and the dense pattern area can be avoided, thereby greatly reducing the manufacture of the mask type read only memory element. cost. In this embodiment, the coded implant process of the mask cover read-only memory is taken as an example. However, the lithography process of the present invention is not limited to the coded implant process of the mask-only read-only memory. The present invention can be applied to lithography processes of any other suitable components, such as lithography processes that form contact windows, and the like. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make a few changes without departing from the spirit of the invention 9.1312557 98-3-16. The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are schematic cross-sectional views showing a process of a coded implantation process of a mask-type read-only memory according to a preferred embodiment of the present invention; and FIG. 2 is a view of a second aspect of the present invention. A top view of a reticle of a coded implant process for a mask-type read-only memory in a preferred embodiment. [Main component symbol description] 100: substrate 102: buried bit line 104: gate oxide layer 106: insulating structure 108: word line 110: photoresist layer 112: coded implantation step 120 Channel area 130: channel area 200 that is not intended to be coded: mask 202: code opening 204: quasi-opening 206: exposure step 10