TWI312189B - Memory device and manufacturing method and operating method thereof - Google Patents

Description

。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 ^ and method of operation. [Prior Art]

The non-volatile memory in the memory component is a memory that does not cause the data stored therein to disappear due to the interruption of the power supply, and has a plurality of (four) stylized, read, and wiped forwards. Memory, such as electrically erasable programmable read only memory (EEpR〇M), nitrided read only memory (NROM), etc., has been widely used in various personal electrical and electronic devices.

Figure 1A is a top plan view of a conventional nitride-reading memory. The figure is a schematic cross-sectional view along the line of Fig. 1 . Referring to FIG. 1A and FIG. 1B, the nitrite read-only memory first forms a plurality of gate structures 125 on the substrate, and the gate structure 125 includes a layer of germanium from the bottom to the top. / Oxidized stone eve) stacked layers ιι〇 and closed 12 〇. Secondly, a buried bit line 130 is formed, and an oxygen layer is formed on both sides of the gate structure 125. Then, word lines 15A are formed on the gate structure 125, and the gates 125 are connected in series. + When the above-mentioned nitride-free read-only memory is formed in the oxidized stone layer 14 ,, the oxidized stone above the interpole 12Q is removed by chemical mechanical polishing. =^ first form a nitrogen cut on the gate (10), and then use the stripping (Lift_(10) way' to _12Q on the cut. These methods are not 40224 18944twf.doc/e

The shortcoming of the I31218S memory component is that the steps are too complicated. It is quite disadvantageous. In addition, since the gate 12Θ is formed when the word line 15〇 is formed, the strip shape becomes a block structure, and therefore, if the gate electrode 12 is etched, the word line 15 is caused by the inversion. The phenomenon of bridging short circuit between 〇 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广In order to avoid the generation of the channel effect, it is possible to reduce the depth of the buried bit line (10). However, such a ^^^ would result in a very unfavorable performance of the remaining (four) high element of the buried bit line 13G. T ' Alt Body Reader Ξ Ξ I I 2 5m785 exposes an electrically erasable programmable only tw memory that does not form a doped region in the substrate, can, set:: effect 'and its operable area Wide, and there is no need to open the pole::;; erase the programmable read-only memory needs to form a floating layer of germanium to isolate the floating gate and bit line. In addition, in order to operate the material, the domain and the county need to form a crucible. [Inventive content] This is an object of providing an embodiment in accordance with the present invention. Yak, which can reduce the short-channel effect, contributes to the memory element 6 1312189. 98-2-26 A further object of the embodiment according to the present invention is to provide a method for manufacturing a memory element, which is formed by a simple process. Local bit lines can not only omit other complicated processes' but also avoid defects in the memory. - Another object of an embodiment provided in accordance with the present invention is to provide a method of operating a memory device that speeds up the operation of the It body component. - Everyone =                                   Wherein, the conductor layer is provided with a composite dielectric layer disposed on the substrate, covering the conductor layer, the sound is 1, and the second layer is surrounded by a layer of charge trapping layer; the gate is disposed on the composite dielectric ". bulk layer. The diffusion region is located only in the base memory under the respective conductor layers. The conductor layer is, for example, a local bit line. In the memory element, the material of the conductor layer is, for example, doped polycrystalline stone. Layer and meaning ^^ In the body 70, the insulating layer is further disposed between the conductors. The thickness of the insulating layer is, for example, between 20 and 200 angstroms, and the substrate is reversely applied to the conductor layer. The voltage and the shape correspond to the two's. The substrate below the conductor layer further includes a region adjacent to the second layer, and the doping under the adjacent two conductor layers distinguishes the upper layer and the other layer of the conductor layer. The other end of the body has a dopant diffusion region under the conductor layer, or the above: ΪΪ :: t 'charge trapping layer material such as tantalum nitride. Layer, charge trap dielectric layer From the bottom up, including the bottom dielectric 1312189 I cargo year 4:::...^ 98-2-26" Source/drainage, which can form a shallow junction (shaU〇W junction) or a non-doped memory element in the substrate,* but can reduce the short channel effect and contribute to the miniaturization of the memory component. In addition, the conductor is used. As a local bit line, the layer can also reduce the resistance value of the bit line, and further accelerate the operation speed of the § memory element. θ The present invention proposes a method for manufacturing a memory element, which is, for example, first ki, Substrate and forming a plurality of conductor layers on the substrate. Then, a plurality of dopant diffusion regions are formed in the underlying substrate of the conductor layer. Thereafter, the substrate is shaped: a complex W electrical layer: covering the conductor layer, and the composite dielectric layer includes - the layer is then formed on the substrate, and the manufacturing method of the (four) poles across the conductor layer TO and the workpiece is a local bit line. r (4) In the method of manufacturing the memory element described above Before the step of stepping, forming a crucible on the substrate; the thickness of the insulating layer is between 20 and angstroms. The thickness of the insulating layer is before the step of manufacturing the memory device. Guarding the enamel to form an insulator layer The one end of the other conductor layer and the other end of the other conductor layer are located in the step of the manufacturing method of the above memory element, and the base under the conductor layer is further included in the gate electrode, adjacent to the adjacent two conductor layer One end of the plurality of doping regions and the other end of the other conductor layer are formed in the doping. The θ knife is located in one of the leads · I3l2l8ft40224 18944twf.doc/e in the above method for manufacturing the memory device, the eighth includes the bottom dielectric The layer, the charge trapping layer and the top dielectric layer 1 are electrically oxidized by the method of manufacturing the above memory element from the bottom up. &"

, into a 7-layer map #化光阻层. The patterned photoresist layer is used as a mask to remove the patterned conductive material layer, and then the patterned photoresist layer is removed. In the method of manufacturing the MS memory device, the material layer is removed. In the step, the composite dielectric layer is further included as a termination layer. In the above method of manufacturing a memory device, the conductor layer is doped with polysilicon. ,

In the above method for manufacturing a δ-remembered element, a local bit line (conductor layer) is formed by a simple process, and not only other complicated processes can be omitted, but also defects in the memory element can be avoided. In addition, in the process of forming the gate, it is not necessary to simultaneously engrave the underlying conductor layer, but the composite dielectric layer is used as the termination layer, and thus, the problem of incomplete etching and bridging between conductors is not caused. . A method of operating a memory device, the memory device is disposed on a substrate, comprising a plurality of pairs of conductor layers disposed on the substrate, each pair of conductor layers including a first conductor layer and a second conductor layer; a composite dielectric a layer disposed on the substrate to cover the conductor layers, the composite dielectric layer including a charge trapping layer; and a plurality of gates disposed on the composite dielectric layer 'crossing the conductor layers, the operation method is as follows: 9 13121 8040224 18944twf.doc/e When performing a stylization operation, a first voltage is applied to the first conductor layer of the selected conductor layer, a second voltage is applied to the second conductor layer of the conductor layer of the germanium layer, and a second gate is applied to the selected gate. At three voltages, a fourth voltage is applied to the substrate, and electrons are injected into the layer into the charge. In the above method of operating the memory device, the memory device is an N-type memory. In the method of operating a memory element, the third voltage is greater than the first voltage, the first voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage, by means of a channel hot electron injection (CHEI) mechanism The injected charge is trapped in the layer. The operating method towel of the above-mentioned money body component further includes: applying a first voltage to the first conductor layer, applying a first voltage to the second conductor layer, or floating to the second conductor layer during the erasing operation, and selecting Applying a fifth voltage to the gate, applying a fourth voltage to the substrate, and inducing the thermoelectric hole to inject electrons in the charge trapping layer by the valence band-guide band tunneling, wherein the first voltage is greater than the first voltage, and the second voltage The voltage is greater than the fourth voltage and the fourth voltage is greater than the voltage. Not%. The operation method of the above memory element further includes performing a read operation f, applying a sixth voltage to the first conductor layer, and applying a second voltage to the selected conductor. A fourth, voltage is applied to the substrate, wherein the eighth voltage is greater than the sixth voltage, the sixth voltage is greater than the seventh voltage ' and the seventh voltage is greater than the fourth voltage. In the above method of operating the memory element, the memory element is memorized. In the above method for operating the memory device, the third voltage is greater than the fourth voltage 10 1312188, 0224 18944 twf.doc/e voltage, the fourth voltage is greater than the second voltage, and the second voltage is greater than the first voltage, by the valence band-guide band Tunneling thermoelectric holes induce a thermal electron injection (btbthe) mechanism, 9 injecting electrons into the layer. In the method of operating the memory device, the method further includes: applying a fifth voltage to the first conductor layer and applying four voltages to the second conductor layer to apply a seventh voltage to the selected gate. Applying a voltage of eight to the substrate, the charge sinker is erased by the channel FN tunneling mechanism, wherein the eighth voltage is greater than the seventh voltage.

In the method for operating the memory device, the method further comprises: performing a read-conductor layer application-the ninth voltage, applying a second gate layer to the gate-applied-the eleventh voltage, and applying a fourth-shot voltage to the substrate. The tenth voltage is greater than the ninth voltage, and the ninth voltage is greater than tenth - 雩眞. 'The invention proposes another method of operating a memory element, the memory element is obliquely recorded, and each pair of conductor layers includes a first-conductor layer and a second-conductor reed;

Above, the cover = layer is electrically disposed on the substrate in the doped region, each pair: t into the layer, one more flute-exchanged, the r-doped region includes a first doped region and the middle, and the second conductive layer is another The base of the base below W, = the cross-conductor layer on the composite dielectric layer, the voltage of the opposite conductor, and the second conductor of the pair of conductor layers 13 1 2 1 8040224 18944twf.doc/e force a bit-second voltage, applying a third voltage to the first doped region below the first conductor layer, and applying a fourth voltage to the second doped region below the second conductor layer Applying a fifth voltage to the selected gate, applying a sixth voltage to the substrate, and trapping the electrons into the human layer, wherein the first and the second underlying the second conductor layer respectively form a first voltage and a second voltage Two reversal zones. The operation of the above memory element is a green towel, which is a memory element. In the operation method of the memory device, the fifth voltage is greater than the third voltage, the third voltage is greater than the fourth voltage, and the fourth voltage is greater than the sixth voltage, and the electronic charge is trapped by the channel hot electron injection mechanism. In the layer. In the operation method of recalling 2 pieces, the method further comprises: performing a wiping operation; applying a first voltage to the conductive layer, applying a second electric house to the second conductive layer, applying a third voltage to the first doping region, and applying a third voltage to the second doping The impurity region applies = four electric dust' or floats to the second doping, applying a seventh electric, ^, , to the thorium gate, applying a sixth voltage to the substrate, and causing thermoelectricity/conduction through the valence band-guide band interpassing The Zhuangjin mechanism 'eliminates the electrons of the charge trapping layer towel, wherein the third voltage is large: four == the electric house is larger than the sixth voltage, the sixth voltage is greater than the seventh and the U-conductor layer τ is the base towel first-voltage spot The second voltage forms an inversion region. The hard green towel of the above-mentioned (4) section further includes (four) row reading operation = applying a first voltage to the conductor layer, applying a second to the second conductor layer, applying an eighth voltage to the first doping region, and applying a second voltage to the second doping The first gate is applied to the first gate and the voltage is applied to the substrate. The voltage is greater than the n voltage. The voltage is greater than the voltage of the 12th 1312. And forming a reversal zone corresponding to the first voltage and the second voltage in the substrate below the first and second conductor layers. In the method of operating the memory device, the memory cell memory device. The operation method of the memory device The fifth voltage is greater than the sixth voltage 'the sixth (four) is greater than the fourth voltage, and the fourth voltage is greater than the third voltage, and the electron injection charge is trapped by the valence band conduction band passing through the thermoelectric hole induced thermal electron injection (btbthe) mechanism. In the operation method of the upper part, the cleaning operation b is performed, the first voltage is applied to the first conductor layer, the second electricity is applied to the second conductor layer, and the first alternating region is applied. Seven voltages, for the second change zone Pressurize, select the gate to apply the ninth voltage, apply a voltage to the substrate - 苐10 voltage' hunting by the channel FN wear random to erase the electrons in the charge trapping layer, where the tenth is greater than the ninth voltage, the first and the second The corresponding first voltage and the second voltage in the substrate below the conductor layer form an inversion region. In the method for operating the memory device, the method further includes: performing a read operation, applying a first voltage to the gas layer, applying a first region to the second conductor layer, and applying a tenth voltage to the bottom of the second doped region. Sixth Xia, the sixth voltage of the towel is greater than the twelfth, the third voltage is greater than the needle-f pressure, and the tenth-turn is greater than the material three electricity 2: the corresponding first-electric (four) two voltage in the base below the guiding layer In the operation method of the bulk element, the dopant diffusion region is used as the source 131218>9〇224 18944twf.doc/« pole/dip pole, or an appropriate voltage is applied to the conductor layer in the base region (source/drain) To limit the charge to the charge trapping layer. The junction depth of the 7L piece of the memory is very shallow, which can reduce the short-channel effect on the resistance value of the conductor layer. 'More (4) Enhance the operation of the memory component due to the above-mentioned and other purposes and features. And the advantages can be more easily understood. The following detailed description of the embodiments, together with the drawings, will be described in detail. [Embodiment] FIG. 2A is a cross-sectional view of a memory device according to an embodiment of the present invention. intention. Referring to FIG. 2A, the memory device of the present embodiment is composed of, for example, a substrate 200, a plurality of conductor layers 210, a composite dielectric layer 22A, and a plurality of gates 230. The conductor layer 21 is disposed on the substrate 2A. The composite dielectric layer 220 is disposed on the substrate 200 to cover the conductor layer 21A. The gate 230 is disposed, for example, on the composite dielectric layer 22, across the conductor shield 210 〇 ', wherein the substrate 200 is, for example, a P-type germanium substrate. The material of the conductor layer 210 is, for example, doped polysilicon/, and the dopant in the doped polysilicon is, for example, an N-type dopant such as arsenic or phosphorus. This dopant, for example, will diffuse downward from the conductor layer 21 to the substrate 200' such that a dopant diffusion region 215 is formed in the substrate 200. The doped diffusion region 215 is, for example, a source/drain, and the conductor layer 210 is used as a local bit line, for example. Of course, since the material of the conductor layer 210 is doped polysilicon, the conductor layer 210 may also function as a source/drain together with the dopant diffusion region 215. Of course, the substrate 200 may further include a well N (not shown) disposed in its 14 I312im 224 18944twf.doc/e I312im 224 18944twf.doc/e. The material of the 1st layer may be mixed with p-type dopant. Recall the body components. The four pieces of the body may also be a P-type P. The composite layer 22G is composed of, for example, a bottom dielectric layer 22 and a dielectric layer 225. Here, the bottom dielectric layer 2 is made of, for example, bismuth oxide, and the material of the charge trapping layer 223 is, for example, ???, and the material of the top dielectric layer 225 is, for example, oxidized stone. Of course, the bottom dielectric layer and the top dielectric layer 225 may also be other charge trapping layers (2). The material is not limited to nitrogen cutting, and the charge may be trapped in the material f, such as a high dielectric constant material. Telluride, titanic acid and oxides. The gate 230 is, for example, disposed on the composite dielectric layer 22 (), and the birch transconductor = 210. The material of the gate 230 is, for example, doped polycrystalline stone. In the present embodiment, the gate electrode 230 is used for example as a word field. Gate 23. The upper layer, for example, is provided with an interlayer dielectric layer, which is, for example, a dielectric material such as oxygen cutting. In the memory device of the above embodiment, the lower diffusion region 215 of the conductor layer 21 is used as the source/drain to form a memory element having a very shallow junction. The short channel effect can be reduced due to the money-characteristics and contributes to the miniaturization of the memory elements. In addition, the conductor layer 2H) 4乍 is used as a local bit line, which can reduce the electric shouting of the bit line and accelerate the setting of the composite dielectric layer 220, which can not only touch the electric charge of the towel. The trapping layer 223 blocks the charge and also has the effect of the isolation conductor layer 210 (bit line) 13 1 2 1 8040224 18944twf.doc/e and the gate 230 (word line). It is to be noted that, in another embodiment, a layer of insulating layer 2〇5 may be provided between the conductor reed 2-10 and the substrate 200 (not shown). Please refer to FIG. 2B, FIG. 2C and FIG. 2D. Figure 2B is a top plan view of a memory device in accordance with another embodiment of the invention. Figure 2C is a schematic cross-sectional view of the H' line in ^, 2B. 2D is a schematic cross-sectional view along π_πσ, FIG. 2B. The 14-layer, insulating layer 2〇5 (4) is, for example, an insulating material such as oxidized oxide, and the dopant in the conductor layer 210 is not diffused into the underbody 200 due to the high temperature in the process. The thickness of the insulating layer 205 is, for example, 2 〇 2 2 Å. Of course, the material of the conductor layer 210 may also be a non-heteropolycrystalline stone, and there is naturally no diffusion of the dopant in the base. Referring to FIG. 2A and FIG. 2D, the conductor layer 21 is, for example, provided with a contact window 250' connectable to a wire (not shown), and an appropriate voltage is applied to the conductor layer 21, so that the memory component is located on the conductor layer. The substrate 200 below the 21 , forms an inversion region _ 210 corresponding to the voltage applied to the conductor layer 21〇. This dynamically established inversion region 21A can serve as a source/drain, so that no additional doping region is required in the substrate 200 as the source/wave. It is to be noted that, as can be seen from the top view of Fig. 2, the conductor layers 21, for example, are arranged substantially in parallel, and are disposed on the substrate 200, which can be used, for example, as a local bit line. The gates 230 are, for example, arranged substantially in parallel, and are disposed on the composite dielectric layer 220, for example, across the conductor layer 21A and extending in the X direction, for example, the gate 230 is used as a word line. Referring to FIG. 2A and FIG. 2D', since an insulating layer 205 is disposed between the conductor layer 21A and the substrate 130, 13 13121 8040224 18944twf.doc/e, the substrate 200 below the end of the conductor layer 21 is, for example, corresponding to each. The conductor layers 21 are provided with doped regions 245, such as N-type heavily doped regions doped with arsenic or phosphorous. The doped region 245 is provided, for example, with a contact window 255 connected to a wire (not shown) for controlling the voltage of the inversion region 21A, (source/drain). It is worth mentioning that, referring to FIG. 2B, the doped regions 245 under the adjacent two conductor layers 210 are respectively located at one end of one of the conductor layers 21〇 and the other end of the other conductor layer 210. That is, the conductors | 21 〇 can be arranged more closely, and the doping regions 245 are, for example, alternately disposed at both ends of the conductor layer 21 。. In a consistent embodiment, doped region 245 may also be a similar structure to a typical CMOS doped region. Referring to FIG. 2E, the doping region 2 is formed, for example, by a lightly doped region 245, and a heavily doped region 245 having a higher dopant concentration. This doped region 245 can be integrated with a general CMOS process, and is similarly controlled to control the voltage from the inversion region 21' (source/drain). In the memory element of the above embodiment, by using the inversion region 21〇 as the source/drain, it is not necessary to implant (or entangle) the dopant in the substrate 2-〇〇, and the short channel effect can be avoided. Further, the size of the inversion area 21〇 can be more closely controlled according to the = and feature size of the cake, so that the size of the memory 70 can be effectively reduced, thereby increasing the component accumulation. Hereinafter, a method of manufacturing the memory element of the present invention will be described. Fig. 3A, Fig. 3C is a flow cutaway view of the X direction obtained by section 1-1 in Fig. 2B. 4A to 4C are cross-sectional views showing the manufacturing process in the y direction obtained by the π_ΙΓ cross section in Fig. 2B. 17 13 1 2 1 ^^40224 18944twf.doc/e Referring to FIG. 3A and FIG. 4A, a method of fabricating a memory device according to an embodiment of the present invention is, for example, first providing a substrate 2, for example, a p-type substrate. A layer of insulating material (not shown) is then formed on the substrate 200. The material of the insulating material layer is, for example, cerium oxide, and the forming method thereof is, for example, a chemical vapor deposition method. The thickness of the insulating material layer is, for example, between 2 〇 and 2 (9) Å. Then, a layer of a conductive material layer (not shown) is formed on the insulating material layer, and the material of the conductive material layer is, for example, doped (four), and the forming method is, for example, after forming an undoped polysilicon layer by chemical vapor deposition. The sub-implantation step is performed to form, or the doped polysilicon can be formed by chemical vapor deposition in a manner of seed implantation. Of course, the material of the conductor material layer may also be a conductor material of undoped polysilicon. Then, the conductor material layer and the insulating material layer are patterned to form the conductor layer 21 and the insulating layer 205. A method of removing a portion of the conductor material layer and a portion of the insulating material layer is, for example, a lithography and a lithography process. Then, referring to FIG. 3B and FIG. 4B, a composite dielectric layer 220 is formed on the substrate 2A. The composite dielectric layer 220 is composed of, for example, a bottom & φ electrical layer 221, a charge trapping layer 223, and a top dielectric layer 225. The material of the bottom dielectric layer 221 is, for example, oxidized stone, and the formation method thereof is, for example, a ruthenium oxidation method. The material of the charge trapping layer 223 is, for example, tantalum nitride, which is formed by a chemical vapor deposition method. The material of the top dielectric layer 225 is, for example, oxidized stone. The method of forming it is, for example, a chemical vapor deposition method. Of course, the bottom dielectric layer 221 and the top dielectric layer 225 may also be other similar dielectric materials. The material of the charge trap layer 223 is not limited to the nitride diarrhea, but also other materials capable of trapping charges therein, such as a high dielectric constant material, oxide, 18 '40224 18944twf.doc/e barium titanate and铪 Oxide layer and the like. Since the composite dielectric layer 220 covers the surface of the conductor layer 21〇 and the substrate 200 in a whole layer, other regions on the substrate 2 that are not formed with memory components (such as peripheral circuit regions) need to be further layered. Composite dielectric layer 220 is removed. Therefore, the composite dielectric layer of the end wall of the conductor layer 21 is removed as shown in Fig. 4B. A layer of conductive material 227 is then formed on composite dielectric layer 220. The material and formation method of the conductor material layer 227 are the same as those of the above-mentioned conductor material layer, and will not be described herein. Then, referring to FIG. 3C and FIG. 4C, the conductor material layer 227 is patterned to form a plurality of gates 230 across the conductor layer 210. The method of patterning the conductor material layer 227 is, for example, forming a layer of positive photoresist on the layer of the conductor material and patterning the photoresist layer (not shown). The patterned photoresist layers are, for example, arranged in parallel in a strip shape and intersect the conductor layer 21A. Next, the conductor material layer milk exposed by the patterned photoresist layer and the patterned photoresist layer are removed to form the gate 230. The gates 230 are arranged in parallel across the conductor layer 21, and these interpoles 230 are also the word lines of the memory element. Among them, a method of removing a portion of the conductor material layer 227 is, for example, a reactive ion residue method. Moreover, when the exposed conductive material layer 227 is removed, it is more likely to use the composite dielectric layer 220 as a stop-stop layer, and the removal of these conductive materials is made easier to control the insect engraving process. Then, referring to FIG. 4C, a sidewall 235' is formed on the sidewall of the end of the conductor layer 210. This spacer 235 is formed, for example, together with a spacer of a CMOS process performed by a peripheral circuit region (not shown). Next, when the light-doped region and the heavily doped region of the CMOS are formed at 19 131218A 〇 224 18944 twf.d〇c/e, the lightly doped region 245 ′ and the heavily doped region are formed under the conductor layer 21 同时 at the same time. 245,,. The lightly doped region 245' and the heavily doped region 245'' are, for example, n-type doped regions with dopant arsenic, both of which constitute doped regions 245. It is to be noted that, referring to the top view of Fig. 2B, the doped regions 245 under the adjacent two conductor layers 210 are respectively located at one end of one of the conductor layers 21 and the other end of the other conductor layer 210. That is, in order to make the conductor layers 210 more closely arranged, the doping regions 245 are, for example, alternately formed at both ends of the conductor layer 210. Thereafter, referring to FIG. 3C and FIG. 4C, an interlayer dielectric layer 240 is formed on the substrate 200. Then, contact windows 250 and 255 are formed to be electrically connected to the conductor layer 210 and the heavily doped region 245 of the doping region 245, respectively. The contact windows 250, 255 are respectively connected to different wires to apply an appropriate voltage to the germanium conductor layer 210 and the doped region 245. The substrate 2 under the conductor layer 210 corresponds to a voltage applied to the conductor layer 210 to form an inversion region 21A, which can serve as a source/drain. The voltage applied to the doped region 245 can be used to control the voltage of the reverse region 210' (source/drain). It is worth mentioning that in the above embodiment, the doping region 245 is performed in combination with the CMOS system, and is a combination of the lightly doped region 245 and the heavily doped region 245. In another embodiment of the present invention, the doping region 245 may also be doped/ion implanted in a predetermined region before forming the insulating layer 2Q5, such as ®1 2D. The doped dopant is, for example, an n-type dopant ', such as germanium, and the doped H 245 is - the entire (tetra) doped region. 20 131218040224 18944twf.doc/e In addition to the above two manufacturing methods, in conjunction with the structure of another memory element of the present invention, the present invention also proposes a method of manufacturing a memory element. The eye is referred to as ® 1 2A. This manufacturing method is the same as that of the above embodiment. On the substrate 200, the insulating layer 2〇5 is not formed, but the conductor layer 210 is formed directly on the substrate 2〇〇.

In the manufacturing method of the present embodiment, the conductor layer 21 is preferably made of, for example, a doped or polycrystalline wafer. As such, during the subsequent formation of the composite dielectric layer 220, the dopant in the conductor layer 21 turns into the substrate 200 due to the high temperature process to form the dopant diffusion region 215. This dopant diffusion region 215 is, for example, a source/drain, and the conductor layer 21 is, for example, a bit line. The formation methods of the other members are the same as those of the above embodiment, and will not be described herein. In particular, since the fabrication method has formed the dopant diffusion region 215 in the substrate 2, the doping region 245 does not need to be additionally formed at the end of the conductor layer 210. . With the voltage applied to the conductor layer 210, the voltage of the source/drain (doped diffusion region 215) can be controlled.

In the above method of fabricating the memory device, since the conductor layer 210 under the gate 230 is used as a local bit line, it is not necessary to engrave the lower conductor layer 210 into a block shape in defining the gate 23. Rather, the conductor layer 21 is isolated from the gate 230 by using a composite dielectric layer 220 having a charge storage function. This avoids problems such as sample connections, knowing paths, and the like between the gates 230. In addition, since the conductor layer 210 and the gate 230 can be isolated by the composite dielectric layer 220, the manufacturing method does not require the formation of a layer of yttrium oxide 21 131218024 18944 twf.doc/e, which can eliminate chemical mechanical polishing or stripping. The steps of the process greatly shorten the manufacturing process and reduce the manufacturing cost. Furthermore, since the present manufacturing method utilizes the dopant in the conductor layer 21, the dopant diffusion region 215 is formed in the substrate 200, or even does not form a doping in the substrate 200 of the memory device, but the inversion region 21 is utilized. 〇, as a source/drain, it is possible to effectively reduce the short-channel effect and form a memory element with a higher degree of integration. @ The following is a description of the operation method of the above memory element. First, the operation method of the memory element in which the insulating layer 205 and the doping region 245 are not provided will be described. Referring to FIG. 5, the dopant diffusion region 215 is a source/drain, and the body layer 21G is a bit line. In the stylization, the selected push diffusion region 215a is used as the gate, and the gate layer (Vd) is applied to the conductor layer 2 above (the bit line); the adjacent dopant diffusion region 21 is north. a source, a source voltage (Vs) is applied to the conductor layer 2i〇b (bit line) above the eight, and a control voltage is applied to the selected gate 230 (word line) across the source and the drain (Vg) A substrate voltage (Vb) is applied to the substrate 200. Among them, the voltage value from small to large is the base county, the source voltage, the b-voltage and the control voltage. Thus, the electrons can be brought into the charge trapping layer 223 by the dopant J-discharge region 215b (source) into the dopant diffusion region (no-pole) by the channel hot electron injection mode. In the embodiment, the source voltage is, for example, 〇1 to 1 volt, the drain (four) is, for example, 3 to 6 volts, the control voltage is, for example, 6 to 12 volts, and the substrate voltage is, for example, volt-volt. Shi Λ un-operational operation 'on the conductor layer 推 极 极 极 极 极 黯 黯 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体(Vs); a control voltage (Vg) is applied to the gate 23?; a substrate voltage (Vb) is applied to the substrate 200, which is, for example, a volt. Among them, the voltage value from small to large is the control voltage, the substrate voltage, the source voltage and the bungee dust. The band-to-Band tunneling induced hot hole injection is used to erase the electrons of the f-charged layer 223. In the _ implementation, the source voltage is, for example, 〇~1 volt, the drain voltage is, for example, 3 to 6 volts, the control voltage is, for example, 〇 -7 volts, and the substrate voltage is, for example, 〇 volt. Applying a drain voltage (Vd) to the conductor layer 2i〇a on the dopant diffusion region 215a when performing a read operation; shaving the source voltage (Vs) to the conductor layer 21 on the dopant diffusion region 2i5b, Extreme force control port == plus substrate voltage (four). Among them, the voltage value is from small to large according to "two are t, source voltage, and dipole (four) control voltage." By channel opening ϊΙ, to determine the number of mussels stored in the charge trapping layer 223 ~ °οΓ Zhong surname is also "疋". In one embodiment, the source voltage is, for example, 2 to 6 2' = the voltage is 〇 5 to 2 volts, the control voltage is, for example, 6 volts, and the substrate voltage is, for example, volts. The above method of operation is for a memory device. The piece is also = 1 type memory element, and the operation is described below. Referring to FIG. 5, the dopant diffusion region 215 is a source/no enthalpy 'applied with a selected dopant diffusion region I: a bulk layer (10) bit line); a transverse conductor 23 13121 β#24 18944twf. Doc/e 13121 β#24 18944twf.doc/e Applying a control voltage (Vg) to the selected gate 230 (character line) of the base drain 200 applies a substrate voltage (vb). Among them, the voltage value from small to large is sequentially the bungee electric castle, the source voltage, the substrate voltage and the control voltage. This allows the electrons to enter the charge trapping layer of the near-doped diffusion region 215a (the drain) from the dopant diffusion region (10) (source) by the valence-duction-induced thermal electron injection (BTBTHE). In one embodiment, the source voltage is, for example, 〇~" 压, for example, -3 to -6 volts, and the control voltage is, for example, 〇7 volts, for example, 0 volts. When the erasing operation is low, the gate voltage (Vd) is applied to the conductor sound 2 on the dopant diffusion region 215a; the conductor layer % on the dopant diffusion region 2i5b is fully charged, and the interpole 23〇 is controlled. The voltage (5) is applied to the base voltage (Vb). Where 'the substrate voltage is greater than the control voltage. The electrons in the layer 223 are utilized. In the embodiment - the source Si = two 5 volts, the step voltage is, for example, (one) volt, the control voltage is -1 * 2 volts, and the substrate voltage is, for example, 〇 5 volts. The control voltage, the bucker voltage, and the voltage are controlled by the small ones in sequence. By channel opening =:1: to:] off, the digital 存 stored in the charge trapping layer 223. In one embodiment, the source voltage is, for example, 24 13 1 2 1 Liu 24 18944 twf.d0c/e 〇 to -0.5 volt, the drain voltage is, for example, _〇5 to _2 volt, and the control voltage is, for example, -2 to -6. Volt, the substrate voltage is, for example, volts. Next, a method of operating the memory element provided with the insulating layer 205 and the doping region 245 will be described. Please refer to Fig. 6 and Fig. 2C (Fig. 6, 剖面, line sectional view). When the stylization operation is performed, 'applying an appropriate auxiliary voltage Vad' to the selected conductor layer 210a causes the substrate 2 under the conductor layer 210a to form the drain inversion region 210a; and the conductor layer adjacent to the conductor layer 210a is applied at 21%. The appropriate auxiliary voltage Vas causes the substrate 200 under the conductor layer 21〇b to form a source inversion region 21〇b, and a drain voltage (Vd) is applied to the doped region 245a at the end of the conductor layer 21; The source voltage (Vs) is applied to the doped region of the 21% terminal 24%; the control voltage is applied to the selected gate 230 (word line) across the source inversion region 2, and the drain reversal region 210a' (Vg); A substrate voltage (Vb) is applied to the substrate 200. Where 'the control voltage is greater than the gate voltage, the drain voltage is greater than the source voltage, and the source voltage is greater than the substrate voltage, so that the electrons are injected by the source reversal zone 2 through the channel hot electron injection (CHEI) mechanism. The charge of the pole inversion region 210a' is trapped in the layer Z23. In an embodiment, the auxiliary voltage bias, Vas is, for example, 2 to 6 volts, the source voltage is, for example, 〇1 to 1 volt, no volts, the control voltage is, for example, 6 to 12 volts, and the substrate voltage (Vb) is, for example, volt volt. . When the erase operation is performed, the appropriate auxiliary voltages Vad, Vas' are applied to the conductor layers 21a, 21b, and the gate inversion region 21a is generated in the substrate, and the source inversion region 2 is observed. Applying a secret voltage (vd) to the doping region 2, applying a source voltage (Vs) to the doping d 245b, and applying a 25 13121 fox 4 18944 twf.doc/e pressure (vg) to the substrate 200 The substrate voltage state, for example, is: 'the drain voltage is greater than the source voltage, the source voltage is greater than the control $ Μ hunting by the valence band _ conduction band tunneling induced thermoelectric hole injection mechanism, erase the electricity: the electrons entering the layer 223 . In one embodiment, the auxiliary voltage is, for example, specific, the source voltage is, for example, G to 1 volt or floating, the step voltage is, for example, 3 to 6 volts, and the control voltage is, for example, 〇~_7 volt. The reading of the material is also carried out in the body layer of the intestine, the application of the enthalpy = the auxiliary voltage Vad, Vas ', so that the conductor layer 2, the suspension = the base 200 forms the inversion region, and the source reversal zone鸠,; ΪΪ ΪΪ 2 wishes to apply the secret voltage (10); apply the source / (Vs) to the doping, apply control to the gate 230 (character line) (4); apply the base voltage (vb) to the bottom 200. Where 'fresh jf turns as if with '_ electricity_money and greater than the bungee ^丄汲 pole voltage is greater than the source voltage, the source _ is greater than the substrate voltage, = Ϊ pass f switch / channel current Α small to judge stored in the charge trapping layer Partial 3 is in place. In one embodiment, the 'auxiliary voltage, the control voltage is, for example, between 2 and 6 volts, the drain voltage is, for example, between about 5 and 2 volts, and the source voltage is, for example, about 〇~ the substrate voltage. (Vb) is, for example, a volt. • The above embodiment relates to an N-type memory element. The following is the operation of the P-type memory device of the insulating layer 205 and the doped region 245. Figure 2C (Figure 1-1, line profile, ^^t, selected _ 21Ga Applying a suitable reversal zone 21〇a to the substrate 200 under the conductor layer 210a, applying appropriate assistance to the adjacent conductor layer 2l〇b of the conductor layer 210a. Voltage

Vas, the substrate 2 under the conductor layer 210b is formed into a source inversion region 210b, and a drain voltage (vd) is applied to the doped region 245a at the end of the conductor layer 21〇a, and a doped region at the end of the conductor layer 210b 245b applies a source voltage..; applies a control voltage (Vg) across the source inversion region 21b, the gate inversion region 210a, and the far gate 23〇 (word line); Substrate 200 ** A substrate voltage (Vb) is applied. # ^ where 'the control voltage is greater than the substrate voltage, the substrate voltage is greater than the source voltage, and the source voltage is greater than the drain voltage, so that the electrons induce thermal electron injection by the valence band-guide band tunneling thermoelectric hole (ΒΤΒΤΗΕ)_ The charge in the near-inversion reversal zone 210a is trapped in the layer 223. In one embodiment, the auxiliary voltages Vad, Vas are, for example, _2 to -6 volts, the source voltage is, for example, volts, the drain voltage is, for example, -3 to -6 volts, and the control voltage is, for example, 〇 to _7 volts, the substrate voltage (Vb). For example, it is volts. When the erase operation is performed, the appropriate auxiliary voltage and Vas are applied to the conductor layer 21A and the conductor layer 21b, so that the drain is formed in the substrate 20, and the inversion region 210a and the source inversion region 210b are formed. Applying a drain voltage (Vd) to the doped region 245a, applying a sigma source voltage (vs) to the doped region 245b, applying a control voltage (Vg) to the interpole 23 〇', and applying a substrate voltage to the substrate 200 (Vb). Wherein, the substrate voltage is greater than the control voltage, and the electrons in the charge trapping layer 223 are implanted by tunneling through the tunnel FN. In one embodiment, the auxiliary electrical calendar is, for example, _2 to -6 volts, and the source voltage is, for example, 〇~5 volts. The threshold voltage is, for example, 〇~5 volts, and the control voltage is, for example, 〇~_12 27 1312 1i8®24 18944 twf. Doc/e volt, the substrate voltage (Vb) is, for example, 〇~5 volts. When the ff take operation is performed, the auxiliary voltages Vad and Vas are applied to the conductor layer and the conductor layer, so that the conductor layer is applied to the base layer of the substrate, and the source inversion region is opposite to the source inversion region. A drain voltage (Vd) is applied to the region 245a; a source voltage (VS) is applied to the doped region; a control money (Vg) is applied to the gate 230; and a substrate voltage (Vb) is applied to the substrate 200. Wherein, the control voltage is, for example, equal to the auxiliary voltage and less than the threshold voltage, and the voltage is less than the voltage of the substrate. It is stored in the charge trapping layer by the channel switch/channel current size. 22$=digits# is “丨” or “〇”. The control voltage is, for example, between _2 and _6 volts, the immersion voltage is, for example, between -0.5 and -2 volts, and the source voltage is, for example, 〇~_〇5 volts, the substrate voltage (Vb) For example, the operation method of the above-mentioned β-remembrane element of 〇V, applying an appropriate voltage, respectively, the dopant diffusion regions 215a, 215b are immersed, the source, or the appropriate auxiliary voltage is applied to the conductor-layer 21〇 The lower square polarity inversion region 2 runs, and the two source inversion regions 210b, so that the charge is blocked from being trapped in the charge trapping layer 223'. Since the junction depth of the memory element is reduced, the phase is reduced by the short channel effect, and The conductor layer 210 (bit line) has a low resistance value, and is more capable of enhancing the operating speed of the memory element. 〜 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and anyone skilled in the art The scope of protection of the present invention 28 1312 Ii8fi24 18944 twf.doc/e is subject to the definition of the scope of the appended patent application, without departing from the spirit and scope of the invention. Brief description of the formula] Figure 1A shows BRIEF DESCRIPTION OF THE DRAWINGS Figure 1B is a cross-sectional view taken along line Γ-Γ of Figure 1A. Figure 2A is a cross-sectional view of a memory device in accordance with an embodiment of the present invention. 2B is a top view of a memory element according to another embodiment of the present invention. Fig. 2C is a cross-sectional view along the Ι-Γ line of Fig. 2B. Fig. 2D is a cross-sectional view along the ΙΙ-ΙΓ line of Fig. 2B. Fig. 2E is a cross-sectional view showing a memory element according to still another embodiment of the present invention. Fig. 3A to Fig. 3C are cross-sectional views showing the manufacturing process of the X. direction obtained by the Ι-Γ cross section in Fig. 2B. Fig. 4A to Fig. 4C is a cross-sectional view of the manufacturing process in the Y direction obtained by the ΙΙ-ΙΓ cross section in Fig. 2B. Fig. 5 is a schematic view showing the operation of the memory device according to an embodiment of the present invention. Fig. 6 is a view showing another embodiment of the present invention. Schematic diagram of the operation of the memory component. [Main component symbol description] 100, 200: substrate 110: ΟΝΟ stacked layer 120, 230: gate 29 13 1 2 1 8 secret 24 18944twf.doc / e 125: gate structure 130: Buried bit line 140: hafnium oxide layer 150: word line 205: insulating layer 210 : Conductor layer 210': inversion region 215, 215a, 215b: dopant diffusion region 220: composite dielectric layer 221: bottom dielectric layer 223: charge trapping layer 225: top dielectric layer 227: conductor material layer 235: gap Wall 240: interlayer dielectric layer 245, 245a, 245b: doped region 245': lightly doped region - 245": heavily doped region 250, 255: contact window 30

Claims (1)

1312189 Brand: (4) Is replacing I 98-2-26 X. Patent application scope: 1. A memory component comprising: a substrate; a plurality of conductor layers 5 disposed on the substrate, a composite dielectric layer disposed thereon a plurality of gates disposed on the composite dielectric layer across the conductor layers and a dopant diffusion region Only in the substrate below each of the conductor layers. 2. The memory component of claim 1, wherein the conductor layers are as local bit lines. 3. The memory device of claim 1, wherein the conductor layers are doped polysilicon. 4. The memory device of claim 1, further comprising an insulating layer disposed between each of the conductor layers and the substrate. 5. The memory device of claim 4, wherein the thickness of the germanium insulating layer is between 20 and 200 angstroms. 6. The memory device of claim 4, wherein the substrate under the conductor layers corresponds to a voltage applied to the conductor layers to form an inversion region. 7. The memory device of claim 1, wherein the substrate under the conductor layers further comprises a plurality of doped regions correspondingly disposed, and the two doped regions under the adjacent two conductor layers One end of one of the conductor layers and the other end of the other conductor layer are respectively located. The memory element of claim 1, wherein the material of the charge trapping layer comprises tantalum nitride. 9. The memory device of claim 1, wherein the composite dielectric layer comprises a bottom dielectric layer, the charge trapping layer and the top dielectric layer from bottom to top. 10. A method of fabricating a memory device, comprising: providing a substrate; forming a plurality of conductor layers on the substrate; forming a plurality of dopant diffusion regions in the substrate under the conductor layers; forming on the substrate a composite dielectric layer covering the conductor layers, the composite dielectric layer including a charge trapping layer; and a plurality of gates formed on the substrate, the gates being disposed across the conductor layers. 11. The method of fabricating a memory device according to claim 10, wherein the conductor layers are as local bit lines. 12. The method of fabricating a memory device according to claim 10, further comprising forming an insulating layer on the substrate before the step of forming the conductor layer. 13. The method of fabricating a memory device according to claim 12, wherein the insulating layer has a thickness of between 20 and 200 angstroms. 14. The method of fabricating the memory device of claim 12, further comprising forming a plurality of doped regions in the substrate under the conductor layers before the step of forming the insulating layer, wherein the phase The two doped regions under the adjacent two conductor layers are respectively located at one end of one of the conductor layers and the other end of the other conductor layer. 32.1312189 98-2-26 15. The method of fabricating the memory device of claim 12, further comprising forming the gates in the substrate below the conductor layers a plurality of doped regions, wherein the two doped regions under the adjacent two conductor layers are respectively located at one end of one of the conductor layers and the other end of the other of the conductor layers. 16. The method of fabricating a memory device according to claim 10, wherein the composite dielectric layer comprises a bottom dielectric layer, the charge trapping layer and a top dielectric layer from bottom to top. 17. The method of fabricating a memory device according to claim 16, wherein the method of forming the bottom dielectric layer comprises a thermal oxidation method. 18. The method of fabricating a memory device according to claim 10, wherein the method of forming the gates comprises: forming a layer of a conductive material on the substrate; forming a patterned light on the layer of conductive material. a resist layer; the patterned photoresist layer is used as a mask to remove a portion of the conductive material layer; and the patterned photoresist layer is removed. 19. The method of fabricating a memory device according to claim 18, wherein the step of removing a portion of the layer of conductive material further comprises using the composite dielectric layer as a termination layer. 20. The method of fabricating a memory device according to claim 10, wherein the material of the conductor layer comprises doped polysilicon. 33