TWI312189B - Memory device and manufacturing method and operating method thereof - Google Patents
Memory device and manufacturing method and operating method thereof Download PDFInfo
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- TWI312189B TWI312189B TW95124288A TW95124288A TWI312189B TW I312189 B TWI312189 B TW I312189B TW 95124288 A TW95124288 A TW 95124288A TW 95124288 A TW95124288 A TW 95124288A TW I312189 B TWI312189 B TW I312189B
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•0224 18944twf.doc/e 九、發明說明: 【發明所屬之技術領域】 本發明是有關於-種半導體元件及其製造方法與操作 方法,且制是有關於-種記憶體元件及其製造方^與操 作方法。 【先前技術】。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 ^ and method of operation. [Prior Art]
記憶體元件中之非揮發性記憶體是一種不會因電源供 應中斷而使儲存在其中之資料消失的記憶體,其中具有可 進行多次㈣之程式化、讀取、抹_動叙轉發性記 憶體,例如可電抹除可程式唯讀記憶體(EEpR〇M)、氮化 石夕唯讀記憶體(NROM)等等,已經廣泛用於各種個人電 和電子設備。The non-volatile memory in the memory component is a memory that does not cause the data stored therein to disappear due to the interruption of the power supply, and has a plurality of (four) stylized, read, and wiped forwards. Memory, such as electrically erasable programmable read only memory (EEpR〇M), nitrided read only memory (NROM), etc., has been widely used in various personal electrical and electronic devices.
圖1A繪示了-種習知的氮化石夕唯讀記憶體的上視 圖。圖為沿著圖1Α^,線之剖面示意圖。請參照圖 1A與圖1B,此種氮化石夕唯讀記憶體是先在基底動上形 成多個閘極結構125,閘極結構125由下而上包括一層 ΟΝΟ (氧化石夕/氮化石夕/氧化石夕)堆疊層ιι〇與閉極12〇。二 後形成埋人式位元線130,再於閘極結構125兩側形成氧 ^石夕層Μ0。之後在閘極結構125上形成字元線15〇,將各 閘極125串接起來。 +上述氮化石夕唯讀記憶體在形成氧化石夕層14〇的時候, 兩要以化學機械研磨法’將間極12Q上方的氧化石夕移除。 =^先在閘極⑽上形成氮切,再利用剝離(Lift_⑽ 的方式’歸_ 12Q上喊切。這些方法不是會 40224 18944twf.doc/eFigure 1A is a top plan view of a conventional nitride-reading memory. The figure is a schematic cross-sectional view along the line of Fig. 1 . Referring to FIG. 1A and FIG. 1B, the nitrite read-only memory first forms a plurality of gate structures 125 on the substrate, and the gate structure 125 includes a layer of germanium from the bottom to the top. / Oxidized stone eve) stacked layers ιι〇 and closed 12 〇. Secondly, a buried bit line 130 is formed, and an oxygen layer is formed on both sides of the gate structure 125. Then, word lines 15A are formed on the gate structure 125, and the gates 125 are connected in series. + When the above-mentioned nitride-free read-only memory is formed in the oxidized stone layer 14 ,, the oxidized stone above the interpole 12Q is removed by chemical mechanical polishing. =^ first form a nitrogen cut on the gate (10), and then use the stripping (Lift_(10) way' to _12Q on the cut. These methods are not 40224 18944twf.doc/e
I31218S 記憶體元件的缺陷,就是有步驟過於繁複的問題。 上相當地不利。 长衣程 此外,由於閘極12Θ是在字元線15〇形成之時, 本的條狀成為塊狀結構,因此,若是閘極12〇蝕刻不—八、 復容意會導致字元線15〇之間產生橋接短路的現象广王 再者,由於積體電路的發展非常迅速,對於侔 度的要求也越來越高’而隨著線寬賴減,短庫= 影響將會更加崎。為了避級通道效躺產生, =能地減少埋人式位元線⑽的深度’然而,這麼一^ —^會導致埋人式位元線13G的餘㈣高 疋件的效能十分不利。 T ' Alt體 讀纪ίΞ專I二5m785揭露了一種可電抹除可程式唯 種唯tw記憶體在基底中並未形成摻雜區,可 ,置::效應’且其可操作的區域較廣,同時還無須 開極::制;;抹除可程式唯讀記憶體需要形成浮置 虱化矽層以隔離浮置閘極與位元線。另外,為了 的的操作料,此域縣需要料形成Μ 【發明内容】 此it依據本發明提供實施例之目的就是在提供 件的微。兀牛,可以降低短通道效應,有助於記憶體元 6 1312189 脊顧 98-2-26 一依據本發明提供實施例之再一目的是提供一種記憶體 元件的製造方法,利用簡單的製程形成局部位元線,不但 可以省略其他繁複的製程’且能夠避免對記憶體造成缺陷。 —依據本發明提供實施例之另一目的是提供一種記憶體 兀件的操作方法,可以加快記,It體元件的操作速度。 、-人人=月提出種§己憶體元件,包括基底、多個導體層、 層.、、多個閘極與掺f擴散區。其中,導體層是設 複人合介電層是設置於基底上,覆蓋住導體層, 声1,抖二^括了—層電荷陷入層;閘極設置於複合介電 “。體層。摻質擴散區僅位於各導體層下方之基 記憶體細中’導體層例如是作為局部位元線。 ^己憶體元件中,導體層的材質例如是摻雜多晶石夕。 層與義^^體70件中,更包括—絕緣層’設置於各導體 間。遂触a絕緣層的厚度例如是介於20〜200埃之 成—反轉^了方之基底中會對應施加於導體層之電壓而形 對應二’這些導體層下方之基底中更包括 別位於苴由二言 >'隹區,且相鄰二導體層下方之摻雜區分 上二、體層的—端與另—導體層的另-端。 上 己隱體元件’以導體層下方之摻質擴散區,或是 上述:ΪΪ :: t ’電荷陷入層的材質例如是氮化矽。 層、電荷陷電Γ介電層由下而上包括底介電 1312189 I货年ϋ力4:::…^ 98-2-26" 以反轉區作為源極/汲極,而可以形成淺接面(shaU〇W junction)或基底中無摻_記憶體元件,*但能夠降低短 通道效應,且有助於記憶體元件的微縮。此外,採用導體 層作為局部位元線,還能夠降低位元線的電阻值,更進-步加快§己憶體元件的操作速度。 θ本發明提出—種記憶體元件的製造方法,其例如是先 ki、基底並於基底上形成多個導體層。然後,於導體層 下基底中形成多個摻質擴散區。之後,於基底上形: 複W電層:覆蓋住導體層,複合介電層中包括—層 接著於基底上形成多個服,這㈣極橫跨導體 層TO卩又置0 工逖圮m體兀件的製造方法 為局部位元線。 r ㈣如 上述記憶體元件的製造方法中, 的步驟之前,於基底上形成—屌 ;>成¥體 如是介於20〜埃之間料緣層。絕緣層的厚度 上述記憶體元件的製造方法中, 的步驟之前,於這此導护屛文匕栝於形成絕緣 體層的一端與另一導體層的另一端二品刀別位於其中一 上述記憶體元件的製造方法中 步驟之後,於這些導體層下方之基^更包括於形成閘極 其中,相鄰二導體層下方之摻雜中形成多個摻雜區 的一端與另一導體層的另一端。°°刀別位於其中一導· I3l2l8ft40224 18944twf.doc/e 上述記憶體元件的製造方法中,八 包括底介電層、電荷陷入層與頂介電層1電層由下而上 上述記憶體元件的製造方法中 為熱氧化法。 &"電層的形成方法The shortcoming of the I31218S memory component is that the steps are too complicated. It is quite disadvantageous. In addition, since the gate 12Θ is formed when the word line 15〇 is formed, the strip shape becomes a block structure, and therefore, if the gate electrode 12 is etched, the word line 15 is caused by the inversion. The phenomenon of bridging short circuit between 〇 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广 广In order to avoid the generation of the channel effect, it is possible to reduce the depth of the buried bit line (10). However, such a ^^^ would result in a very unfavorable performance of the remaining (four) high element of the buried bit line 13G. T ' Alt Body Reader Ξ Ξ I I 2 5m785 exposes an electrically erasable programmable only tw memory that does not form a doped region in the substrate, can, set:: effect 'and its operable area Wide, and there is no need to open the pole::;; erase the programmable read-only memory needs to form a floating layer of germanium to isolate the floating gate and bit line. In addition, in order to operate the material, the domain and the county need to form a crucible. [Inventive content] This is an object of providing an embodiment in accordance with the present invention. Yak, which can reduce the short-channel effect, contributes to the memory element 6 1312189. 98-2-26 A further object of the embodiment according to the present invention is to provide a method for manufacturing a memory element, which is formed by a simple process. Local bit lines can not only omit other complicated processes' but also avoid defects in the memory. - Another object of an embodiment provided in accordance with the present invention is to provide a method of operating a memory device that speeds up the operation of the It body component. - Everyone = Wherein, the conductor layer is provided with a composite dielectric layer disposed on the substrate, covering the conductor layer, the sound is 1, and the second layer is surrounded by a layer of charge trapping layer; the gate is disposed on the composite dielectric ". bulk layer. The diffusion region is located only in the base memory under the respective conductor layers. The conductor layer is, for example, a local bit line. In the memory element, the material of the conductor layer is, for example, doped polycrystalline stone. Layer and meaning ^^ In the body 70, the insulating layer is further disposed between the conductors. The thickness of the insulating layer is, for example, between 20 and 200 angstroms, and the substrate is reversely applied to the conductor layer. The voltage and the shape correspond to the two's. The substrate below the conductor layer further includes a region adjacent to the second layer, and the doping under the adjacent two conductor layers distinguishes the upper layer and the other layer of the conductor layer. The other end of the body has a dopant diffusion region under the conductor layer, or the above: ΪΪ :: t 'charge trapping layer material such as tantalum nitride. Layer, charge trap dielectric layer From the bottom up, including the bottom dielectric 1312189 I cargo year 4:::...^ 98-2-26" Source/drainage, which can form a shallow junction (shaU〇W junction) or a non-doped memory element in the substrate,* but can reduce the short channel effect and contribute to the miniaturization of the memory component. In addition, the conductor is used. As a local bit line, the layer can also reduce the resistance value of the bit line, and further accelerate the operation speed of the § memory element. θ The present invention proposes a method for manufacturing a memory element, which is, for example, first ki, Substrate and forming a plurality of conductor layers on the substrate. Then, a plurality of dopant diffusion regions are formed in the underlying substrate of the conductor layer. Thereafter, the substrate is shaped: a complex W electrical layer: covering the conductor layer, and the composite dielectric layer includes - the layer is then formed on the substrate, and the manufacturing method of the (four) poles across the conductor layer TO and the workpiece is a local bit line. r (4) In the method of manufacturing the memory element described above Before the step of stepping, forming a crucible on the substrate; the thickness of the insulating layer is between 20 and angstroms. The thickness of the insulating layer is before the step of manufacturing the memory device. Guarding the enamel to form an insulator layer The one end of the other conductor layer and the other end of the other conductor layer are located in the step of the manufacturing method of the above memory element, and the base under the conductor layer is further included in the gate electrode, adjacent to the adjacent two conductor layer One end of the plurality of doping regions and the other end of the other conductor layer are formed in the doping. The θ knife is located in one of the leads · I3l2l8ft40224 18944twf.doc/e in the above method for manufacturing the memory device, the eighth includes the bottom dielectric The layer, the charge trapping layer and the top dielectric layer 1 are electrically oxidized by the method of manufacturing the above memory element from the bottom up. &"
,成7層圖#化光阻層。以此圖案化光阻層為罩幕^除 科導體材料層,之後再移除圖案化光阻層而办成之’、 MS記憶體S件的製造方法中,移除^分;材料層 的步驟中,更包括以複合介電層為終止層。 上述記憶體元件的製造方法中,導體層的 摻雜多晶矽。 、, into a 7-layer map #化光阻层. The patterned photoresist layer is used as a mask to remove the patterned conductive material layer, and then the patterned photoresist layer is removed. In the method of manufacturing the MS memory device, the material layer is removed. In the step, the composite dielectric layer is further included as a termination layer. In the above method of manufacturing a memory device, the conductor layer is doped with polysilicon. ,
上述δ己憶體元件的製造方法,利用簡單的製程,形成 局部位元線(導體層),不但可以省略其他繁複的製程, 且能夠避免對記憶體元件造成缺陷。此外,由於形成閘極 的過程中,不必一併餘刻下方的導體層,而是利用複合介 電層為敍刻終止層,-因此,不會產生蚀刻不完全、導體之 間橋接短路的問題。 一種記憶體元件的操作方法,此記憶體元件設置於— 基底上,包括多對導體層,設置於基底上,各對導體層包 括一第一導體層與一第二導體層;一複合介電層,設置於 基底上,覆蓋住這些導體層,複合介電層中包括一電荷陷 入層;多個閘極,設置於複合介電層上’橫跨這些導體層, 此操作方法例如是: 9 13121 8040224 18944twf.doc/e 進行程式化操作時,對選定之導體層的第—導體層施 加第-電壓,對駭之導體層的第二導體層施加第二電 壓,對-選定閘極施加第三電壓,對基底施加第四電壓, 將電子注入電荷陷入層中。 上述記憶體元件的操作方法中,記憶體元件為N型記 . 憶體元件。 . β. ^述記憶體元件的操作方法中,第三電壓大於第一電 壓,第一電壓大於第二電壓,第二電壓大於第四電壓,藉 • 由通道熱電子注入(CHEI)機制將電子注入電荷陷入層中。曰 士上述錢體元件的操作方法巾,更包括在進行抹除操 作時’對第-導體層施加第一電壓,對第二導體層施加第 —電壓,或浮至第二導體層,對選定閘極施加一第五電壓, 對基底施加第四電壓,藉由價帶_導帶間穿隧誘發熱電洞注 抹除電荷陷入層中的電子,其中第一電壓大於第 一包壓,第二電壓大於第四電壓,且第四電壓大於 壓。 不 % • 上述記憶體元件的操作方法中,更包括在進行讀取操 f,對第一導體層施加一第六電壓,對第二導體層施加 . ’對選定閘極施加-第人電壓,對基底施加第 四,壓,其中第八電壓大於第六電壓,第六電壓大於第七 電壓’且第七電壓大於第四電壓。 上述記憶體元件的操作方法中,記憶冑 憶體元件。 上述記憶體元件的操作方法中,第三電壓大於第四電 10 1312188, 0224 18944twf.doc/e 壓,第四電壓大於第二電壓,第二電壓大於第一電壓,藉 由價帶-導帶穿隧熱電洞誘發熱電子注入(btbthe)機制,9 將電子注入電荷陷入層中。 上述記憶體元件的操作方法中,更包括在進行抹除操 作日^ ’對第-導體層施加一第五電壓’對第二導體層施加 4六電壓’對選定閘極施加-第七電壓,對基底施加一 弟八電壓,藉由通道FN穿隧機制抹除電荷陷入 子’其中第八電壓大於第七電壓。In the above method for manufacturing a δ-remembered element, a local bit line (conductor layer) is formed by a simple process, and not only other complicated processes can be omitted, but also defects in the memory element can be avoided. In addition, in the process of forming the gate, it is not necessary to simultaneously engrave the underlying conductor layer, but the composite dielectric layer is used as the termination layer, and thus, the problem of incomplete etching and bridging between conductors is not caused. . A method of operating a memory device, the memory device is disposed on a substrate, comprising a plurality of pairs of conductor layers disposed on the substrate, each pair of conductor layers including a first conductor layer and a second conductor layer; a composite dielectric a layer disposed on the substrate to cover the conductor layers, the composite dielectric layer including a charge trapping layer; and a plurality of gates disposed on the composite dielectric layer 'crossing the conductor layers, the operation method is as follows: 9 13121 8040224 18944twf.doc/e When performing a stylization operation, a first voltage is applied to the first conductor layer of the selected conductor layer, a second voltage is applied to the second conductor layer of the conductor layer of the germanium layer, and a second gate is applied to the selected gate. At three voltages, a fourth voltage is applied to the substrate, and electrons are injected into the layer into the charge. In the above method of operating the memory device, the memory device is an N-type memory. In the method of operating a memory element, the third voltage is greater than the first voltage, the first voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage, by means of a channel hot electron injection (CHEI) mechanism The injected charge is trapped in the layer. The operating method towel of the above-mentioned money body component further includes: applying a first voltage to the first conductor layer, applying a first voltage to the second conductor layer, or floating to the second conductor layer during the erasing operation, and selecting Applying a fifth voltage to the gate, applying a fourth voltage to the substrate, and inducing the thermoelectric hole to inject electrons in the charge trapping layer by the valence band-guide band tunneling, wherein the first voltage is greater than the first voltage, and the second voltage The voltage is greater than the fourth voltage and the fourth voltage is greater than the voltage. Not%. The operation method of the above memory element further includes performing a read operation f, applying a sixth voltage to the first conductor layer, and applying a second voltage to the selected conductor. A fourth, voltage is applied to the substrate, wherein the eighth voltage is greater than the sixth voltage, the sixth voltage is greater than the seventh voltage ' and the seventh voltage is greater than the fourth voltage. In the above method of operating the memory element, the memory element is memorized. In the above method for operating the memory device, the third voltage is greater than the fourth voltage 10 1312188, 0224 18944 twf.doc/e voltage, the fourth voltage is greater than the second voltage, and the second voltage is greater than the first voltage, by the valence band-guide band Tunneling thermoelectric holes induce a thermal electron injection (btbthe) mechanism, 9 injecting electrons into the layer. In the method of operating the memory device, the method further includes: applying a fifth voltage to the first conductor layer and applying four voltages to the second conductor layer to apply a seventh voltage to the selected gate. Applying a voltage of eight to the substrate, the charge sinker is erased by the channel FN tunneling mechanism, wherein the eighth voltage is greater than the seventh voltage.
上述記憶體元件的操作方法中,更包括在進行讀取 作—導體層施加—第九電壓,對第二導體層施加 =閘極施加—第十一電壓,對基底施加 ’射第四電壓大於料,第十電壓大於第 九電壓,且第九電壓大於第十—雩眞。 ' ^發明提出另—種記憶體元件的操作方法,記憶體元 斜靜錄底上,各 對導體層包括—第—導體層與—第二導體芦; 合In the method for operating the memory device, the method further comprises: performing a read-conductor layer application-the ninth voltage, applying a second gate layer to the gate-applied-the eleventh voltage, and applying a fourth-shot voltage to the substrate. The tenth voltage is greater than the ninth voltage, and the ninth voltage is greater than tenth - 雩眞. 'The invention proposes another method of operating a memory element, the memory element is obliquely recorded, and each pair of conductor layers includes a first-conductor layer and a second-conductor reed;
上,覆蓋=層電電 對摻雜區設置於基底中,各對:t 入層,多 一笛-换她r 對摻雜區包括一第一摻雜區與 中,以及第二導體層之另W下方的基底 極,=複合介電層上’撗跨導體層, =問 進仃程式倾作時’對妓之 ^ 弟電壓,對叙之此對導體層的第二導體層施 13 1 2 1 8040224 18944twf.doc/e 力一口-弟二電壓,對第-導體層下方之第一摻雜區施加一第 三電壓,對第二導體層下方之第二摻雜區施加一第四電 壓’對選定閘極施加-第五電壓,對基底施加一第六電壓, 將電子注人電荷陷人層中,其中第—與第二導體層下方之 基底中分別對應第-電壓與第二電壓形成二反轉區。 上述記憶體元件的操作綠巾,記龍 憶體元件。 口 ^述記憶體元件的操作方法中,第五電壓大於第三電 壓’第三電壓大於第四電麗,第四電壓大於第六電壓,藉 由通道熱電子注人機制將電子注人電荷陷入層中。 作憶2件的操作方法中,更包括在進行抹除操 = 導層施加第—電壓,對第二導體層施加第 二電屋,對第—摻雜區施加第三電壓,對第二摻雜區施加 =四電塵’或浮至第二摻,對敎閘極施加一第七電 、^、、,對基底施加第六電壓,藉由價帶-導帶間穿隨誘發熱電 /同庄入機制’抹除電荷陷人層巾的電子,其中第三電壓大 :四==電屋大於第六電壓,第六電壓大於第七 且U —導體層τ方之基底巾第—電壓斑 第二電壓形成反轉區。 上述記㈣科的難綠巾,更包括㈣行讀取操 作=對卜導體層施加第—電壓,對第二導體層施加第 ,對第-摻雜區施加—第八電壓,對第二摻雜區施 第定閘極施加—第十電壓’對基底施加 第,、電壓,其中斜大於n壓,“電壓大於第 12 1312 服24 18944twf.doc/e 九電壓’第九電壓大於第六電壓,且第一與第二導體層下 方之基底中對應第-電壓與第二電壓形成反轉區。 上述記憶體元件的操作方法中,記憶體元 型記 憶體元件。 上述記憶體元件的操作方法中,第五電壓大於第六電 壓’第六㈣大於第四電壓,第四電壓大於第三電壓,藉 由價帶導帶穿隨熱電洞誘發熱電子注入(btbthe)機制, 將電子注入電荷陷入層中。 上„件的操作方法中,更包括在進行抹除操 作b,對第-導體層施加第—電壓,對第二導體層施加第 二電,,對第-換雜區施加—第七電壓,對第二換雜區施 加壓,選定閘極施加―第九電壓,對基底施加 -苐十電壓’猎由通道FN穿随機制抹除電荷陷入層中的 電子,其中第十·大於第九電壓,第—與第二導體層下 方之基底中對應第-電壓與第二電壓形成反轉區。 上述記憶體元件的操作方法中,更包括在進行讀取操 作^對气ί體層施加第-電壓’對第二導體層施加第 雜區施加—第十—電壓,對第二摻雜區 底施加第六霞,其巾第六電壓大於第十二,第ΐ 電壓大於針-f壓,且第十—轉大於料三電2: 導趙層下方之基底中對應第-電㈣二電壓 上述記憶體元件的操作方法中,以摻質擴散區作為源 131218>9〇224 18944twf.doc/« 極/汲極,或於導體層施加適當的電壓,於基底中形 區(源極/汲極),使電荷得以阻限於電荷陷入層^。轉 記憶體7L件的接面深度很淺,可以減少短通道效應於 導體層的電阻值低’更㈣加強記憶體元件的操^逮声因 ^為讓本發日狀上述和其他目的、特徵和優點能更^ 易懂,下文特舉實施例,並配合所附圖式,作詳細說明^ 下〇 【實施方式】 一圖2A是繪示依照本發明一實施例之記憶體元件的剖 面不意圖。請參照圖2A,本實施例之記憶體元件例如是由 基底200、多個導體層210、複合介電層22〇與多個閘極 230所組成的。其中,導體層21〇是設置於基底2〇〇上。 複合介電層220設置於基底200上,覆蓋住導體層21〇。 閘極230例如是設置於複合介電層22〇上,橫跨過導體屏 210 〇 ’、 曰 其中,基底200例如是P型矽基底。導體層210的材 質例如是掺雜多晶石/,摻雜多晶矽中的摻質例如是砷或磷 等N型摻質。此掺質例如是會從導體層21〇中向下擴散至 基底200 ’使得基底200中會形成有掺質擴散區215。此摻 i擴散區215例如是作為源極/汲極,而導體層210例如是 作為局部位元線之用。當然,由於導體層210的材質為摻 雜多晶矽,因此,導體層210也有可能與摻質擴散區215 一同作為源極/汲極。 當然,基底200更可以包括有N井(未繪示)設置於其 14 I312im〇224 18944twf.doc/e I312im〇224 18944twf.doc/e 中 1層训的材質可以是接雜有p型摻質 憶體元件。 ^之4體几件也可以是P型記 朴P々複電層22G由下而上例如是由底介電層22卜電 層225所组成的。其中,底介電層 2二材貝例如疋氧化石夕,電荷陷入層223的材質例如是 =夕,頂介電層225的材質例如是氧化石夕。當然,底介 ^曰功及頂介電層225也可以是其他 電荷陷入層⑵之材質並不限於氮切,也可 ^電荷陷人於其f之材f,例如高介電常數材料了组ΐ 化物、鈦酸銘物與給氧化物等。 閘極230例如是設置於複合介電層22()上,樺跨導體 = 210。閘極230的材質例如是摻雜多晶石夕,在本實施例 :’閘極230例如料為字域之用。閘極23。上方例如. 1設置有層間介電層’其例如是氧切之類的介電材 料。 上述實施例中之記憶體元件,以導體層21〇下方 質擴散區215作為源極/汲極,而構成了接面極淺的記憶體 兀件。由於錢接_特性’因此能夠降低短通道效應, 並且有助於記憶體元件的微縮。 一 此外,採用導體層2H) 4乍為局部位元線,可以降低位 兀線的電喊H步加快記龍元件_作速度 者’複合介電層220的設置,不但能触其巾之電荷陷入 層223阻限住電荷,還兼具有隔離導體層210 (位元線) 13 1 2 1 8040224 18944twf.doc/e 與閘極230 (字元線)的功效。 特別要說明的是’在另-實施例中,更可以於導體芦 2一 10與基底200之間’設置有-層絕緣層2〇5 (如圖 不)。请參照圖2B、圖2C與圖2D。圖2B是繪示依 發明另-實施例之記憶體元件的上視圖。圖2C是^ , 2B中H’線之剖面示意圖。圖2D沿著圖2B中π_πσ,: 剖面示意圖。 ’ 14 -層、絕緣層2〇5㈣質例如是氧化石夕等絕緣材料, • *得導體層210中的摻質不會因製程中的高溫而往灵底 200中擴散。絕緣層205的厚度例如是2〇〜2〇〇埃。當然一, 導體層210的材質也可以是採用無#雜多晶石夕,則基^細 中自然不會有摻質的擴散。 一 請參照圖2Β與圖2D,導體層21〇上例如是設置有接 觸窗250’可連接至導線(未繪示),於導體層21〇施加 適當電壓,可以使得此記憶體元件位於導體層21〇下方之 基底200,會對應施加於導體層21〇之電壓形成反轉區 _ 210。這個動態建立的反轉區21〇’可以作為源極/汲極,因 此,基底200中便無須另外設置摻雜區來作為源極/波極。 特別注意的是’由圖2Β之上視圖可看出,導體層21 〇 •… 例如是大致平行地排列,設置於基底200上,其例如是可 作為局部位元線之用。閘極230例如是大致平行地排列, 设置於複合介電層220上,其例如是橫跨導體層21〇 ,並 往X方向延伸,閘極230例如是作為字元線之用。 請參照圖2Β與圖2D ’由於導體層21〇與基底200之 16 13121 8040224 18944twf.doc/e 間設置了一層絕緣層205,因此,在導體層21〇末端下方 之基底200中例如是對應每個導體層21〇而設置有摻雜區 245,此摻雜區245例如是摻雜有砷或磷的N型重摻雜區。 摻雜區245上例如是設置有接觸窗255,連接至導線(未 繪示),用來控制反轉區21〇,(源極/汲極)的電壓。 值得一提的是,請參照圖2B,相鄰二導體層210下方 之摻雜區245分別位於其中一導體層21〇的一端與另一導 體層210的另-端。也就是說,$ 了使導體| 21〇可以更 緊猞地排列,摻雜區245例如是交錯地設置於導體層21〇 的兩端。 在一貫施例中,摻雜區245也可以是與一般CMOS的 摻雜區相類似的結構。請參照圖2E,摻雜區2幻例如是由 輕摻雜區245,,以及摻質濃度較高的重摻雜區245,,所银 成的。此摻雜區245可以與一般CMOS製程相整合,立同 樣"J以控制由反轉區21〇’(源極/汲極)的電壓。 、上述實施例之記憶體元件,利用反轉區21〇,作為源椏 /及極,不必在基底2-〇〇中植入(或趨入)摻質,而能夠避 ,短通道效應。再者,反轉區21〇,的尺寸能夠依據製糕的 =、特徵尺寸而更準雜控制,因此更可以有效縮小記憶 體70件之尺寸’從而提高元件積集度。 以下說明本發明之記憶體元件的製造方法。圖3A i 圖3C為圖2B中’由1-1,剖面所得之X方向的製作流稃剖 =圖。圖4A至圖4C為圖2B中,由π_ΙΓ剖面所得之y 方向的製作流程剖面圖。 17 13 1 2 1 ^^40224 18944twf.doc/e 凊參照圖3A與圖4A,本發明一實施例之記憶體元件 的製造方法例如是先提供基底2〇〇,基底200例如是p型 基底。然後’於基底200上形成一層絕緣材料層(未繪示)。 絕緣材料層的材質例如是氧化矽,其形成方法例如是化學 氣相沈積法。絕緣材料層的厚度例如是介於2〇〜2⑼埃之 , 間。接著’於絕緣材料層上形成一層導體材料層(未繪示), 導體材料層的材質例如是摻雜多㈣,其形成方法例如是 利用化學氣相沈積法形成一層未摻雜多晶矽層後,進行離 • 子植入步驟以形成之,或者也可以採用臨場植入掺質的方 式以化學氣相沈積法形成摻雜多晶矽。當然,導體材料層 的材質也可以是無摻雜多晶矽之導體材料。 曰 然後,圖案化導體材料層與絕緣材料層,以形成導體 層21〇與絕緣層205。移除部分導體材料層與部分絕緣材 料層的方法例如是進行微影、敍刻製程。 繼而,請參照圖3B與圖4B,於基底2〇〇上形成一層 複合介電層220。複合介電層220由下而上例如是由底& φ 電層221、電荷陷入層223與頂介電層225所構成的。底 介電層221之材質例如是氧化石夕,其形成方法例如是哉氧 化法。電荷陷入層223之材質例如是氮化矽,其形成^法 " 例如是化學氣相沈積法。頂介電層225之材質例如是氧化 石夕’其形成方法例如是化學氣相沈積法。當然,底介電層 221及頂介電層225也可以是其他類似的介電材質。電荷 陷=層223之材質並不限於氮化石夕,也可叹其他能夠使 電荷陷入於其中之材質’例如高介電常數材料,氧化物、 18 '40224 18944twf.doc/e 鈦酸锶物與铪氧化層物等。 由於複合介電層220是一整層地覆蓋於導體層21〇與 基底200表面,因此,在基底2〇〇上其他未形成記憶體元 件的區域(如周邊電路區),需要再將這一層複合介電層 220移除。因此,導體層21〇末端側壁的複合介電層挪 ' 便會被一併移除’如圖4B所示。 - 之後’於複合介電層220上形成一層導體材料層227。 導體材料層227的材質與形成方法與上述之導體材料層相 # 同,於此不再贅述。 然後,請參照圖3C與圖4C,圖案化導體材料層227, 而形成橫跨導體層210的多個閘極230。圖案化導體材料 層227的方法例如是先爽導體材料層上形成一層正光阻而 幵j圖案化光阻層(未緣示)。圖案化光阻層例如是呈條 狀平行排列,與導體層21〇相交。接下來,移除圖案化光 阻層暴露出之導體材料層奶以及此圖案化光阻層,便形 成閘極230。閘極230平行排列橫跨於導體層21〇上,這 • 些間極230也就是此-記憶體元件的字元線。 .· 其中,移除部分導體材料層227的方法例如是反應性 離子餘刻法。而且,在移除暴露出之導體材料層227的時 候’更可以是利用複合介電層220為敍刻終止層,移除這 些導體材料’使|虫刻製程更容易控制。 、繼而,請繼續參照圖4C,在導體層210末端的側壁形 成間隙壁235 ’此間隙壁235例如是與周邊電路區(未繪 不)進行的CMOS製程之間隙壁一併形成的。接下來,在 19 131218A〇224 18944twf.d〇c/e 形成CMOS的輕摻雜區與重摻雜區時,也同時在導體層 21〇下方,形成輕摻雜區245’與重摻雜區245,,。輕摻雜區 245’與重摻雜區245’’例如是具有摻質砷的n型摻雜區,兩 者構成了摻雜區245。 特別注意的是’請參照圖2B之上視圖,相鄰二導體 層210下方之摻雜區245分別位於其中一導體層21〇的一 端與另一導體層210的另一端。也就是說,為了使導體層 210可以更緊密地排列,摻雜區245例如是交錯地形成於 導體層210的兩端。 之後,請繼續參照圖3C與圖4C,於基底200上形成 層間介電層240。然後,再形成接觸窗250、255,分別與 導體層210,以及摻雜區245之重摻雜區245,,電性連接。 接觸窗250、255會分別連接至不同的導線,而得以對轸導 體層210與摻雜區245施加適當的電壓。 導體層210下方之基底2〇〇中會對應施加於導體層 210的電壓而形成反轉區21〇,,此反轉區21〇,可以作為源 極/汲極。而施加於摻雜區245的電壓,則可以用來控制反 轉區210’(源極/汲極)的電壓。 值得一提的是’上述實施例中,摻雜區245是與CMOS 製私一起進行,而為輕摻雜區245,與重摻雜區245,,的組 合。惟於本發明之另一實施例中,摻雜區245也可以是在 形成絕緣層2Q5之前,就先在預定區域進行摻質/離子植入 製紅’如®1 2D所不。才直入的掺質例如是珅之類的n型摻 質’且摻雜H 245為-整個㈣摻雜區。 20 131218040224 18944twf.doc/e 除了上述兩種製造方法之外,配合本發明另外一種記 憶體元件的結構,本發明還提出—種記憶體元件的製造方 法。睛參照®1 2A,此製造方法與上述實施例$同的是,在 基底200上,並未形成絕緣層2〇5,而是直接於基底2〇〇 上形成導體層210。Above, the cover = layer is electrically disposed on the substrate in the doped region, each pair: t into the layer, one more flute-exchanged, the r-doped region includes a first doped region and the middle, and the second conductive layer is another The base of the base below W, = the cross-conductor layer on the composite dielectric layer, the voltage of the opposite conductor, and the second conductor of the pair of conductor layers 13 1 2 1 8040224 18944twf.doc/e force a bit-second voltage, applying a third voltage to the first doped region below the first conductor layer, and applying a fourth voltage to the second doped region below the second conductor layer Applying a fifth voltage to the selected gate, applying a sixth voltage to the substrate, and trapping the electrons into the human layer, wherein the first and the second underlying the second conductor layer respectively form a first voltage and a second voltage Two reversal zones. The operation of the above memory element is a green towel, which is a memory element. In the operation method of the memory device, the fifth voltage is greater than the third voltage, the third voltage is greater than the fourth voltage, and the fourth voltage is greater than the sixth voltage, and the electronic charge is trapped by the channel hot electron injection mechanism. In the layer. In the operation method of recalling 2 pieces, the method further comprises: performing a wiping operation; applying a first voltage to the conductive layer, applying a second electric house to the second conductive layer, applying a third voltage to the first doping region, and applying a third voltage to the second doping The impurity region applies = four electric dust' or floats to the second doping, applying a seventh electric, ^, , to the thorium gate, applying a sixth voltage to the substrate, and causing thermoelectricity/conduction through the valence band-guide band interpassing The Zhuangjin mechanism 'eliminates the electrons of the charge trapping layer towel, wherein the third voltage is large: four == the electric house is larger than the sixth voltage, the sixth voltage is greater than the seventh and the U-conductor layer τ is the base towel first-voltage spot The second voltage forms an inversion region. The hard green towel of the above-mentioned (4) section further includes (four) row reading operation = applying a first voltage to the conductor layer, applying a second to the second conductor layer, applying an eighth voltage to the first doping region, and applying a second voltage to the second doping The first gate is applied to the first gate and the voltage is applied to the substrate. The voltage is greater than the n voltage. The voltage is greater than the voltage of the 12th 1312. And forming a reversal zone corresponding to the first voltage and the second voltage in the substrate below the first and second conductor layers. In the method of operating the memory device, the memory cell memory device. The operation method of the memory device The fifth voltage is greater than the sixth voltage 'the sixth (four) is greater than the fourth voltage, and the fourth voltage is greater than the third voltage, and the electron injection charge is trapped by the valence band conduction band passing through the thermoelectric hole induced thermal electron injection (btbthe) mechanism. In the operation method of the upper part, the cleaning operation b is performed, the first voltage is applied to the first conductor layer, the second electricity is applied to the second conductor layer, and the first alternating region is applied. Seven voltages, for the second change zone Pressurize, select the gate to apply the ninth voltage, apply a voltage to the substrate - 苐10 voltage' hunting by the channel FN wear random to erase the electrons in the charge trapping layer, where the tenth is greater than the ninth voltage, the first and the second The corresponding first voltage and the second voltage in the substrate below the conductor layer form an inversion region. In the method for operating the memory device, the method further includes: performing a read operation, applying a first voltage to the gas layer, applying a first region to the second conductor layer, and applying a tenth voltage to the bottom of the second doped region. Sixth Xia, the sixth voltage of the towel is greater than the twelfth, the third voltage is greater than the needle-f pressure, and the tenth-turn is greater than the material three electricity 2: the corresponding first-electric (four) two voltage in the base below the guiding layer In the operation method of the bulk element, the dopant diffusion region is used as the source 131218>9〇224 18944twf.doc/« pole/dip pole, or an appropriate voltage is applied to the conductor layer in the base region (source/drain) To limit the charge to the charge trapping layer. The junction depth of the 7L piece of the memory is very shallow, which can reduce the short-channel effect on the resistance value of the conductor layer. 'More (4) Enhance the operation of the memory component due to the above-mentioned and other purposes and features. And the advantages can be more easily understood. The following detailed description of the embodiments, together with the drawings, will be described in detail. [Embodiment] FIG. 2A is a cross-sectional view of a memory device according to an embodiment of the present invention. intention. Referring to FIG. 2A, the memory device of the present embodiment is composed of, for example, a substrate 200, a plurality of conductor layers 210, a composite dielectric layer 22A, and a plurality of gates 230. The conductor layer 21 is disposed on the substrate 2A. The composite dielectric layer 220 is disposed on the substrate 200 to cover the conductor layer 21A. The gate 230 is disposed, for example, on the composite dielectric layer 22, across the conductor shield 210 〇 ', wherein the substrate 200 is, for example, a P-type germanium substrate. The material of the conductor layer 210 is, for example, doped polysilicon/, and the dopant in the doped polysilicon is, for example, an N-type dopant such as arsenic or phosphorus. This dopant, for example, will diffuse downward from the conductor layer 21 to the substrate 200' such that a dopant diffusion region 215 is formed in the substrate 200. The doped diffusion region 215 is, for example, a source/drain, and the conductor layer 210 is used as a local bit line, for example. Of course, since the material of the conductor layer 210 is doped polysilicon, the conductor layer 210 may also function as a source/drain together with the dopant diffusion region 215. Of course, the substrate 200 may further include a well N (not shown) disposed in its 14 I312im 224 18944twf.doc/e I312im 224 18944twf.doc/e. The material of the 1st layer may be mixed with p-type dopant. Recall the body components. The four pieces of the body may also be a P-type P. The composite layer 22G is composed of, for example, a bottom dielectric layer 22 and a dielectric layer 225. Here, the bottom dielectric layer 2 is made of, for example, bismuth oxide, and the material of the charge trapping layer 223 is, for example, ???, and the material of the top dielectric layer 225 is, for example, oxidized stone. Of course, the bottom dielectric layer and the top dielectric layer 225 may also be other charge trapping layers (2). The material is not limited to nitrogen cutting, and the charge may be trapped in the material f, such as a high dielectric constant material. Telluride, titanic acid and oxides. The gate 230 is, for example, disposed on the composite dielectric layer 22 (), and the birch transconductor = 210. The material of the gate 230 is, for example, doped polycrystalline stone. In the present embodiment, the gate electrode 230 is used for example as a word field. Gate 23. The upper layer, for example, is provided with an interlayer dielectric layer, which is, for example, a dielectric material such as oxygen cutting. In the memory device of the above embodiment, the lower diffusion region 215 of the conductor layer 21 is used as the source/drain to form a memory element having a very shallow junction. The short channel effect can be reduced due to the money-characteristics and contributes to the miniaturization of the memory elements. In addition, the conductor layer 2H) 4乍 is used as a local bit line, which can reduce the electric shouting of the bit line and accelerate the setting of the composite dielectric layer 220, which can not only touch the electric charge of the towel. The trapping layer 223 blocks the charge and also has the effect of the isolation conductor layer 210 (bit line) 13 1 2 1 8040224 18944twf.doc/e and the gate 230 (word line). It is to be noted that, in another embodiment, a layer of insulating layer 2〇5 may be provided between the conductor reed 2-10 and the substrate 200 (not shown). Please refer to FIG. 2B, FIG. 2C and FIG. 2D. Figure 2B is a top plan view of a memory device in accordance with another embodiment of the invention. Figure 2C is a schematic cross-sectional view of the H' line in ^, 2B. 2D is a schematic cross-sectional view along π_πσ, FIG. 2B. The 14-layer, insulating layer 2〇5 (4) is, for example, an insulating material such as oxidized oxide, and the dopant in the conductor layer 210 is not diffused into the underbody 200 due to the high temperature in the process. The thickness of the insulating layer 205 is, for example, 2 〇 2 2 Å. Of course, the material of the conductor layer 210 may also be a non-heteropolycrystalline stone, and there is naturally no diffusion of the dopant in the base. Referring to FIG. 2A and FIG. 2D, the conductor layer 21 is, for example, provided with a contact window 250' connectable to a wire (not shown), and an appropriate voltage is applied to the conductor layer 21, so that the memory component is located on the conductor layer. The substrate 200 below the 21 , forms an inversion region _ 210 corresponding to the voltage applied to the conductor layer 21〇. This dynamically established inversion region 21A can serve as a source/drain, so that no additional doping region is required in the substrate 200 as the source/wave. It is to be noted that, as can be seen from the top view of Fig. 2, the conductor layers 21, for example, are arranged substantially in parallel, and are disposed on the substrate 200, which can be used, for example, as a local bit line. The gates 230 are, for example, arranged substantially in parallel, and are disposed on the composite dielectric layer 220, for example, across the conductor layer 21A and extending in the X direction, for example, the gate 230 is used as a word line. Referring to FIG. 2A and FIG. 2D', since an insulating layer 205 is disposed between the conductor layer 21A and the substrate 130, 13 13121 8040224 18944twf.doc/e, the substrate 200 below the end of the conductor layer 21 is, for example, corresponding to each. The conductor layers 21 are provided with doped regions 245, such as N-type heavily doped regions doped with arsenic or phosphorous. The doped region 245 is provided, for example, with a contact window 255 connected to a wire (not shown) for controlling the voltage of the inversion region 21A, (source/drain). It is worth mentioning that, referring to FIG. 2B, the doped regions 245 under the adjacent two conductor layers 210 are respectively located at one end of one of the conductor layers 21〇 and the other end of the other conductor layer 210. That is, the conductors | 21 〇 can be arranged more closely, and the doping regions 245 are, for example, alternately disposed at both ends of the conductor layer 21 。. In a consistent embodiment, doped region 245 may also be a similar structure to a typical CMOS doped region. Referring to FIG. 2E, the doping region 2 is formed, for example, by a lightly doped region 245, and a heavily doped region 245 having a higher dopant concentration. This doped region 245 can be integrated with a general CMOS process, and is similarly controlled to control the voltage from the inversion region 21' (source/drain). In the memory element of the above embodiment, by using the inversion region 21〇 as the source/drain, it is not necessary to implant (or entangle) the dopant in the substrate 2-〇〇, and the short channel effect can be avoided. Further, the size of the inversion area 21〇 can be more closely controlled according to the = and feature size of the cake, so that the size of the memory 70 can be effectively reduced, thereby increasing the component accumulation. Hereinafter, a method of manufacturing the memory element of the present invention will be described. Fig. 3A, Fig. 3C is a flow cutaway view of the X direction obtained by section 1-1 in Fig. 2B. 4A to 4C are cross-sectional views showing the manufacturing process in the y direction obtained by the π_ΙΓ cross section in Fig. 2B. 17 13 1 2 1 ^^40224 18944twf.doc/e Referring to FIG. 3A and FIG. 4A, a method of fabricating a memory device according to an embodiment of the present invention is, for example, first providing a substrate 2, for example, a p-type substrate. A layer of insulating material (not shown) is then formed on the substrate 200. The material of the insulating material layer is, for example, cerium oxide, and the forming method thereof is, for example, a chemical vapor deposition method. The thickness of the insulating material layer is, for example, between 2 〇 and 2 (9) Å. Then, a layer of a conductive material layer (not shown) is formed on the insulating material layer, and the material of the conductive material layer is, for example, doped (four), and the forming method is, for example, after forming an undoped polysilicon layer by chemical vapor deposition. The sub-implantation step is performed to form, or the doped polysilicon can be formed by chemical vapor deposition in a manner of seed implantation. Of course, the material of the conductor material layer may also be a conductor material of undoped polysilicon. Then, the conductor material layer and the insulating material layer are patterned to form the conductor layer 21 and the insulating layer 205. A method of removing a portion of the conductor material layer and a portion of the insulating material layer is, for example, a lithography and a lithography process. Then, referring to FIG. 3B and FIG. 4B, a composite dielectric layer 220 is formed on the substrate 2A. The composite dielectric layer 220 is composed of, for example, a bottom & φ electrical layer 221, a charge trapping layer 223, and a top dielectric layer 225. The material of the bottom dielectric layer 221 is, for example, oxidized stone, and the formation method thereof is, for example, a ruthenium oxidation method. The material of the charge trapping layer 223 is, for example, tantalum nitride, which is formed by a chemical vapor deposition method. The material of the top dielectric layer 225 is, for example, oxidized stone. The method of forming it is, for example, a chemical vapor deposition method. Of course, the bottom dielectric layer 221 and the top dielectric layer 225 may also be other similar dielectric materials. The material of the charge trap layer 223 is not limited to the nitride diarrhea, but also other materials capable of trapping charges therein, such as a high dielectric constant material, oxide, 18 '40224 18944twf.doc/e barium titanate and铪 Oxide layer and the like. Since the composite dielectric layer 220 covers the surface of the conductor layer 21〇 and the substrate 200 in a whole layer, other regions on the substrate 2 that are not formed with memory components (such as peripheral circuit regions) need to be further layered. Composite dielectric layer 220 is removed. Therefore, the composite dielectric layer of the end wall of the conductor layer 21 is removed as shown in Fig. 4B. A layer of conductive material 227 is then formed on composite dielectric layer 220. The material and formation method of the conductor material layer 227 are the same as those of the above-mentioned conductor material layer, and will not be described herein. Then, referring to FIG. 3C and FIG. 4C, the conductor material layer 227 is patterned to form a plurality of gates 230 across the conductor layer 210. The method of patterning the conductor material layer 227 is, for example, forming a layer of positive photoresist on the layer of the conductor material and patterning the photoresist layer (not shown). The patterned photoresist layers are, for example, arranged in parallel in a strip shape and intersect the conductor layer 21A. Next, the conductor material layer milk exposed by the patterned photoresist layer and the patterned photoresist layer are removed to form the gate 230. The gates 230 are arranged in parallel across the conductor layer 21, and these interpoles 230 are also the word lines of the memory element. Among them, a method of removing a portion of the conductor material layer 227 is, for example, a reactive ion residue method. Moreover, when the exposed conductive material layer 227 is removed, it is more likely to use the composite dielectric layer 220 as a stop-stop layer, and the removal of these conductive materials is made easier to control the insect engraving process. Then, referring to FIG. 4C, a sidewall 235' is formed on the sidewall of the end of the conductor layer 210. This spacer 235 is formed, for example, together with a spacer of a CMOS process performed by a peripheral circuit region (not shown). Next, when the light-doped region and the heavily doped region of the CMOS are formed at 19 131218A 〇 224 18944 twf.d〇c/e, the lightly doped region 245 ′ and the heavily doped region are formed under the conductor layer 21 同时 at the same time. 245,,. The lightly doped region 245' and the heavily doped region 245'' are, for example, n-type doped regions with dopant arsenic, both of which constitute doped regions 245. It is to be noted that, referring to the top view of Fig. 2B, the doped regions 245 under the adjacent two conductor layers 210 are respectively located at one end of one of the conductor layers 21 and the other end of the other conductor layer 210. That is, in order to make the conductor layers 210 more closely arranged, the doping regions 245 are, for example, alternately formed at both ends of the conductor layer 210. Thereafter, referring to FIG. 3C and FIG. 4C, an interlayer dielectric layer 240 is formed on the substrate 200. Then, contact windows 250 and 255 are formed to be electrically connected to the conductor layer 210 and the heavily doped region 245 of the doping region 245, respectively. The contact windows 250, 255 are respectively connected to different wires to apply an appropriate voltage to the germanium conductor layer 210 and the doped region 245. The substrate 2 under the conductor layer 210 corresponds to a voltage applied to the conductor layer 210 to form an inversion region 21A, which can serve as a source/drain. The voltage applied to the doped region 245 can be used to control the voltage of the reverse region 210' (source/drain). It is worth mentioning that in the above embodiment, the doping region 245 is performed in combination with the CMOS system, and is a combination of the lightly doped region 245 and the heavily doped region 245. In another embodiment of the present invention, the doping region 245 may also be doped/ion implanted in a predetermined region before forming the insulating layer 2Q5, such as ®1 2D. The doped dopant is, for example, an n-type dopant ', such as germanium, and the doped H 245 is - the entire (tetra) doped region. 20 131218040224 18944twf.doc/e In addition to the above two manufacturing methods, in conjunction with the structure of another memory element of the present invention, the present invention also proposes a method of manufacturing a memory element. The eye is referred to as ® 1 2A. This manufacturing method is the same as that of the above embodiment. On the substrate 200, the insulating layer 2〇5 is not formed, but the conductor layer 210 is formed directly on the substrate 2〇〇.
在本實施例之製造方法中,導體層21〇例如是選用摻 ,多晶發’其形成方法請參照上述說明。如此—來,在後 續形成複合介電層220的過程中,導體層21〇中的摻質會 因為高溫製程而趨入至基底200中,形成摻質擴散區215。 此摻質擴散區215例如是作為源極/汲極,導體層21〇 例如是作為位元線。至於其他構件的形成方法皆與上述實 施例相同,於此不贅述。 、 特別要說明的是,由於此製造方法已於基底2〇〇中形 成摻質擴散區215,因此,導體層210的末端無須另外再 形成摻雜區245。。利用施加於導體層210的電壓,即可以 控制源極/汲極(摻質擴散區215)的電壓。In the manufacturing method of the present embodiment, the conductor layer 21 is preferably made of, for example, a doped or polycrystalline wafer. As such, during the subsequent formation of the composite dielectric layer 220, the dopant in the conductor layer 21 turns into the substrate 200 due to the high temperature process to form the dopant diffusion region 215. This dopant diffusion region 215 is, for example, a source/drain, and the conductor layer 21 is, for example, a bit line. The formation methods of the other members are the same as those of the above embodiment, and will not be described herein. In particular, since the fabrication method has formed the dopant diffusion region 215 in the substrate 2, the doping region 245 does not need to be additionally formed at the end of the conductor layer 210. . With the voltage applied to the conductor layer 210, the voltage of the source/drain (doped diffusion region 215) can be controlled.
在上述記憶體元件的製造方法中,由於閘極230下方 的導體層210是作為局部位元線之用,因此在定義閘極23〇 夺不需要將下方之導體層210姓刻成塊狀,而是利用具 有儲存電荷功能的複合介電層220,將導體層21〇與閘極 230隔離開來,如此便可以避免閘極230之間會產生样接、 知·路等問題。 阿 ^此外,正因為導體層210與閘極230可以利用複合介 電層220而隔離,故而本製造方法無須另行形成氧化矽 21 131218024 18944twf.doc/e 層,而能夠省去化學機械研磨或剝離等製程的步驟,大幅 縮短了製造流程,同時也降低製造成本。 再者,由於本製造方法是利用導體層21〇中的摻質, 於基底200形成摻質擴散區215,或甚至未於記憶體元件 的基底200中形成掺雜’而是利用反轉區21〇,作為源極/ 汲極,因此,能夠有效減輕短通道效應,形成積集度更高 的記憶體元件。 @ 以下是說明上述記憶體元件的操作方法。 首先說明未設置絕緣層205與摻雜區245之記憶體元 件的操作方法。請參照圖5,摻質擴散區215為源極/汲極, ‘體層21G為位元線。在進行程式化時,以選定之推質擴 散區215a作為沒極,對其上方之導體層2施(位元線) 施加汲極電壓(Vd);以相鄰之摻質擴散區21北為源極,對 八上方之導體層2i〇b (位元線)施加源極電壓(Vs);對橫 跨上述源極、汲極之選定閘極230 (字元線)施加控制電 麼(Vg);對基底200施加基底電壓(Vb)。其中,電壓值由 小到大依序為基底縣、源極電壓、汲極f壓與控制電壓。 々此可以使電子藉由通道熱電子注入模式,由摻 質J放區215b (源極)進人靠近摻質擴散區服(沒極) 之電荷陷入層223巾。在-實施例中,源極電壓例如是〇 〜1伏特’汲極㈣例如是3〜6伏特,控制電壓例如是6 〜12伏特,基底電壓例如是〇伏特。 施Λ 未除操作時’對推質擴散區2i5a上之導體層黯 及極電麗⑽;對摻質擴散區215b上之導體層雇 22 13 1 2 1 8040224 18944twf.doc/e 施加源極電壓(Vs);對閘極23〇施加控制電壓(Vg);對基 底200施加基底電壓(Vb) ’其例如是〇伏特。其中,電壓 值由小到大依序為控制電壓、基底電壓、源極電壓與汲極 電塵。利用價帶-導帶間穿隧誘發熱電洞注入機制 (Band-to-Band tunneling induced Hot Hole Injection),抹除 f荷入層223巾的電子。在_實施射,源極電壓例如 =〇〜1伏特,汲極電壓例如是3〜6伏特,控制電壓例如 是〇〜-7伏特,基底電壓例如是〇伏特。 進行讀取操作時’對摻質擴散區215a上之導體層2i〇a 施加汲極電壓(Vd);對摻質擴散區2i5b上之導體層21恥 把力源極電壓(Vs),對間極施力口控制電 ==加基底電壓㈣。其中,電壓值由小到大依“ 二皆t、源極電壓、汲極電㈣控制電壓。’藉由。通道開 ΐΪΓΛ ϊΙ、來判斷儲存於電荷陷入層223中的數位 〇貝〜°οΓ仲姓」還疋「〇」。在一實施例中,源極電壓例如是 是2〜6二’= 壓广如是〇.5〜2伏特,控制電壓例如 6伏特,基底電壓例如是〇伏特。 上述操作方法是用於Ν型記憶體元件。 件還=是1>型記憶體元件,以下即說明其操作^。凡 明參照圖5,摻質擴散區215為源極/沒極 夺’以選定之摻質擴散區I: 體層⑽位元線)施加源極電綱;對橫導 23 13121 β#24 18944twf.doc/e 13121 β#24 18944twf.doc/e 對基 汲極之選定閘極230 (字元線)施加控制電壓(Vg) 底200施加基底電壓(vb)。 其中,電壓值由小到大依序為汲極電堡、源極電壓、 基底電壓與控制電壓。如此可以使電子藉由價帶-導 熱電洞誘發熱電子注入(BTBTHE),從摻質擴散區⑽(源 極)進入^近摻質擴散區215a (汲極)之電荷陷入層您 中。在一實施例中,源極電壓例如是〇〜」 曰 壓例如是-3〜-6伏特,控制電壓例如是〇〜7伏 雷 壓例如是0伏特。 可土低电 進行抹除操作時,對摻質擴散區215a上之導體声2 施加汲極電壓(Vd);對摻質擴散區2i5b上之導體層%滿 電,對間極23〇施加控制電壓㈤鳴 底200施加基底電壓(Vb)。 其中’基底電壓大於控制電壓。利用 入層223中的電子。在-實施例中’源極Si =二5伏特,沒極電壓例如是㈠伏特,控制電壓例 疋了-1*2伏特,基底電壓例如是〇〜5伏特。 控制電壓、汲極電壓 ,、,電紐由小取依序為 關/通道雜1额基底電壓。藉由通道開 =:1:來:]斷,存於電荷陷入層223中的數位 〇」。在一實施例中,源極電壓例如是 24 13 1 2 1柳24 18944twf.d0c/e 〇〜-0.5伏特,汲極電壓例如是_〇 5〜_2伏特,控制電壓例 如是-2〜-6伏特,基底電壓例如是〇伏特。 接下來,說明設置有絕緣層205與摻雜區245之記憶 體元件的操作方法。請參照圖6與圖2C (圖6中Η,線之 剖面圖)。進行程式化操作時’於選定導體層210a施加適 當的辅助電壓Vad’使位於導體層210a下方之基底2〇〇形 成汲極反轉區210a,;於導體層210a相鄰之導體層21% 施加適當的輔助電壓Vas,使位於導體層21〇b下方之基底 200形成源極反轉區21〇b,;於導體層21加末端之摻雜區 245a施加汲極電壓(Vd);於導體層21%末端之摻雜區24% 施加源極電壓(Vs);對橫跨上述源極反轉區2娜,、汲極反 轉區210a’之選定閘極230 (字元線)施加控制電壓(Vg); 對基底200施加基底電壓(Vb)。 其中’控制電壓大於没極電壓,汲極電壓大於源極電 壓,源極電壓大於基底電壓,使電子藉由通道熱電子注入 (CHEI)機制,由源極反轉區2勘,進人靠近汲極反轉區 210a’之電荷陷入層Z23中。在—實施例中,輔助電壓偏、 Vas例如是2〜6伏特,源極電壓例如是〇〜1伏特,沒極 伏特,控制電壓例如是6〜12伏特,基底 電壓(Vb)例如是〇伏特。 進行抹除操作時,同樣是對導體層21〇a、21〇b施加適 *的辅助電壓Vad、Vas ’於基底中產生汲極反轉區 21〇a,與源極反轉區2勘,;於摻雜區2祝施加祕電壓 (vd),於摻雜d 245b施加源極電壓(Vs);對閉極咖施加 25 13121狐4 18944twf.doc/e 壓(vg) ’對基底200施加基底電壓州,其例如是 其:’汲極電壓大於源極電壓,源極電壓大於控 $ Μ猎由價帶_導帶間穿隧誘發熱電洞注入機制,抹除電 :入層223中的電子。在一實施例中,輔助電壓例如是 特,源極電壓例如是G〜1伏特或是浮置,没極電 壓例如是3〜6伏特,控制電壓例如是〇〜_7伏特。 進行讀取操料’同樣是要料體層肠、鳩施加 =虽的輔助電壓Vad、Vas ’使位於導體層2舰、懸下 =基底200形成沒極反轉區施,與源極反轉區鳩,; ίΪΪ區2祝施加祕電壓⑽;於摻龍施加源 /(Vs),對閘極230 (字元線)施加控制電麗㈣;對 暴底200施加基底電壓(vb)。 其中’鮮jf翻如是與’_電_錢且大於汲極 ^丄汲極電壓大於源極電壓,源極_大於基底電壓, =Ϊ通f開關/通道電流Α小來判斷儲存於電荷陷入層 偏3 ϋ入位貝成。在一實施例中’輔助電壓、控制電壓 例如=介於2〜6伏特之間,汲極電壓例如是約介於〇 5 〜2伏特之間,源極電壓例如是約介於〇〜 基底電壓(Vb)例如是〇伏特。 ·>伙特之間 上述實施例是關於N型記憶體元件。以下是絕緣 層205與摻雜區245之P型記憶體元件的操 ^社來 照圖ό與圖2C (圖ό中1-1,線之剖面图、 ^ ^ t 作時,於選定_ 21Ga施加適 26 13 1 2 1 8^224 18944twf.doc/e 於導體層210a下方之基底200形成汲極反轉區21〇a,:於 導體層210a相鄰之導體層2l〇b施加適當的辅助電壓In the above method of fabricating the memory device, since the conductor layer 210 under the gate 230 is used as a local bit line, it is not necessary to engrave the lower conductor layer 210 into a block shape in defining the gate 23. Rather, the conductor layer 21 is isolated from the gate 230 by using a composite dielectric layer 220 having a charge storage function. This avoids problems such as sample connections, knowing paths, and the like between the gates 230. In addition, since the conductor layer 210 and the gate 230 can be isolated by the composite dielectric layer 220, the manufacturing method does not require the formation of a layer of yttrium oxide 21 131218024 18944 twf.doc/e, which can eliminate chemical mechanical polishing or stripping. The steps of the process greatly shorten the manufacturing process and reduce the manufacturing cost. Furthermore, since the present manufacturing method utilizes the dopant in the conductor layer 21, the dopant diffusion region 215 is formed in the substrate 200, or even does not form a doping in the substrate 200 of the memory device, but the inversion region 21 is utilized. 〇, as a source/drain, it is possible to effectively reduce the short-channel effect and form a memory element with a higher degree of integration. @ The following is a description of the operation method of the above memory element. First, the operation method of the memory element in which the insulating layer 205 and the doping region 245 are not provided will be described. Referring to FIG. 5, the dopant diffusion region 215 is a source/drain, and the body layer 21G is a bit line. In the stylization, the selected push diffusion region 215a is used as the gate, and the gate layer (Vd) is applied to the conductor layer 2 above (the bit line); the adjacent dopant diffusion region 21 is north. a source, a source voltage (Vs) is applied to the conductor layer 2i〇b (bit line) above the eight, and a control voltage is applied to the selected gate 230 (word line) across the source and the drain (Vg) A substrate voltage (Vb) is applied to the substrate 200. Among them, the voltage value from small to large is the base county, the source voltage, the b-voltage and the control voltage. Thus, the electrons can be brought into the charge trapping layer 223 by the dopant J-discharge region 215b (source) into the dopant diffusion region (no-pole) by the channel hot electron injection mode. In the embodiment, the source voltage is, for example, 〇1 to 1 volt, the drain (four) is, for example, 3 to 6 volts, the control voltage is, for example, 6 to 12 volts, and the substrate voltage is, for example, volt-volt. Shi Λ un-operational operation 'on the conductor layer 推 极 极 极 极 极 黯 黯 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体(Vs); a control voltage (Vg) is applied to the gate 23?; a substrate voltage (Vb) is applied to the substrate 200, which is, for example, a volt. Among them, the voltage value from small to large is the control voltage, the substrate voltage, the source voltage and the bungee dust. The band-to-Band tunneling induced hot hole injection is used to erase the electrons of the f-charged layer 223. In the _ implementation, the source voltage is, for example, 〇~1 volt, the drain voltage is, for example, 3 to 6 volts, the control voltage is, for example, 〇 -7 volts, and the substrate voltage is, for example, 〇 volt. Applying a drain voltage (Vd) to the conductor layer 2i〇a on the dopant diffusion region 215a when performing a read operation; shaving the source voltage (Vs) to the conductor layer 21 on the dopant diffusion region 2i5b, Extreme force control port == plus substrate voltage (four). Among them, the voltage value is from small to large according to "two are t, source voltage, and dipole (four) control voltage." By channel opening ϊΙ, to determine the number of mussels stored in the charge trapping layer 223 ~ °οΓ Zhong surname is also "疋". In one embodiment, the source voltage is, for example, 2 to 6 2' = the voltage is 〇 5 to 2 volts, the control voltage is, for example, 6 volts, and the substrate voltage is, for example, volts. The above method of operation is for a memory device. The piece is also = 1 type memory element, and the operation is described below. Referring to FIG. 5, the dopant diffusion region 215 is a source/no enthalpy 'applied with a selected dopant diffusion region I: a bulk layer (10) bit line); a transverse conductor 23 13121 β#24 18944twf. Doc/e 13121 β#24 18944twf.doc/e Applying a control voltage (Vg) to the selected gate 230 (character line) of the base drain 200 applies a substrate voltage (vb). Among them, the voltage value from small to large is sequentially the bungee electric castle, the source voltage, the substrate voltage and the control voltage. This allows the electrons to enter the charge trapping layer of the near-doped diffusion region 215a (the drain) from the dopant diffusion region (10) (source) by the valence-duction-induced thermal electron injection (BTBTHE). In one embodiment, the source voltage is, for example, 〇~" 压, for example, -3 to -6 volts, and the control voltage is, for example, 〇7 volts, for example, 0 volts. When the erasing operation is low, the gate voltage (Vd) is applied to the conductor sound 2 on the dopant diffusion region 215a; the conductor layer % on the dopant diffusion region 2i5b is fully charged, and the interpole 23〇 is controlled. The voltage (5) is applied to the base voltage (Vb). Where 'the substrate voltage is greater than the control voltage. The electrons in the layer 223 are utilized. In the embodiment - the source Si = two 5 volts, the step voltage is, for example, (one) volt, the control voltage is -1 * 2 volts, and the substrate voltage is, for example, 〇 5 volts. The control voltage, the bucker voltage, and the voltage are controlled by the small ones in sequence. By channel opening =:1: to:] off, the digital 存 stored in the charge trapping layer 223. In one embodiment, the source voltage is, for example, 24 13 1 2 1 Liu 24 18944 twf.d0c/e 〇 to -0.5 volt, the drain voltage is, for example, _〇5 to _2 volt, and the control voltage is, for example, -2 to -6. Volt, the substrate voltage is, for example, volts. Next, a method of operating the memory element provided with the insulating layer 205 and the doping region 245 will be described. Please refer to Fig. 6 and Fig. 2C (Fig. 6, 剖面, line sectional view). When the stylization operation is performed, 'applying an appropriate auxiliary voltage Vad' to the selected conductor layer 210a causes the substrate 2 under the conductor layer 210a to form the drain inversion region 210a; and the conductor layer adjacent to the conductor layer 210a is applied at 21%. The appropriate auxiliary voltage Vas causes the substrate 200 under the conductor layer 21〇b to form a source inversion region 21〇b, and a drain voltage (Vd) is applied to the doped region 245a at the end of the conductor layer 21; The source voltage (Vs) is applied to the doped region of the 21% terminal 24%; the control voltage is applied to the selected gate 230 (word line) across the source inversion region 2, and the drain reversal region 210a' (Vg); A substrate voltage (Vb) is applied to the substrate 200. Where 'the control voltage is greater than the gate voltage, the drain voltage is greater than the source voltage, and the source voltage is greater than the substrate voltage, so that the electrons are injected by the source reversal zone 2 through the channel hot electron injection (CHEI) mechanism. The charge of the pole inversion region 210a' is trapped in the layer Z23. In an embodiment, the auxiliary voltage bias, Vas is, for example, 2 to 6 volts, the source voltage is, for example, 〇1 to 1 volt, no volts, the control voltage is, for example, 6 to 12 volts, and the substrate voltage (Vb) is, for example, volt volt. . When the erase operation is performed, the appropriate auxiliary voltages Vad, Vas' are applied to the conductor layers 21a, 21b, and the gate inversion region 21a is generated in the substrate, and the source inversion region 2 is observed. Applying a secret voltage (vd) to the doping region 2, applying a source voltage (Vs) to the doping d 245b, and applying a 25 13121 fox 4 18944 twf.doc/e pressure (vg) to the substrate 200 The substrate voltage state, for example, is: 'the drain voltage is greater than the source voltage, the source voltage is greater than the control $ Μ hunting by the valence band _ conduction band tunneling induced thermoelectric hole injection mechanism, erase the electricity: the electrons entering the layer 223 . In one embodiment, the auxiliary voltage is, for example, specific, the source voltage is, for example, G to 1 volt or floating, the step voltage is, for example, 3 to 6 volts, and the control voltage is, for example, 〇~_7 volt. The reading of the material is also carried out in the body layer of the intestine, the application of the enthalpy = the auxiliary voltage Vad, Vas ', so that the conductor layer 2, the suspension = the base 200 forms the inversion region, and the source reversal zone鸠,; ΪΪ ΪΪ 2 wishes to apply the secret voltage (10); apply the source / (Vs) to the doping, apply control to the gate 230 (character line) (4); apply the base voltage (vb) to the bottom 200. Where 'fresh jf turns as if with '_ electricity_money and greater than the bungee ^丄汲 pole voltage is greater than the source voltage, the source _ is greater than the substrate voltage, = Ϊ pass f switch / channel current Α small to judge stored in the charge trapping layer Partial 3 is in place. In one embodiment, the 'auxiliary voltage, the control voltage is, for example, between 2 and 6 volts, the drain voltage is, for example, between about 5 and 2 volts, and the source voltage is, for example, about 〇~ the substrate voltage. (Vb) is, for example, a volt. • The above embodiment relates to an N-type memory element. The following is the operation of the P-type memory device of the insulating layer 205 and the doped region 245. Figure 2C (Figure 1-1, line profile, ^^t, selected _ 21Ga Applying a suitable reversal zone 21〇a to the substrate 200 under the conductor layer 210a, applying appropriate assistance to the adjacent conductor layer 2l〇b of the conductor layer 210a. Voltage
Vas,使位於導體層210b下方之基底2〇〇形成源極反轉區 210b,於導體層21〇a末端之摻雜區245a施加汲極電壓 (vd),於導體層210b末端之摻雜區245b施加源極電壓 .. ;對橫跨上述源極反轉區2l〇b,、汲極反轉區210a,之 • 遠疋閘極23〇 (字元線)施加控制電壓(Vg);對基底200 ** 施加基底電壓(Vb)。 # ^其中’控制電壓大於基底電壓,基底電壓大於源極電 壓,源極電壓大於汲極電壓,使電子藉由價帶-導帶穿隧熱 電洞誘發熱電子注人(ΒΤΒΤΗΕ)_,進人#近跡反轉 區210a之電荷陷入層223中。在一實施例中,輔助電壓 Vad、Vas例如是_2〜_6伏特,源極電壓例如是伏特, 汲極電壓例如是-3〜_6伏特,控制電壓例如是〇〜_7伏特, 基底電壓(Vb)例如是〇伏特。 進行抹除操作時,同樣是對導體層21〇a與導體層21〇b • 施加適當的輔助電壓與Vas,使基底20〇中形成汲極 . 反轉區210a,與源極反轉區210b,;對摻雜區245a施加汲 極電壓(Vd),對摻雜區245b施力σ源極電壓(vs);對間極23 〇 ' 施加控制電壓(Vg),·對基底200施加基底電壓(Vb)。 其中,基底電壓大於控制電壓,利用通道FN穿隧誘 發熱電洞注入抹除電荷陷入層223中的電子。在一實施例 中辅助電歷例如是_2〜_6伏特,源極電壓例如是〇〜5 伏特’汲極電壓例如是〇〜5伏特,控制電壓例如是〇〜_12 27 1312 1i8®24 18944twf.doc/e 伏特,基底電壓(Vb)例如是〇〜5伏特。 進行ff取操作時,對導體層咖與導體層施加 如的輔助電壓Vad與Vas,使導體層施解體層雇 之基底中形纽極反轉區聽,與源極反轉區 ,對摻雜區245a施加汲極電壓(Vd);對摻雜區勘 施加源極電壓(VS);對閘極230施加控制錢(Vg);對基 底200施加基底電壓(Vb)。 β其中,控制電壓例如是等於輔助電壓且小於汲極電 壓’汲極糕小於雜電壓,馳電壓小於基底電壓。藉 由通道開關/通道電流大小來朗儲存於電荷陷入層22$ =數位#訊是「丨」還是「〇」。在—實施财^助電 壓”控制電壓例如是介於_2〜_6伏特,沒極電壓例如是介 於-0.5〜-2伏特,源極電壓例如是〇〜_〇 5伏特,基底電壓 (Vb)例如是〇伏特 上述β己憶體元件的操作方法,施加適當的電壓,分別 以摻質擴散區215a、215b為沒極、源極,或者是施加適者 的輔助電壓,於導體-層21〇下方形歧極反轉區2跑,二 源極反轉區210b,,使電荷得以阻限於電荷陷入層223中'。 由於記憶體元件的接面深度减,相減少短^道效應, 且因導體層210 (位元線)的電阻值低,更能夠加強記憶 體元件的操作速度。 〜 雖然本發明已以實施例揭露如上,然其並非用以限定 本發明,任何熟習此技藝者,在不脫離本發明之精神和^ 圍内,當可作些許之更動與潤飾,因此本發明之保護範圍 28 1312 Ii8fi24 18944twf.doc/e 當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A繪示了 一種習知的氮化矽唯讀記憶體的上視圖。 圖1B為沿著圖1A之Ι-Γ線之剖面示意圖。 圖2A是繪示依照本發明一實施例之記憶體元件的剖 面示意圖。 圖2B是繪示依照本發明另一實施例之記憶體元件的 上視圖。 圖2C是沿著圖2B中Ι-Γ線之剖面示意圖。 圖2D沿著圖2B中ΙΙ-ΙΓ線之剖面示意圖。 圖2E是繪示本發明又一實施例之記憶體元件的剖面 示意圖。 圖3A至圖3C為圖2B中,由Ι-Γ剖面所得之X.方向 的製作流程剖面圖。 圖4A至圖4C為圖2B中,由ΙΙ-ΙΓ剖面所得之Y方 向的製作流程剖面圖。 圖5是繪示本發朝一實施例之記憶體元件的操作示意 圖。 圖6是繪示本發明另一實施例之記憶體元件的操作示 意圖。 【主要元件符號說明】 100、200 :基底 110 : ΟΝΟ堆疊層 120、230 :閘極 29 13 1 2 1 8秘24 18944twf.doc/e 125 :閘極結構 130 :埋入式位元線 140 :氧化矽層 150 :字元線 205 :絕緣層 210 :導體層 210’ :反轉區 215、215a、215b :摻質擴散區 220 :複合介電層 221 :底介電層 223 :電荷陷入層 225 :頂介電層 227 :導體材料層 235 :間隙壁 240 :層間介電層 245、245a、245b :摻雜區 245’ :輕摻雜區-245” :重摻雜區 250、255 :接觸窗 30Vas, the substrate 2 under the conductor layer 210b is formed into a source inversion region 210b, and a drain voltage (vd) is applied to the doped region 245a at the end of the conductor layer 21〇a, and a doped region at the end of the conductor layer 210b 245b applies a source voltage..; applies a control voltage (Vg) across the source inversion region 21b, the gate inversion region 210a, and the far gate 23〇 (word line); Substrate 200 ** A substrate voltage (Vb) is applied. # ^ where 'the control voltage is greater than the substrate voltage, the substrate voltage is greater than the source voltage, and the source voltage is greater than the drain voltage, so that the electrons induce thermal electron injection by the valence band-guide band tunneling thermoelectric hole (ΒΤΒΤΗΕ)_ The charge in the near-inversion reversal zone 210a is trapped in the layer 223. In one embodiment, the auxiliary voltages Vad, Vas are, for example, _2 to -6 volts, the source voltage is, for example, volts, the drain voltage is, for example, -3 to -6 volts, and the control voltage is, for example, 〇 to _7 volts, the substrate voltage (Vb). For example, it is volts. When the erase operation is performed, the appropriate auxiliary voltage and Vas are applied to the conductor layer 21A and the conductor layer 21b, so that the drain is formed in the substrate 20, and the inversion region 210a and the source inversion region 210b are formed. Applying a drain voltage (Vd) to the doped region 245a, applying a sigma source voltage (vs) to the doped region 245b, applying a control voltage (Vg) to the interpole 23 〇', and applying a substrate voltage to the substrate 200 (Vb). Wherein, the substrate voltage is greater than the control voltage, and the electrons in the charge trapping layer 223 are implanted by tunneling through the tunnel FN. In one embodiment, the auxiliary electrical calendar is, for example, _2 to -6 volts, and the source voltage is, for example, 〇~5 volts. The threshold voltage is, for example, 〇~5 volts, and the control voltage is, for example, 〇~_12 27 1312 1i8®24 18944 twf. Doc/e volt, the substrate voltage (Vb) is, for example, 〇~5 volts. When the ff take operation is performed, the auxiliary voltages Vad and Vas are applied to the conductor layer and the conductor layer, so that the conductor layer is applied to the base layer of the substrate, and the source inversion region is opposite to the source inversion region. A drain voltage (Vd) is applied to the region 245a; a source voltage (VS) is applied to the doped region; a control money (Vg) is applied to the gate 230; and a substrate voltage (Vb) is applied to the substrate 200. Wherein, the control voltage is, for example, equal to the auxiliary voltage and less than the threshold voltage, and the voltage is less than the voltage of the substrate. It is stored in the charge trapping layer by the channel switch/channel current size. 22$=digits# is “丨” or “〇”. The control voltage is, for example, between _2 and _6 volts, the immersion voltage is, for example, between -0.5 and -2 volts, and the source voltage is, for example, 〇~_〇5 volts, the substrate voltage (Vb) For example, the operation method of the above-mentioned β-remembrane element of 〇V, applying an appropriate voltage, respectively, the dopant diffusion regions 215a, 215b are immersed, the source, or the appropriate auxiliary voltage is applied to the conductor-layer 21〇 The lower square polarity inversion region 2 runs, and the two source inversion regions 210b, so that the charge is blocked from being trapped in the charge trapping layer 223'. Since the junction depth of the memory element is reduced, the phase is reduced by the short channel effect, and The conductor layer 210 (bit line) has a low resistance value, and is more capable of enhancing the operating speed of the memory element. 〜 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and anyone skilled in the art The scope of protection of the present invention 28 1312 Ii8fi24 18944 twf.doc/e is subject to the definition of the scope of the appended patent application, without departing from the spirit and scope of the invention. Brief description of the formula] Figure 1A shows BRIEF DESCRIPTION OF THE DRAWINGS Figure 1B is a cross-sectional view taken along line Γ-Γ of Figure 1A. Figure 2A is a cross-sectional view of a memory device in accordance with an embodiment of the present invention. 2B is a top view of a memory element according to another embodiment of the present invention. Fig. 2C is a cross-sectional view along the Ι-Γ line of Fig. 2B. Fig. 2D is a cross-sectional view along the ΙΙ-ΙΓ line of Fig. 2B. Fig. 2E is a cross-sectional view showing a memory element according to still another embodiment of the present invention. Fig. 3A to Fig. 3C are cross-sectional views showing the manufacturing process of the X. direction obtained by the Ι-Γ cross section in Fig. 2B. Fig. 4A to Fig. 4C is a cross-sectional view of the manufacturing process in the Y direction obtained by the ΙΙ-ΙΓ cross section in Fig. 2B. Fig. 5 is a schematic view showing the operation of the memory device according to an embodiment of the present invention. Fig. 6 is a view showing another embodiment of the present invention. Schematic diagram of the operation of the memory component. [Main component symbol description] 100, 200: substrate 110: ΟΝΟ stacked layer 120, 230: gate 29 13 1 2 1 8 secret 24 18944twf.doc / e 125: gate structure 130: Buried bit line 140: hafnium oxide layer 150: word line 205: insulating layer 210 : Conductor layer 210': inversion region 215, 215a, 215b: dopant diffusion region 220: composite dielectric layer 221: bottom dielectric layer 223: charge trapping layer 225: top dielectric layer 227: conductor material layer 235: gap Wall 240: interlayer dielectric layer 245, 245a, 245b: doped region 245': lightly doped region - 245": heavily doped region 250, 255: contact window 30
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