TW200814238A - Self-aligned stacked gate and method for making the same - Google Patents

Abstract

A method of making self-aligned stacked gate for a flash memory device is disclosed. The method includes the steps of (a) providing a substrate; (b) sequentially forming a first dielectric layer, a first conductive layer and a mask layer on the substrate; (c) partly etching the mask layer, the first conductive layer and the first dielectriclayer to define a shallow trench; (d) filling the shallow trench with a second dielectric layer to form a shallow trench isolation (STI) unit; (e) entirely forming a second conductive layer; (f) partly etching the second conductive layer to form a spacer on the first conductive, wherein the first conductive layer and the spacer provide a floating gate (FG) unit; (g) partly removing the STI unit to expose a part of side wall of the first conductive layer and the spacer; (h) sequentially forming a third dielectric layer and a third conductive layer; and (i) partly etching the third conductive layer to define a control gate (CG), thereby obtaining the self-aligned stacked gate structure with high coupling ratio.

Description

200814238 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for manufacturing a non-volatile memory, and more particularly to a method for manufacturing a self-aligned stacked gate in a non-volatile memory. [Prior Art]

In various types of memory products in the industry today, the erasable programmable read-only memory (EPROM) has the functions of writing, writing, and erasing multiple data, and depositing them. The data does not disappear after power-off, so it has become a memory component widely used in personal computers and electronic devices. A typical programmable non-volatile memory system uses a doped polysilicon to fabricate a floating gate (FG) gate (control gate, CG). * The annual gate and the control electrode are separated by a gate dielectric layer, and the floating gate and the substrate are separated by a tunnel dielectric layer. When a write/erase data action is performed on this memory, a charge is injected into the floating gate or the charge is discharged from the floating gate by applying a bias voltage to the control gate and the source/drain regions. Move out. While reading the data % in the memory, an operating voltage is applied to the control gate, and the floating starting voltage (threshold v 〇 tage) has been changed by the previous writing/wiping, so The difference in starting voltage is used to interpret the data value. However, in practical applications, since the floating gate is a continuous layer of semi-200814238 conductor layer (polysilicon layer), the charge injected into the floating gate is evenly distributed throughout the floating gate. For such memory, a memory cell can only store one bit of data, so how to effectively define and shorten the distance between adjacent polysilicon gates to achieve the purpose of reducing the size of the wafer becomes an important issue. . In the semiconductor process, the self-aligned, contact Uelf-aligned contact (SAC) process can effectively deviate and shorten the distance between the gates of the Zhengzhou polycrystalline germanium to reduce the size of the wafer. • A first figure (A) - the first figure (1) reveals - the conventional technology flash memory schematic diagram of the early gate stacking process. This manufacturing process is disclosed in U.S. Patent No. 6,171,909. As shown in the first figure (A): First, a substrate having a well, source/drain (not disclosed) is provided. This technique is a well-known technique and will not be described in detail herein. Further, above the substrate, a first-dielectric layer 1G2, a conductive layer 1G4, and a nitrogen-metal layer 1G6 are sequentially stacked and formed thereon. Thereafter, a photoresist layer 11 having a defined pattern is formed on the tantalum nitride layer 1〇6. The first dielectric layer 102 can form an oxide layer having a thickness of about 60 to 120 angstroms (angStr 〇 mS) by oxidizing the base layer. The conductive layer 104 may be formed by doping a polysilicon layer; the tantalum nitride layer 1〇6 may be in the first figure (8), through the residual layer cover, the ratification layer 106, the conductive layer 1〇4 The first dielectric layer ι〇2 fish plate 1GG is subjected to non-isotropic (four) until the substrate 1 is topped up = trench 112. The photoresist layer 11 is removed after the non-isotropic first name. a pad oxide layer (liner idexide 7 200814238 la^er) 114 is formed on the surface of the trench 112, the first dielectric layer 102, and the electric s 104, wherein the pad The oxide layer 114 can be formed by a method of thermal oxidation. In the thermal oxidation process, the trench 112 and the conductive layer = surface are oxidized to form a thin oxide layer while extending outwardly and covering the sidewall of the first dielectric layer 102. During this period, the tantalum nitride layer has no formation of a pad oxide layer. In the first (D), an oxide layer 116 is formed over the substrate 10Q, wherein the oxide layer 116 has a thickness sufficient to cover the layer 106. 7

^, in Fig. (E), a chemical-mechanical polishing (CMP) process is performed on the oxide layer 116 with the tantalum nitride 106 as a reference end point for the purpose of daily soiling. The remaining oxide layer 116 and the aforementioned pad = -114 constitute an insulating layer ι18. In the first, second, and (F), (iv) the insulating layer 118 until the upper portion of the layer 104 is exposed. The etching can be dry etching or wet etching. The insulating layer 118 is formed by oxygen dicing to isolate the Uhallow trench isolation (STI) unit. The 12th portion of the household 12"Fig. 2) 12 is further formed on the remaining 10° - the conductive material layer 12-0, wherein the layer 12 of the electrical material can be obtained by pushing the polycrystalline stone. In the first figure, the conductive material layer 12 is non-isotropically etched until the tantalum nitride layer 106 and the insulating layer U8 are exposed. Thus, the etch-conducting sidewall 12a is formed on the sidewall of the conductive layer 104 and the nitride layer (10), and the conductive layer 120a and the conductive layer serve as the first gate conductive layer 122. The nitrogen cut layer 1G6 is removed after forming the first gate conductive layer 122. In the first diagram (i), a second dielectric layer 124 and a second gate conductive layer 126 are sequentially It is formed on the substrate 1〇〇. The second layer of germanium 124 is an oxide/nitride/oxide (0N0) layer; and the second gate conductive layer 126 is a doped polysilicon layer. , that is, a stack gate of a flash memory unit is obtained. On the other hand, U.S. Patent No. 6, P, 856, discloses a stack gate manufacturing process for another flash memory cell. As shown in the first figure (κ) of the second figure (A), it discloses a schematic diagram of the manufacturing process of the stacked gate of another conventional flash memory unit. First, as shown in the second figure (1), a tantalum oxide layer 2〇3 is formed on a substrate 201. Next, as shown in Fig. 2 (8), a mask layer 2〇5 is formed on the pad oxide layer 2〇3, and the mask layer 205 is formed of a deposited tantalum nitride. In the sister-in-law (C), after the pattern of the 疋Yiyuan mask layer 205, the mask layer m, the cushion oxide layer 2〇3, and the day/day are engraved. Thereby, a trench having an opening 207 and a bottom region Z11 is formed. In Fig. (D), a dielectric layer 213 is deposited to cover the trench and the mask layer m, and fills the opening 207. Subsequent to the process, a portion of the dielectric layer 213 is removed to obtain an insulating region, as shown in Fig. (E). Removing the mask layer 2〇5 can be obtained as shown in the second figure (7): removing the pad oxide layer 203 and forming a gate erbium oxide, and simultaneously, the gate oxide layer 231 and the insulating region 223 An enamel layer (poly_1) 233 is formed thereon as shown in the second diagram (g). The structure shown in the second figure (H) can be obtained by chemical and mechanical polishing. In the second figure (1), the portion of the insulating layer 1 is partially engraved with the side wall of the polycrystalline (tetra) 233. At this time, a sidewall layer 200814238 (spacer iayer) 241 is deposited to obtain the illustrated structure. The first structure I 5 is sequentially generated by a second and a passive conductive (P〇ly-3), and the stacked gate of a flash memory unit is shown, as described in the second figure (K) HJ. Conventional techniques in the processing of flash memory stacks have attracted self-aligned stack gate production = ringing can increase the coupling ratio (c〇upHngrati〇) to drop: 'align ί in practical applications, such Although the conventional structure disclosed in the prior art can achieve a high coupling ratio, the stacked gate cell walls (Spacer) as shown in Figure-J (J) and Figure 2 (L) The structure is slid across the STI shallow trench isolation, and the reduction of the structure is the most unfavorable. In view of the people of the month, I have carefully studied and applied it to the method of manufacturing the non-volatile memory. In addition to providing a high coupling ί nrratio stack gate structure, the invention of operating power is reduced. Refers to the development of the miniaturization 'actually - not many [inventive content] of some features of the 乂 section, other features will be described in the following:: additional application - ^ The main purpose of this case is to provide a non-volatile application Memory 200814238 Self-aligned stack gate manufacturing method. In addition to the stacking gate of the coupling ratio, which can be used to reduce the operating voltage, it is more conducive to the miniaturization of the wafer size. invention. The production method is a self-aligned stacking gate, and the method comprises the following steps: a) providing a substrate; b) sequentially forming a first-dielectric layer on the substrate; a conductive layer and a mask g; c) partially etching the mask layer, the first conductive layer, the first dielectric layer and the substrate to form a shallow trench; d) using a second dielectric layer Filling 4 shallow trenches to form a shallow trench isolation (sal 1 (10) (9) STI) unit, and removing the mask layer; e) fully forming: a second conductive layer; f) partially etching the second conductive layer Forming a sidewall on the first conductive f; S) partially removing the shallow trench isolation unit to expose a portion of the second conductive layer and sidewalls of the first conductive layer; (8) sequentially depositing a third The self-aligned stacked gate is obtained by the dielectric layer and a third conductive layer; and the third conductive layer is partially etched. • According to the present concept, the substrate is a germanium substrate. According to the present invention, the substrate further has a source/drain active region. According to the present invention, the first dielectric layer is a gate layer. According to the present invention, the first conductive layer is a floating gate unit polycrystalline layer. According to the present invention, the mask layer is a tantalum nitride layer. According to the present invention, wherein the step b) further comprises the step of: thermally oxidizing the substrate to form the first dielectric layer; b2) depositing the first conductive layer on the first 200814238::: The layer; and the mask layer is redeposited on b3. Brother v electric layer. Imagine that the second dielectric layer is a deposition-isolated oxygen full-tit ΐ conception wherein the step d) further comprises the step of: dl) W ® α-Bei Di Di dielectric layer to fill the shallow trench, and Cover the cover

And d2) planarizing the second dielectric layer until the surface of the mask layer is exposed, and d3) removing the mask layer. The case concept 'where the step d2) is - chemical mechanical polishing or an etching process. 1 Guarantee According to the concept of the case, the side wall polycrystalline germanium layer. A conductive layer is a floating gate single. According to the present invention, the third dielectric layer is an oxide/nitride/oxide (0Ν0) layer.

According to the present invention, the third conductive layer is - a controlled closed polycrystalline ostrich. A further object of the present invention is to provide a self-aligned stacked gate for use in non-volatile memory. By placing the sidewall unit on the conductive gate to obtain a stack structure with a high coupling ratio (c〇uplingrati〇') to reduce the operating voltage, the wafer size is further reduced. Development is a rare invention. To achieve the above objective, the present invention provides a self-aligned stacked gate comprising a semiconductor substrate; a first dielectric layer disposed on the semiconductor substrate; and a first conductive gate disposed in the first dielectric region a side wall unit, disposed on both sides of the first conductive gate, and covering the first conductive gate of 12 200814238 1 to form a floating gate unit; a shallow trench isolation (shallow trench isolati〇n , STI) unit is disposed on both sides of the word; an oxidized dielectric layer covers the surface of the shallow trench isolation (4) gate unit, and is in contact with the sidewall of the sidewall unit and a portion of the gate; and—control gate Formed on the deuteration layer; over the layer of the pen to form the self-aligned stack gate. According to the present invention, the semiconductor substrate is a germanium substrate. The present invention contemplates that the semiconductor substrate further has a source//and an active region. Floor. According to the present invention, the first dielectric layer is oxidized by a gate. According to the present invention, wherein the first conductive gate is conceived by a polysilicon structure, wherein the sidewall unit is composed of polysilicon. Composition of layers. Jiupingmu Isolation is composed of a deposited oxygen according to the present invention, in which the oxide ~ nitride/oxide (0N0) layer is formed.乳 Nitrile rolling conception where the control gate consists of polycrystalline germanium. According to the present invention, the side wall of the single electric gate is projected within the projected area. The invention is not limited to the features described above. This issue = described below. The present invention is based on the appended claims. The embodiment of the present invention is to explain the present invention, but the present invention is not limited to the specific materials, and the invention is defined by the scope of the appended patent application. Steps or dimensions. This dtl third figure (Α) to the third figure (7), which reveals the case - preferably: for example: the second: the schematic diagram of the manufacturing process of the stacked gates. The first step is 'F '## - substrate 3, and the substrate: 1 electrical layer 32, a first conductive layer 33 and -f first dielectric layer 32 in this embodiment is - ° ° eight can be oxidized by a thermal oxidation process high temperature The oxide layer of the thickness of the plate 31. The first conductive layer 33 is used for the wide-gated gate unit, and may be an inherent polycrystalline stone ^ ° ^ (conf〇rmal deposlti〇n proc^ss) ^^ <<LpcvD„ A. The conductive layer 33 can also be deposited by non-homomorphism = (n〇n-COnformal dep〇siti〇n can be used for the production of non-cuffed or known to be invented. As for oxymtnde, SxON) or other materials Composition; can be deposited as polycrystalline germanium thickness by chemical phase deposition (CVD) or other processes to withstand subsequent oxidative etching. n and ping wit three figures ^ to define a mask pattern, part of the surname of the f cover layer 34, the brother-conductive layer 33, the first-dielectric layer 32 and the substrate 31 to form a shallow trench 311, the process can be formed by a semi-ditch isolation unit ("STI") technique. A suitable process has been found in the U.S. Patent No. 6,355,524 issued by Tuan et al. and approved on March 12, 2002, 200814238, ^1)_2〇〇2年1〇月

U.S. Patent Application Serial No. 1/262, 785, filed on Jan. 1, the priority of the U.S. Patent Application Serial No. </ RTI> </ RTI> </ RTI> </ RTI> Other Yang case processes are also feasible. In the embodiment of the present invention, the shallow trench is filled with a second dielectric layer 35 to form a shallow trench isolation (STI) unit 312. The detailed process is as shown in the third figure (6) of the second dielectric layer 35' to fill the shallow trench 31, ί ΓΜΡ ^, 34 ^; ? second (four) 35, until the mask layer is exposed &quot; 5 sides: Yes, the structure shown in Figure 2 (8). Wherein the second dielectric layer is an -oxide layer 'sometimes referred to as "yang", as it is a sulphur dioxide in some embodiments. The invention is not limited to such implementation For example, the crystallized body is completed by the above steps, and the structure shown in the second figure (E) is obtained by removing the mask layer 34. - The top surface forms a second conductive layer 36, As shown in the third figure (7), the second conductive layer 36 is used to provide a layer of the floating gate of the floating gate. The second layer is etched by an anisotropic etching process. The conductive layer 36' can form a sidewall 361 on the first conductive layer as shown in FIG. 3(G). The second etching process is performed by removing the shallow trench isolation unit from the shallow trench isolation unit. The layer 36 and the first sidewall are used to obtain a floating gate unit 33, such as a third layer, and then sequentially n dielectric layers 37 (m' and - third conductive layer 38; and partially defined - 2 (= 15 200814238 p can be paid for the self-aligned stacking pole of this case, in the case of this case, the third dielectric 屌^^(J) is shown. ((10)ide/nitride/oxide, 0N 1 is an oxygen Oxygen is - a polycrystalline stone providing a control interpole. The third conductive layer 38 is provided according to the method disclosed above, and the self-aligned stack of the θ 性 性 记 记 记 记 记 记 记 记 记 记 记 记), which reveals that the slaughter is better. The monthly reading of the four brothers (Α) Guan Tuo # ^ Mubei knows the self-aligned pile Nie

β. , and the four pictures of the younger brother (Α) reveal the self-right and projection diagram. The fourth figure (β) is revealed and the schematic view of the gate is cut. In addition, (indicated as shown in the third figure (1). If the second display = 3? The gate is included - the semiconductor wire 31 is first dielectric: =; on the 2 conductor substrate 31 ... the first - conductive closed polarity = a: a sidewall unit 361 disposed on the two sides above the gate 33 and covering the first conductive gate rh η to form a floating closed-pole unit 331, · shallow The trench isolation ihgall7Jrench isolation, STI) unit 312 is disposed on both sides of the floating giant ~ very early 331; an oxidized dielectric layer 37 covers the shallow trench spacer, the surface of the unit 312 and the floating gate unit 331, and The sidewall unit 361 is in contact with a sidewall of a portion of the first conductive gate 33; and a control gate 38 is formed over the oxide dielectric layer 37 to form the self-aligned stacked gate. In practical applications, the semiconductor substrate 31 is a germanium substrate, and further has a source/drain active region 301/302 disposed correspondingly below the self-aligned stacked gate. In addition, the first The dielectric layer 32 is a gate oxide layer; and the first conductive gate 33, the sidewall unit 16 200814238 361 and the control gate 38 can be made of polycrystalline germanium material. The shallow trench isolation is separated by - deposition oxidation The oxide dielectric layer 37 is composed of a layer of oxonium oxide (oxlde/nitride/〇xide, 雠), and the self-aligned stacked gate can be obtained by the method disclosed in the previous case, and the obtained structure The characteristics are as shown in the third figure (J), the fourth figure (A), and the fourth figure (8). In addition to the self-aligned stack gates obtained by the above method, the subsequent steps include other semiconductor manufacturing. The structure of the control gate 38 is further covered with a dielectric protective layer, and a conductive contact layer 40 is further penetrated from the top to the source/drain active region 301/302. The relative position of the contact is shown in the figure, and will not be described in detail here. The sidewall 361 included in the floating gate unit 331 of the present case is located above the first conductive closed pole 33, so it can be clearly seen from the third figure (7) that the sidewall unit 361 is included in the ^= gate Within the projected area of the pole 33. Compared to the prior art, the projection surface formed by the floating gate unit of oxygen is not as conventionally known as the electric gate plus the side wall. Although the prior art is as shown in the first figure &amp; The conductive interpoles shown in Figure 2-7 are identical to the floating gates of this case: they are increased by the reference of the spacer structure (upl lng rat 10). However, due to the floating poles of the prior art The STi &amp; trench isolation (four) is constructed. Therefore, the skill of using the =iSTi shallow trench isolation structure to achieve miniaturization of the wafer line size will be limited by the STi shallow trench isolation structure. : Since the quasi-stacking pole structure, except for the first figure, only the seven coupling ratio (couplingratio) can be used to reduce the operating voltage of 200814238. Since the sidewall structure of the case (4) is located above the floating gate, this case STI shallow trench isolation structure can be reduced to reach the wafer line ruler In summary, the present invention provides a method for manufacturing self-aligned stacked gates in non-volatile memory, which can be used to facilitate the development of wafer line miniaturization by a combination of simple processes. The resulting self-aligned stacked gate structure, in addition to increasing the coupling ratio and lowering the operating voltage, contributes to the development of wafer size miniaturization, which is not possible with conventional techniques. The technology is practical, novel and progressive, and the application is made according to the law. Even though the invention has been described in detail by the above embodiments, it can be modified by those skilled in the art, and the application is not excluded. The scope of the patent is intended to protect. 200814238 [Simple description of the drawings] The first figure (A) to the first figure (1): it discloses a schematic diagram of the manufacturing process of the stacked gate of a conventional element. Bamboo Flash Memory Single Picture (A) to Figure 2 (K) ···························· The conventional flash memory unit is shown in FIG. 3(A) to FIG. 3(J), which is a schematic diagram showing the flow of the method for manufacturing the stacked gates according to a preferred embodiment of the present invention.

In the fourth picture (A) and the fourth picture (b), the straight Fu Tai is aligned with the stack gate. Description of the self-primary components of the preferred embodiment of the present invention 100 102 104 106 110 112 114 116 118 120 120a 122 124 126 201 • Substrate: First dielectric layer: Conductive layer • Nitride layer: Photoresist layer: Ditch: Pad oxide layer: oxide layer • insulating layer: conductive material layer • conductive sidewall layer • first gate conductive layer: second dielectric layer: second gate conductive layer • hair substrate 200814238

203 205 207 213 213 223 231 233 241 243 245 301/302 31 311 312 32 33 331 34 pad oxide layer open layer bottom area dielectric layer insulation area gate oxide layer polysilicon layer sidewall layer side layer layer source / Bungee active area substrate shallow trench shallow trench isolation unit first dielectric layer first conductive layer floating gate unit mask layer 35: second dielectric layer 36: second conductive layer 361 37 38 39 sidewall third dielectric layer Third conductive layer dielectric protective layer conductive contact layer 20 40

Claims (1)

200814238 X. Patent Application Range: 1 · A self-aligned stack gate manufacturing method comprising the following steps: a) providing a substrate; b) sequentially forming a first dielectric layer and a first conductive layer on the substrate a layer and a mask layer; c) partially etching the mask layer, the first conductive layer, the first dielectric layer and the substrate to form a shallow trench; d) filling with a second dielectric layer The shallow trench is formed by a shallow trench is〇lati〇n (STI) unit, and the germanium mask layer is removed, and a second conductive layer is formed. The second conductive layer is formed on the first conductive layer to remove the shallow trench isolation unit to expose a portion of the second electrical layer and the sidewall of the first conductive layer; h) sequentially depositing a third dielectric layer And a third conductive reed; a gate electrode. Partially etching the third conductive layer ' can be obtained from the "quasi-stack 2" - the manufacturing method described in the first item, wherein the substrate 3 is: 1 There is a patent = the manufacturing method described in Item 1, which has a source/drain active region. Soil low ^ The dielectric layer as described in the scope of the patent application is a gate oxide layer. "Where to go, the first 5 guides and two applications: the manufacturing method described in the first paragraph of the patent range, wherein the driving layer is a 1-layer gate unit polycrystalline germanium layer. - A. Zhuo - 21 200814238 The manufacturing method of claim 1, wherein the mask layer is a layer of nitride. The manufacturing method of claim 1, wherein the step b) further comprises the steps of: bl) thermally oxidizing the substrate to form the first dielectric layer; b2) depositing on the first dielectric layer The first conductive layer; and b3) redepositing the mask layer on the first conductive layer: 2, the manufacturing method described in claim 1 wherein the step c) is an anisotropic etch. The manufacturing method of claim 1, wherein the second private layer is a deposition isolation oxide layer. The method of claim 2, wherein the cover deposits a second dielectric genus to fill the trenches and cover the surface; The mask layer is removed by exposing the mask layer d3). 11. The manufacturing method / step d2) as described in claim 1 is a chemical mechanical polishing or an inscription process. 12. The manufacturing method described in claim i—the V electrical layer is a floating gate unit sidewall polysilicon layer. The manufacturing method described in the first aspect of the patent application. drawer. The electric layer is oxide/nitride/oxide (0N0). 14. The manufacturing method according to claim i, wherein the second conductive layer of the 200814238 is a control gate polysilicon layer. . 15· A self-aligned stacked gate comprising: a semiconductor substrate; a dielectric layer disposed on the semiconductor substrate; a first conductive gate disposed on the first dielectric region; Provided on both sides of the first conductive gate and covered on the first conductive gate to form a floating gate unit; one shallow trench isolation (shallow trench is〇lati〇n, the lamp is set on the floating The two sides of the gate unit; an oxygen dielectric layer covering the shallow trench isolation unit and the floating interlayer and the side of the sidewall unit and a portion of the first conductive gate are formed on the oxide dielectric Above the layer 'to form the self-aligned stacking of the semiconductor substrate as described in item 15 of the patent application, the semiconductor substrate is a substrate. L7: self-pairing according to item 15 The quasi-stacking gate further has a source/drain active region. The pole 19·pole 20. The pole 21· pole 151 The self-aligned stack described in the shell, wherein the dielectric layer is a gate oxide layer Self-aligned stacking as described in item 15 of the patent application scope The first conductive gate is composed of a polycrystalline germanium. If the application is made of a special material, the side wall unit is composed of a polysilicon. The 竿隹I gate is as self-right, as described in item 15 of the application (4). The shallow trench isolation unit is composed of a -deposited oxide layer. And 200814238 22. The self-electrode according to claim 15 wherein the oxide dielectric layer is made of an oxide/nitride/oxide 23. The layer is composed of a layer of 23. The self-polarization described in claim 15 wherein the control gate is composed of a polycrystalline crucible. ι闲24. Self-polarization as described in claim 15 Wherein the sidewall unit is included in the first product. twenty four