1310959 九、發明說明： 【菊^明戶厅廣 喝气技術領域；1 【發明領域】 本心月係有關於-步進機中之晶圓上積體電路的製 & °具體^ ’本發明係關於用來對準—步進格和一晶圓 的精細對準標記之配置。 C先前】 【發明背景】 10 積體電路型板(dle)係利用眾所熟知的技術(諸如光刻） 在石夕晶圓上-齊製造的。利用這些技術，可將該積體電路 型板之一特定層中定義元件和互連之尺寸和形狀的一圖樣 印於該晶圓上。印於該晶圓上的圖樣係佈置成一陣列或矩 陣的標線片（reticle)影像。一晶圓步進機將該圖樣支撐於〜 15 晶圓上方，並將該標線片之圖樣影像透過一透鏡投射於兮 晶圓上。該影像投影至該晶圓上的區域即定義為一步進格 現在請參考先前技藝的圖1，圖中顯示一步進機 側視圖。步進機100包含一光源122、遮罩葉片124、〜棒後 片126、一透鏡128以及一平台112。該光源122將光線穿遠 過遮罩葉片124之一開口 126a，再穿過標線片126上的〜韵 圖 樣126a的透明部份，再透過透鏡128投射於該平台112上的 晶圓133。藉此方法，即可將該標線片126的圖樣126a複製 於該晶圓133上，一般係採5 : 1的縮尺。位於該標線片126 之内部或中央部份的一圖樣通過透鏡128之一中失部_^八 128a。同樣地，位於該標線片126之外圍或邊緣部份的〜圖 20 1310959 樣126b通過透鏡128之—外圍部份隱。 積體電路係實質上藉於該晶圓133上形成許多互連之 層膜’-層一層地構建起來的。由於這些層膜係互相連接， 故有必要確保晶圓I33上的各層圖樣係實際上精確地定位 5並成形的。傳統方法依賴該晶圓133、該平台112、該透鏡 128及該‘線片126的精確_準，以精確地製成—積體電路。 有幾個引發誤差的變數可影響使用光刻法時，一晶圓 上-影像之精確形成。這些變數包含旋轉對準誤差、轉換 對準誤差以及透鏡失真誤差等等。以上三種引發誤差的變 H)數，皆可由該步進機的一不同部份修正。最好能將不同種 類的誤差隔離’並分別獨立量測，使不至出現令人困擾的 誤差量測，且對每一變數產生的修正不至於互相抵觸而產 生不良後果。 由標線片126相對於該晶圓133的旋轉動作（反之亦然） 15所引發的旋轉對準誤差，係此處所特別要討論的。如上所 述，最好將旋轉誤差與其他引發誤差的變數隔離，以補償 旋轉誤差的實際尺寸。 參考先刖技藝圖2A，其中顯示—晶圓133和一步進格的 俯視圖，錢器的前、後側係分別以箭頭3〇和32表示。對 20準標記14和16置於該晶圓133上，以確保積體電路形成之 前，該晶圓133及該檁線片126(第的最終對準正確。該 對準標記14和16係位於一步進格12的刻劃線區域中。一步 進格12可能係由多個積體電路型板或單一型板所構成。在 整個晶圓133曝光前，需產生多個步進格。 1310959 先引技*圖2A„兒明了一種僅利用兩個對準標記μ和】6 =配置方式。對準標記14係用來取得y方向的偏移量，而對 準標記關_來取得x方⑽偏移量。在該㈣技藝中， 5 10 15 對準標記14和16與㈣計(如控餘體申所定 義的）位置或 !向_偏差係轉為-轉換誤差，但實際上它可能係-方疋轉誤差或上透鏡失真誤差。 在先刚技藝中為執行一旋轉誤差之量測，需要一額外 的對準心。己18，如先前技藝圖2B中所示。先前技藝的設計 準則指定，對準標記18必須位於其y座標不致妨礙y方向量 、仏號(如對準心心句之處。結果，對準標記μ和對準標記 18並互相對準’且其y方向間隔—偏移量2〇。量測偏移量 2〇的量，以判定其旋轉誤差的量。亦即，例如在沒有旋轉 誤差的狀況中，已知偏移量20的量。若將步進格12順時針 轉動’偏移量2G的量會依據此轉動量而增加，而其增加 則可轉換成旋轉誤差的尺寸。 因此’在先前技藝中若要判定旋轉誤差的量，必須檢 視所有三個對準標記14、16和18的位置’並量測其與預計 位置間的誤差值。在某些步進機的實例中，為獲得所需量 測值以判定旋轉誤差，而檢視多個步進格的標記位置^ 此，對每—晶圓必須多次檢視對準標記14、16和18並量' 其位置。檢視這些標記、獲得量測值並計算旋轉誤差所2 的時問與處理的功夫，將限制該步進機的生產率。 而 另外，用來檢視標記Μ、16和18的對準鏡必須適㈣ 焦，以用必要的精度檢視標記，才能計算旋轉誤差。二: 20 1310959 母片晶圓進行此錄古两# Λ , a π Α 。，、，、動作，或依據其他頻率（如每隔—# 曰日®—次、每五片曰 ^ ^ 日日圓―二人...等）。無論在任何速率之下， ^動作所需的時間部將進-步限制該步進機的生產率。 旋轉誤1的=:::當=積體電路製造程序中的 X糸4>。同時亦需要有能滿足上 盖牛且能“㈣及處科__種方法和 善步進機的生產率。 从改 【發明内容】 【發明概要】 10 15 本發明的一項目標係為上述需求提供一新賴的解決方 法，以及-種能適當補償積體電路製造程序中的旋 的方法和/或系統。本發明同時亦提供能滿足上述需求，且 能即痛量測及處理時問的-種方法和系統，以改善步進機 的生產率。 進機 根據第-項觀點，本發明提供一種每一步進格使用四 個精細對準標記的方法和系統，以製造積體電路。根 二項觀點，本發明提供—種每一步進格具有四個精細對準 標記的晶圓。根據另-項觀點，本發明提供—種標線片， 用以在該晶圓上形成該四個對準標記。 适四個對準標記係形成於一四邊形步進格每一邊的刻 劃線中。根據本發明，在該步進格對邊上的對準標記係位 於鏡射影像的位置。在-項具體實施例巾，形或矩來 的步進格的對準標記係位於該步進格之每一邊的中\點。在 另-項具體實施例中，對準標記係位於該步進格的每一角 20 1310959 落上。 在—項具體實施例中’每一對準標記皆包含複數個具 有才曰疋尺寸（如長及寬)之矩形。在一項具體實施例中，對準 標記係利用一正抗蝕程序形成，因此將由一明亮底色中的 5實心（例如鉻)矩形構成。在另一項具體實施例中，對準標記 係利用—負抗蝕程序形成，因此將由其中含有矩形窗口（例 如非鉻區域）的一深暗底色(例如鉻）背景構成。 因相鄰步進格之刻劃線重疊，故於—步進格中形成的 弟一對準標記將與前一步進格中形成的一第一對準標記 1〇重疊(例如，―第—步進格中的—右側對準標記將與相鄰步 進格中的一左側對準標記重疊）。在無旋轉誤差（步進格相對 於曰B圓無旋轉）的狀況下，第一與第二標記將會對齊，且構 成該對準標記的矩形將維持其指定尺寸。 另一方面，在步進格相對於晶圓旋轉的狀況下，相鄰 15步進格中的第一與第二標記將無法對齊，且構成這些標記 的矩形尺寸將依據旋轉的量而以一量調整。換言之若為 乾淨底色中的實心矩形，則這些矩形的寬度將依據該旋轉 誤差的量以-量縮減。而若為深暗底色中的明亮矩形，則 這些矩形的寬度將依據該旋轉誤差的量以一量增加。 2〇 然、而，依據本發明，就該步進格相對於該晶圓繞著其 中心旋轉的狀況而言（反之亦然），這些矩形的中心線及其對 準才示δ己即使故旋轉亦將維持不變，從而補償了旋轉誤差而 不茜量測因此’本質上旋轉誤差的作用已被依據本發明 的該四個對準標記的配置所抵消（補償）。 1310959 就該步進格繞著其一邊的中心旋轉(例如，繞著其該步 進格的左側中心）的狀況而言，其旋轉誤差已縮減了一半。 因此，依據本發明，此後面的旋轉誤差狀況已縮減至最小， 從而將消耗較小的預定重疊需求。 5 因此，依據本發明，由重疊相鄰步進格之對準標記所 產生的對準標記將能補償繞著一步進格之中心旋轉的作 用。結果，已不需再檢視這些對準標記以判定旋轉誤差， 因地節省了時間並減少處理的功夫，從而增加步進機的生 產率。另外，由於本發明的對準方法係每一步進格使用四 10 個對準標記，故能相對於傳統方法提高製造程序的精度。 【圖式簡單說明】 參考較佳具體實施例的詳細說明及附圖後，熟悉技藝 人士將可更明白本發明這些及其他目的及優點。 第1圖為導入本發明之一項具體實施例的一步進機之側視 15 圖； 第2A及2B圖為依據先前技藝之對準標記的配置； 第3圖為依據本發明之一項具體實施例之步進機的方塊 圖； 第4 a圖顯示依據本發明之一項具體實施例的積體電路 20 型板之一般佈置； 第4b圖為依據本發明之一項具體實施例的對準標記之配 置； 第4c圖為依據本發明之另一項具體實施例的對準標記 之配置； 10 1310959 第5圖為依據本發明之一項具體實施例的一對準標記 中的標記圖樣； 第6a圖描述依據本發明之一項具體實施例的一不具旋 轉誤差的對準標記； 5 第6b圖描述依據本發明之一項具體實施例的一對準標 記，其係繞著一步進格的中心作順時針旋轉； 第6 c圖描述依據本發明之一項具體實施例的一對準標 記，其係繞著一步進格的左側中心作順時針旋轉； 第7圖為依據本發明之一項具體實施例的在一晶圓上 10 形成對準標記之步驟流程圖；以及 第8圖為依據本發明之一項具體實施例的具有對準標 記之晶圓的俯視圖。 【實施方式1 【較佳實施例之詳細說明】 15 現在將藉由本發明的較佳具體實施例並參考附圖來詳 細說明本發明。雖然配合較佳具體實施例來說明本發明， 然而應瞭解，這些具體實施例並不是用來限制本發明的。 相反地，本發明乃是用來涵蓋替代、修改與同等物，其可 包括在隨附的申請專利範圍所定義之本發明的精神及範疇 20 内。另外，在以下本發明的詳細說明中，將會陳述許多特 定的細節，以提供對本發明全面性的暸解。但是，熟知技 藝人士應明瞭，在不運用這些特定細節的情況下，仍然可 實施本發明。在其他的例子中，並未詳紙說明已知方法、 程序、元件及電路，以免不必要地混淆本發明的觀點。 1310959 以下之咩細說明中，部份係以程序、還輯方塊、處理 及其他對作業象徵性之陳述表現，以描述一晶圓上製造積 體電路的方法。這些說明和表示方式係熟悉此項晶圓製造 技藝人士所常用，以最有效地對其他熟悉技藝人士傳達其 5要義者。本申請書中認為，一程序、邏輯方塊、方法等等 係一完整連貫之步驟或指示，以獲得一理想結果。其進行 步驟要求對實質數量進行物理的操作。通常（雖非必然地) 這些數置係以一電腦系統中能儲存、傳送、合併或以其他 方法操縱的電或磁性信號的形式表現，以製造一積體電路。 10 然而應記住，這些及其他類似術語宜配合適當實質數 里’且純粹係應用於此類數童的方便陳述符號。除非下文 中明確地以不同方式描述’否則應明白，本發明中使用諸 如「獲得」、「執行」、「形成」、「重疊於」等術語之討論， 皆係關於積體電路製造的動作及程序（例如，第7圖之程序 15 700)。 請參考第3圖，其中顯示依據本發明之一項具體實施例 的一步進機2〇2之一方塊圖。步進機2〇2包含與一平台動作 裝置210耦合的一平台208、一處理器212、一信號收發器204 以及一記憶體214。晶圓206係置於平台208上.，以在步進 20機中接受處理。 s己憶體214包含的程式指令可透過處理器212執行。記 憶體214可為諸如唯讀記憶體(R〇M)之永久記憶體，或諸如 吸機存取記憶體(RAM)之暫時記憶體。記憶體214亦可為任 何其他形式’能包程序指令的記憶儲存裝置，諸如一硬式 12 1310959 磁碟、一CDROM或快門記憶體。程序212可為一現存之系 統處理器或微處理器、一專用於數住信號處理(digita丨signal procesing，DSP)之處理器單元，或一專用控制器或微控制 器。或者’亦可用一狀態機（state machine)以執行這些程序 5 指令。 信號收發器204係與處理器212耦合。信號收發器204 係諸如一雷射之一輻射電磁光束之來源。另外，信號收發 器204係一電磁信號（諸如自晶圓2〇6反射之返回光束）之一 接收器。 10 第4A圖顯示一晶圓（如第3圖之晶圓206)上的單一積體 電路型板元素400的一般配置。型板元素4〇〇雖係繪成方 形，應明瞭型板元素400亦可為矩形。型板元素4〇〇包含積 體電路型板401，其係由一輸入/輸出（1/〇)觸點區（pad area)402、一防護環（gUar(j ring)4〇3以及一刻劃線4〇4所環 15繞。該刻劃線404包含在一晶圓上生產積體電路型板時使用 的插入物與量產標號(例如，第4B或4C圖中的對準標號）。 當型板元素400在製造時於該晶圓2〇6中各處產生時，該刻 劃線404亦在各處形成邊與邊重疊、頂與底重疊的現象。換 言之，某一步進格中刻劃線之一部份會和其鄰近步進格中 20刻劃線之一部份重疊。例如，一第一步進格之一刻劃線之 右側部份’會與其相鄰步進格之刻劃線之左側部份重疊。 第4B圖顯示依據本發明之一項具體實施例的一晶圓 206上一步進格410中的對準標記42〇a、420b、43〇0〇43〇b 之配置。步進格410雖係繪成方形，應明暸步進格41〇亦可 13 1310959 為矩形。對準標記420a、420b、430a和430b係配置於步進 格410之刻劃線中（如第4A圖之刻劃線404)。熟悉技藝人士 應明瞭，第4B圖所描繪之對準標記的配置方式亦符合用以 形成晶圓206上之步進格41 〇中的對準標記420a、420b、430a 5和430b的一標線片上之一標記圖樣。 參考第4B圖，對準標記420a和420b係位於步進格410 之相對邊上，且係位於鏡射位置。在本發明中，對準標記 420a和420b係位於步進格410之相對邊的中點位置。同樣 地’對準標記430a和430b係位於步進格410之另二相對邊的 10 鏡射位置上。在本發明中，對準標記430a和430b係位於步 進格410之對邊的中點位置。應明瞭，在其他具體實施例 中，對準標記420a、420b、430a和430b亦可配置於其他不 同於步進格410之各邊之中點的位置，只要對準標記42如和 420b係位於相對邊上的鏡射位置’且對準標記43〇a和430b 15 係位於另二相對邊上的鏡射位置即可。 第4C圖為依據本發明之另一項具體實施例的對準標記 440a、440b、440c和440d之配置。在此具體實施例中，對 準標記440a、440b、440c和440d係配置於步進格41〇的四個 角落上。 20 參考第4A、4B和4C圖’當型板400在晶圓2〇6中各處產 生時’各步進格410的刻劃線404亦被其相鄰步進格重疊， 如上所述。因此，刻劃線404中的對準標記亦將與一相鄰步 進格的一對準標記重疊。例如，一第一步進格中的對準標 記430b會與下一相鄰步進格（在第一個步進格右側）中的對 14 1310959 準標記430a重疊。 吾人將發現，使用四個對準標記，以及其在一步進格 之刻劃線中以鏡射位置配置的方式，提供了一有效且精確 的方法及系統以隔離並補償旋轉誤差（參考下第6a至6C 圖）。另外，每一步進格使用四個對準標記將可提昇該對準 程序的精度。再者，如本發明中所述地配置四個對準標記， 亦可平衡或降低透鏡失真誤差。 第5圖顯示依據本發明之一項具體實施例的一對準標 5己（如第4B和4C圖的標記）中的標記圖樣500a和500b。該標 1〇記圖樣500a包括在一明亮底色512中複數個之實心（一般為 鉻）矩形510。該標記圖樣5001?包括一深暗底色（一般為鉻） 背景522中的明亮矩形520。該標記圖樣5〇〇a和500b係利用 一熟知的正抗蝕程序或負抗蝕程序形成。 雖然標記圖樣500a和500b皆顯示有六個矩形，應明瞭 15依據本發明，可使用任何數目的此種矩形。再者，依據本 發明’可使用其他類型的標記圖樣及設計，由P. Leroux發 明並讓渡予本發明之受讓人的美國專利US-A 5,316,984中 描述了一個此種設計。同時應明瞭，第5圖的標記圖樣係對 應於形成步進格410(第4B和4C圖）中晶圓206上的標記圖樣 2〇 500a和500b所用的一標線片上的標記圖樣。 再參考第5圖，矩形510和520圖的尺寸係經精確指定。 一般而言，矩形510和520之寬度為4微米，長度則為30微 米。然而’這些尺寸並非本發明之重點，且亦可使用不同 之尺寸。 ί 15 1310959 〇依據本發明之—項具體實施例’第6A圖描述一標記標 號(如一矩形510)在—對準標記(如第48和4(：圖的對準標記) 的對準，且無旋轉誤差的狀況。請記得，依據本發明，一 ^進袼的對準標記將與下—相鄰步進格的對準標記重疊。 例如 第—步進格中的對準標記430b會與下一相鄰步進 格(在第—個步進格右側）中的對準標記43 0 a重疊。為方便此 处°寸’由相重豐的對準標記所形成的對準標記此後將稱 為「重疊標記」或「合成標記」。 在無旋轉誤差的狀況下，對準標記430a(位於第二步進 10格中）的枯记標號(如矩形51〇)將與對準標記430b(位於第一 y進私中）的標§己標號完全吻合。結果，該重疊標記中每一 矩开v51〇的才曰疋尺寸將不會變更(例如，每-矩开)51〇將仍為 4微米乘30微米）。結果，該重疊標記中的每-矩形510之中 心（質心）未變更，且該重疊標記的質心亦未變更。 15 *因此，依據本發明，當該重疊標記中該矩形510的尺寸 未欠更時，即表不無旋轉誤差。反之，當對準標記43〇b(來 自第-步進格)與對準標記4術(來自第二步進格)對準時， 此亦表示無旋轉誤差。因此，此處並不％要量測與計算來 判定旋轉誤差，故節省了製造與處理的時間，並提昇了該 20 步進機的生產率。 第6B圖描述依據本發明之一項具體實施例，一對準標 記(如第4B和4C_的對準標記）中的一標紀標號(如矩形51〇) 在每一步進格皆有繞其中心順時針的旋轉時之狀況。第6B 圖同時亦可描述第-步進格適當對準（無旋轉誤差）而相鄰 16 1310959 的第二步進格則繞其中心旋轉的狀況。任一種狀况的結 果，第二步進格的對準標記43〇a都不會精確地與第—步進 格的對準標記430b對準。結果，（第二步進格之）對準標記 430a之一（左側）標記標號(如矩形63〇)不會與（第一步進格之) 5對準標記430b之一（右側）標記標號(如矩形632)對準。 依據正抗蝕程序，矩形630和632重疊的結果將形成畫 斜線的矩形510。因此，該標記重疊的矩形5丨〇將具有縮小 的尺寸（亦即，其寬度將略小於4微米，依該旋轉量而定）。 然而，在旋轉繞著一步進格之中心發生的情況，矩形51〇的 10中心並未改變，因此該重疊標記的質心亦未改變。應注意， 就負抗蝕程序而言，矩形630和632重疊的結果將使矩形51〇 的尺寸增加（亦即，其寬度將略大於4微米，依該旋轉量而 定）。 因此’依據本發明’若旋轉係繞著一步進格之中心發 15生，則誠轉的作用將受到抵消（補償），因該重叠標記的質 心未改k。換e之’該重疊標記中的每__合歧形51〇之質 心，以及該重疊標記的質心，與該步進格的質心保持在同 -點。因此，該步進格的旋轉可藉尋找到訪重疊標記的質 心獲得㈣’猶如未旋轉—般。因此，此處並不需要量測 20與計异來判定旋轉誤差，故節省了製造與處理的時間，並 提昇了該步進機的生產率。 第6C圖描述依據本發明之_項具體實劇，—對準標 記(如第4Β和4C圖的對準標記）中的一標記標號(如矩形51〇) 在每一步進格皆有繞其-側邊令心順時針旋轉時之狀況。 17 1310959 第6C圖同時亦可描述(例如）第一步進格適當對準（無旋轉誤 差）而相鄰的第二步進格則繞其左侧中心旋轉的狀況。任一 種狀況的結果，第二步進格的對準標記430a都不會精確地 與第一步進格的對準標記430b對準。結果，（第二步進格之) 5對準標記430a之一標記標號（如矩形640)不會與（第一步進 格之)對準標記43 〇b之一標記標號(如矩形642)對率。 依據正抗触程序，矩形640和642重疊的結果將形成矩 形510。因此，該標記重疊的矩形51〇將具有縮小的尺寸（亦 即，其寬度將略小於4微米，依該旋轉量而定）。應注意， 1〇就負抗姓程序而言，矩形630和632重疊的結果將使矩形 的尺寸增加（亦即，其寬度將略大於4微米，依該旋轉量而 定）。 在匕狀;兄中，一步進格繞著其一邊的中心旋轉，該重 15疊軚°己中美—合成矩形510的質必將與該步進格的中心不 15同。因此該重疊標記的質心將會與該步進格的中心不同。 护此將而要量測並補償此種旋轉的旋轉誤差。然而，一 ° 、’堯著该步進格的一邊之中心旋轉並不似繞著該步 的3中心旋轉這般頻繁。再者’依據本發明’旋轉誤差 >〇耗降:了 —半。因此，此種旋轉誤差將不至明顯地消 疋重疊。因此，相對於先前技藝中較大數量的實例， ‘略轉誤差，故步進機功能將不至受其不利地影 響且能獲得改善。 〜 生因此1據本發明，若旋轉錢著—步進格之中心發 、X疑轉的作用將受到抵消(補償），因該重疊標記的質 1310959 心未改變。換言之，每一合成矩形510之質心，以及該重疊 標記的質心，與該步進格的質心保持在同一點。因此，此 處並不需要量測與計算來判定旋轉誤差，故節省了製造與 處理的時間，並提昇了該步進機的生產率。在其他實例中， 5 旋轉係繞著一步進格的一邊之中點發的生，故該旋轉誤差 的幅度已減低，因此將不至明顯地消耗預定重疊。 第7圖為依據本發明之一項具體實施例的程序700之步 驟，以於一晶圓206(第4Β和4C圖）中形成對準標記(例如第 4Β和4C圖的對準標記）。程序700之步驟的許多指令以及資 10 料的輸入/輸出都會利用到記憶體，和第3圖中顯示的控制 器硬體設備。例如，晶圓206、平台208及信號收發器204可 由記憶體214及處理器212所控制，以達成程序700中要求的 步驟。同樣可實施第3圖中的替換性具體實施例，以執行程 序700的步驟。再者，本具體實施例中的程序700雖係於一 15 步進機設備中實施，本發明亦可適用於其他需要晶圓對準 的裝置。在本具體實施例中，記憶體214中的軟體不需為程 序700修改。 本具體實施例的程序700顯示一特定順序及數量之步 驟，本發明亦適用於其他替代性之具體實施例。例如，本 20 發明亦適用於比程序700的步驟為多或少的一具體實施 例。同樣地，其步驟的先後順序可依應用而修改。再者， 雖然程序700係以單一序列程序顯示，其亦可以一連續或並 行流程實施。 在第7圖之步驟710中，步進機202接收了 一晶圓206(第 19 1310959 3圖）。 在第7圖之步驟720中（同時參考第4A、4B和4C圖），執 行了第一步進格410。依據本發明’在步進格410的刻劃線 404之内形成了四個對準標記。在一項具體實施例中，該四 個對準標記係如第4B圖所示之位置配置，換言之，對準標 記420a和420b係配置於步進格410之相對邊之鏡射位置，而 對準標記430a和430b則係類似地配置。在另一項具體實施 例中’四個對準標記係如第4C圖中所顯示的44〇a至b的位置。 在第7圖之步驟730中（同時亦參考第4A、4B和4C圖）， 10 15 20 執行了具有四個對準標記的第二步進格41〇。該第二步進格 之刻劃線404的一部份與該第一步進格之刻劃線4〇4的一部 伤重疊’使3第二步進格的—對準標記與該第―步進格的 對準仏α己重$。例如，該第二步進格之刻劃線撕的左侧 :份可與該第—步進格之刻劃線404的右側部份重疊，在此 中及第—步進格的對準標記43〇a將與該第一步進格 的對準標記430b重疊。 對準St明’若步進格無旋轉，則(第二步進格上的) 5己43%料钱_—步祕上的m標記他 進格上的）料^個步進格繞著其中‘，，則（第二步 對準標記43^7將無法精確地與（第—步進格上的） 質必將仍代料步崎X财纽象_成重疊標記的 旋轉誤差之幅 、〜' °目此’並無量測或計算該 …、，且該第二步進格的旋轉可藉找到 20 1310959 該重疊標記的質心獲得補償。 若其中一個或兩個步進格繞著其-邊的中心旋轉，則 (第二步進格上的）對準標記4鳩將無法精如也與（第一步進 格上的）對準標記挪對準。在此狀況中，該重疊現象所形 5成重疊標記的質必將因旋轉誤差而與該步進格的中心不 同’然而’該旋轉誤差的幅度將較傳統方法縮減—半。 第8圖為依據本發明之一項具體實施例的_具有多個 對準標記836之晶圓83〇的俯視圖。晶圓請係分割成數個步 進格，以步進格840代表。在第8圖巾，為說明之目的，步 10 進格850、852、860、862、870、872、88〇和882皆擁有四 個對準標記836住於其每一邊的中點上，如第4B圖所描述。 然而應明瞭，依據本發明，每一步進格84〇可有四個對準標 記836。 再度參考第8圖，僅以相鄰的步進格85〇及852作為實 15例，對準標5己836係位於步進格850的右側及步進格852的左 側。如上所述，對準標記836係由重疊步進格852的左側標 記與步進格850的右側標記而形成的。因此，對準標記836 κ際上係兩個不同步進格中形成的標記的混合物。 一般而言，當對準步進機及晶.圓時，將為該對準選擇 20某數量的步進格。典型地，可能會為對準選擇八個步進格。 然而’依據本發明，相鄰步進格共享對準標記，如先前所 述。相對地’諸如對準標記836的一標記實際上能代表兩個 步進格(如步進格850和852)。因此，依據本發明，選擇作對 準的步進格數量可縮減一半’而仍能保持目前的精度水 21 1310959 準。另一方面，若不縮減為對準選擇的步進格數量，則其 精度將可增加一倍。因此，本發明的另一項優點為：其可 合意地增加生產率而不損失精度，或提高精度而不損失生 產率。 5 因此，本發明提供一種能適當補償積體電路製造程序中的 旋轉誤差的方法和系統。本發明同時亦提供能節省量測及處理 時間的一種方法和系統，從而改善步進機的生產率。 以上即說明本發明之較佳具體實施例，一步進機對準 之自我補償標號設計。本發明雖以特定具體實施例說明， 10 然應明瞭，不應以這些具體實施例限制本發明，而應依據 隨後申請專利範圍作其限制範圍。 ί：圖式簡單說明3 第1圖為導入本發明之一項具體實施例的一步進機之側視 圖， 15 第2Α及2Β圖為依據先前技藝之對準標記的配置； 第3圖為依據本發明之一項具體實施例之步進機的方塊 圖； 第4a圖顯示依據本發明之一項具體實施例的積體電路 型板之一般佈置； 20 第4b圖為依據本發明之一項具體實施例的對準標記之配 置； 第4c圖為依據本發明之另一項具體實施例的對準標記 之配置； 第5圖為依據本發明之一項具體實施例的一對準標記 22 1310959 中的標記圖樣， 第6a圖描述依據本發明之一項具體實施例的一不具旋 轉誤差的對準標記； 第6b圖描述依據本發明之一項具體實施例的一對準標 5 記，其係繞著一步進格的中心作順時針旋轉； 第6c圖描述依據本發明之一項具體實施例的一對準標 記，其儀繞著一步進格的左侧中心作順時針旋轉； 第7圖為依據本發明之一項具體實施例的在一晶圓上 形成對準標記之步驟流程圖；以及 10 第8圖為依據本發明之一項具體實施例的具有對準標 記之晶圓的俯視圖。 【主要元件符號說明】 231310959 IX. Description of the invention: [Ji Ju ^ Ming Hall is widely used in the technical field of gas; 1 [Invention field] This is the system of the integrated circuit on the wafer in the stepper machine. The invention relates to the configuration of fine alignment marks for alignment-step cells and a wafer. C Previously [Background of the Invention] 10 Integral circuit boards (dles) are fabricated on a Shihwa wafer using well-known techniques such as photolithography. Using these techniques, a pattern defining the size and shape of the components and interconnects in a particular layer of one of the integrated circuit boards can be printed on the wafer. The patterns printed on the wafer are arranged in an array or matrix of reticle images. A wafer stepper supports the pattern over the ~15 wafer and projects the image of the reticle onto the wafer through a lens. The area onto which the image is projected onto the wafer is defined as a step cell. Referring now to Figure 1 of the prior art, a side view of a stepper is shown. The stepper 100 includes a light source 122, a masking vane 124, a rod rear panel 126, a lens 128, and a platform 112. The light source 122 passes light through an opening 126a of the mask vane 124, passes through a transparent portion of the rhyme pattern 126a on the reticle 126, and is projected through the lens 128 onto the wafer 133 on the platform 112. In this way, the pattern 126a of the reticle 126 can be copied onto the wafer 133, typically a 5:1 scale. A pattern located in the inner or central portion of the reticle 126 passes through one of the lenses 128 and is lost. Similarly, the pattern 126b located at the periphery or edge portion of the reticle 126 passes through the peripheral portion of the lens 128. The integrated circuit is essentially constructed by layering a plurality of interconnected layers of film 133 on the wafer 133. Since these layers are interconnected, it is necessary to ensure that the pattern of the layers on the wafer I33 is actually accurately positioned and shaped. The conventional method relies on the wafer 133, the stage 112, the lens 128, and the precision of the 'strip 126 to be accurately fabricated. There are several variables that cause errors that can affect the precise formation of an image on a wafer when using photolithography. These variables include rotational alignment errors, conversion alignment errors, and lens distortion errors. The above three variations of the induced error H) can be corrected by a different part of the stepper. It is best to isolate the different types of errors and independently measure them so that no cumbersome error measurements occur, and the corrections for each variable do not contradict each other and have undesirable consequences. The rotational alignment error caused by the rotational action of the reticle 126 relative to the wafer 133 (and vice versa) 15 is particularly discussed herein. As mentioned above, it is best to isolate the rotation error from other variables that cause errors to compensate for the actual size of the rotation error. Referring to the prior art Fig. 2A, in which a plan view of the wafer 133 and a step cell is shown, the front and rear side lines of the money device are indicated by arrows 3 〇 and 32, respectively. The alignment marks 14 and 16 are placed on the wafer 133 to ensure that the wafer 133 and the turns 126 are correct before the formation of the integrated circuit. (The final alignment is correct. The alignment marks 14 and 16 are located. In the scribe line region of the step block 12. A step grid 12 may be composed of a plurality of integrated circuit patterns or a single stencil. Before the entire wafer 133 is exposed, a plurality of step cells are generated. 1310959 Figure 2A shows a way to use only two alignment marks μ and 6 = configuration. The alignment mark 14 is used to obtain the offset in the y direction, and the alignment mark is off to obtain the x square (10). Offset. In the (4) technique, 5 10 15 alignment marks 14 and 16 and (4) gauges (as defined by the control body) or ! _ deviations are converted to - conversion errors, but in fact it may System-to-square error or upper lens distortion error. In order to perform a measurement of rotational error in the prior art, an additional alignment is required. As shown in the prior art Figure 2B. Prior art design The criterion specifies that the alignment mark 18 must be located at its y coordinate without obstructing the y-direction quantity and apostrophe (such as the alignment of the heart) As a result, the alignment mark μ and the alignment mark 18 are aligned with each other 'and their y-direction intervals-offset 2 〇. The amount of the offset amount 2 量 is measured to determine the amount of the rotation error. That is, For example, in the case of no rotation error, the amount of the offset amount 20 is known. If the step grid 12 is rotated clockwise, the amount of the offset 2G is increased according to the amount of rotation, and the increase is converted into a rotation. The size of the error. Therefore, to determine the amount of rotational error in the prior art, the position of all three alignment marks 14, 16 and 18 must be examined and the error value between the predicted position and the predicted position must be measured. In the example of the incoming machine, in order to obtain the required measurement value to determine the rotation error, and to view the marking position of the plurality of step grids, the alignment marks 14, 16, and 18 must be viewed multiple times for each wafer. 'The position. Viewing these marks, obtaining measurements and calculating the time and processing of the rotation error 2 will limit the productivity of the stepper. In addition, it is used to view the alignment of the marks 16, 16 and 18. The mirror must be suitable for (four) focus to view the mark with the necessary accuracy. Calculate the rotation error. 2: 20 1310959 The master wafer is used to perform the recording of the two # Λ , a π Α , , , , , or according to other frequencies (such as every -# ®日® times, every five 曰^ ^ 日日圆-二人...etc.) At any rate, the time required for the action will further limit the productivity of the stepper. Rotation error 1 =::: When = product X糸4> in the body circuit manufacturing program. At the same time, it is also necessary to have the productivity that can satisfy the upper cover cow and can "(4) and the department __ method and the good stepper.] [Invention] [Summary of the Invention] 10 15 It is an object of the present invention to provide a new solution to the above needs, and a method and/or system that can properly compensate for spins in an integrated circuit fabrication process. The present invention also provides a method and system that satisfies the above needs and can be used for pain measurement and processing time to improve the productivity of the stepper. Advancement According to a first aspect, the present invention provides a method and system for using four fine alignment marks per step grid to fabricate an integrated circuit. In the second aspect, the present invention provides a wafer having four fine alignment marks per step. According to another aspect, the present invention provides a reticle for forming the four alignment marks on the wafer. Four alignment marks are formed in the scribe lines on each side of a quadrilateral stepped cell. According to the invention, the alignment marks on the opposite sides of the step are located at the position of the mirror image. In the embodiment of the invention, the alignment marks of the step or grid of the step are located at the midpoint of each side of the step. In another embodiment, the alignment marks are located at each corner 20 1310959 of the step grid. In the particular embodiment, each of the alignment marks comprises a plurality of rectangles having dimensions (e.g., length and width). In a specific embodiment, the alignment marks are formed using a positive resist process and will therefore be comprised of 5 solid (e.g., chrome) rectangles in a bright background. In another embodiment, the alignment mark is formed using a negative resist process and will therefore be formed from a dark dark background (e.g., chrome) background containing a rectangular window (e.g., a non-chromium region) therein. Since the scribe lines overlap in the adjacent step cells, the alignment mark formed in the step block will overlap with a first alignment mark 1 形成 formed in the previous step (for example, "first" The right alignment mark in the step cell will overlap with a left alignment mark in the adjacent step cell. In the absence of a rotation error (the step lattice is not rotated relative to the 曰B circle), the first and second marks will be aligned, and the rectangle constituting the alignment mark will maintain its specified size. On the other hand, in the case where the step grid is rotated relative to the wafer, the first and second marks in the adjacent 15 step cells will not be aligned, and the rectangular size constituting the marks will be one according to the amount of rotation. Quantity adjustment. In other words, if it is a solid rectangle in a clean background, the width of these rectangles will be reduced by - according to the amount of the rotation error. If it is a bright rectangle in a dark dark background, the width of these rectangles will increase by an amount according to the amount of the rotation error. 2, and in accordance with the present invention, the centerline of the rectangles and their alignment are shown to be δ, even if the step is rotated relative to the wafer about its center (and vice versa). The rotation will also remain unchanged, thereby compensating for the rotational error without measurement so that the effect of the 'intrinsically rotational error has been offset (compensated) by the configuration of the four alignment marks in accordance with the present invention. 1310959 The rotation error has been reduced by half in the case where the step is rotated about the center of its side (for example, around the center of the left side of the step). Thus, in accordance with the present invention, this latter rotational error condition has been reduced to a minimum, thereby consuming less predetermined overlap requirements. 5 Thus, in accordance with the present invention, alignment marks produced by overlapping alignment marks of adjacent step cells will compensate for the effect of rotation about the center of a step. As a result, it is no longer necessary to examine these alignment marks to determine the rotation error, thereby saving time and reducing the processing effort, thereby increasing the productivity of the stepper. In addition, since the alignment method of the present invention uses four 10 alignment marks per step cell, the precision of the manufacturing process can be improved with respect to the conventional method. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and advantages of the present invention will become apparent to those skilled in the <RTIgt; 1 is a side view 15 of a stepper introduced into a specific embodiment of the present invention; FIGS. 2A and 2B are views of an alignment mark according to the prior art; FIG. 3 is a specific embodiment of the present invention; A block diagram of a stepper of an embodiment; FIG. 4a shows a general arrangement of an integrated circuit 20 type board in accordance with an embodiment of the present invention; and FIG. 4b shows a pair of embodiments in accordance with an embodiment of the present invention. Configuration of the quasi-marker; Figure 4c is a configuration of the alignment mark in accordance with another embodiment of the present invention; 10 1310959 Figure 5 is a mark pattern in an alignment mark in accordance with an embodiment of the present invention Figure 6a depicts an alignment mark without rotation error in accordance with an embodiment of the present invention; 5 Figure 6b depicts an alignment mark in accordance with an embodiment of the present invention, which is stepped around a step The center of the grid is rotated clockwise; FIG. 6c depicts an alignment mark according to an embodiment of the present invention, which rotates clockwise around the left center of a step cell; FIG. 7 is a diagram in accordance with the present invention. a specific embodiment In the step of forming a wafer alignment mark 10 of the flowchart; and a plan view of a wafer having alignment marks in the graph according to an eighth embodiment of the present invention is. [Embodiment 1] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail by way of preferred embodiments thereof with reference to the accompanying drawings. Although the present invention has been described in connection with the preferred embodiments, it should be understood that these embodiments are not intended to limit the invention. Rather, the invention is to cover alternatives, modifications, and equivalents, which are included within the spirit and scope of the invention as defined by the appended claims. In addition, many specific details are set forth in the Detailed Description of the <RTIgt; However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits are not described in detail to avoid unnecessarily obscuring the inventive aspects. 1310959 The following detailed descriptions are based on procedures, renditions, processing, and other representations of the symbolic representation of the job to describe the method by which an integrated circuit is fabricated on a wafer. These instructions and presentations are familiar to those skilled in the art of wafer fabrication and are most effective in communicating the five essentials to other familiar artisans. In the present application, a program, logic block, method, etc., is considered to be a complete coherent step or instruction to achieve an ideal result. Its steps require physical manipulation of the physical quantity. Usually, though not necessarily, these numbers are represented in the form of electrical or magnetic signals that can be stored, transferred, combined, or otherwise manipulated in a computer system to produce an integrated circuit. 10 However, it should be borne in mind that these and other similar terms should be used in conjunction with the appropriate substantive number and are purely applicable to the convenience statement of such children. Unless explicitly stated below in a different manner, it should be understood that the discussion of terms such as "obtaining," "executing," "forming," and "overlapping" in the present invention is directed to the operation of integrated circuit fabrication and Program (for example, program 15 700 of Figure 7). Referring to Figure 3, there is shown a block diagram of a stepper 2〇2 in accordance with an embodiment of the present invention. The stepper 2〇2 includes a platform 208 coupled to a platform action device 210, a processor 212, a signal transceiver 204, and a memory 214. Wafer 206 is placed on platform 208 to be processed in stepper 20. The program instructions contained in the suffix 214 can be executed by the processor 212. The memory 214 can be a permanent memory such as a read only memory (R〇M) or a temporary memory such as a memory access memory (RAM). The memory 214 can also be any other form of memory storage device capable of instructing program instructions, such as a hard 12 1310959 disk, a CDROM or a shutter memory. The program 212 can be an existing system processor or microprocessor, a processor unit dedicated to digits (signal procesing, DSP), or a dedicated controller or microcontroller. Alternatively, a state machine can be used to execute these program 5 instructions. Signal transceiver 204 is coupled to processor 212. Signal transceiver 204 is a source of radiation electromagnetic beams, such as one of a laser. Additionally, signal transceiver 204 is a receiver of an electromagnetic signal, such as a return beam that is reflected from wafer 2〇6. 10 Figure 4A shows the general configuration of a single integrated circuit board element 400 on a wafer (e.g., wafer 206 of Figure 3). Although the stencil element 4 is drawn in a square shape, it should be understood that the stencil element 400 may also be rectangular. The template element 4A includes an integrated circuit pattern board 401 which is composed of an input/output (1/〇) pad area 402, a guard ring (gUar (j ring) 4〇3, and a scribe The wire 4 is surrounded by a ring 15. The score line 404 includes an insert and a production number (for example, an alignment mark in FIG. 4B or 4C) used in producing an integrated circuit pattern on a wafer. When the template element 400 is produced in the wafer 2〇6 at the time of manufacture, the scribe line 404 also forms a phenomenon in which the sides overlap with the sides and the top and bottom overlap. In other words, in a certain step cell One part of the scribe line overlaps with one of the 20 scribe lines in its adjacent step grid. For example, the right part of one of the first step grids will be adjacent to its adjacent step. The left side of the scribe line partially overlaps. Figure 4B shows the alignment marks 42〇a, 420b, 43〇0〇43〇b in a step cell 410 on a wafer 206 in accordance with an embodiment of the present invention. The configuration of the step grid 410 is a square shape, it should be clear that the step grid 41 can also be 13 1310959 as a rectangle. The alignment marks 420a, 420b, 430a and 430b are arranged in the step In the scribe line 410 (such as the scribe line 404 at 4A), it will be apparent to those skilled in the art that the alignment marks depicted in FIG. 4B are also configured to conform to the step size formed on the wafer 206. One of the alignment marks 420a, 420b, 430a 5 and 430b of the enamel marks a pattern on the reticle. Referring to FIG. 4B, the alignment marks 420a and 420b are located on opposite sides of the step grid 410 and are located in the mirror. In the present invention, the alignment marks 420a and 420b are located at the midpoints of the opposite sides of the step grid 410. Similarly, the 'alignment marks 430a and 430b are located on the other two opposite sides of the step grid 410. In the present invention, the alignment marks 430a and 430b are located at the midpoints of the opposite sides of the step grid 410. It should be understood that in other embodiments, the alignment marks 420a, 420b, 430a, and 430b It may also be disposed at other positions different from the points of the sides of the step grid 410 as long as the alignment marks 42 and the 420b are at the mirror positions on the opposite sides and the alignment marks 43A and 430b are located. The other two mirror positions on the opposite side. Figure 4C is another according to the present invention. Configuration of alignment marks 440a, 440b, 440c, and 440d of a particular embodiment. In this particular embodiment, alignment marks 440a, 440b, 440c, and 440d are disposed on four corners of step block 41A. 4A, 4B, and 4C, 'When the template 400 is produced everywhere in the wafer 2〇6', the score lines 404 of the respective step cells 410 are also overlapped by their adjacent step blocks, as described above. The alignment marks in the score line 404 will also overlap an alignment mark of an adjacent step cell. For example, the alignment mark 430b in a first step cell overlaps the pair 14 1310959 quasi-mark 430a in the next adjacent step cell (on the right side of the first step cell). We will find that using four alignment marks and their mirror position configuration in a stepped line provides an efficient and accurate method and system to isolate and compensate for rotational errors (see next 6a to 6C)). In addition, the use of four alignment marks per stepper will increase the accuracy of the alignment procedure. Furthermore, by arranging four alignment marks as described in the present invention, the lens distortion error can be balanced or reduced. Figure 5 shows the marking patterns 500a and 500b in an alignment mark (e.g., the marks of Figures 4B and 4C) in accordance with an embodiment of the present invention. The standard pattern 500a includes a plurality of solid (typically chrome) rectangles 510 in a bright background 512. The marking pattern 5001 includes a dark rectangle (typically chrome) of a bright rectangle 520 in the background 522. The mark patterns 5〇〇a and 500b are formed using a well-known positive resist process or a negative resist process. Although the marking patterns 500a and 500b are all shown with six rectangles, it should be understood that any number of such rectangles can be used in accordance with the present invention. One such design is described in U.S. Patent No. 5,316,984, the entire disclosure of which is incorporated herein by reference. It should also be understood that the marking pattern of Figure 5 corresponds to the marking pattern on a reticle used to form the marking patterns 2 〇 500a and 500b on the wafer 206 in the step grid 410 (Figs. 4B and 4C). Referring again to Figure 5, the dimensions of the rectangles 510 and 520 are precisely specified. In general, rectangles 510 and 520 have a width of 4 microns and a length of 30 microns. However, these dimensions are not the focus of the present invention, and different sizes may be used. 15 15 1310959 第 In accordance with an embodiment of the present invention, FIG. 6A depicts an alignment of a label (eg, a rectangle 510) in an alignment mark (such as alignment marks of FIGS. 48 and 4). There is no rotation error condition. Please remember, according to the present invention, an alignment mark will overlap the alignment mark of the lower-adjacent step cell. For example, the alignment mark 430b in the first step cell will be The alignment marks 43 0 a in the next adjacent step grid (on the right side of the first step grid) overlap. For the sake of convenience, the alignment marks formed by the coincident alignment marks will be It is called “overlap mark” or “composite mark.” In the absence of rotation error, the dry mark (such as rectangle 51〇) of the alignment mark 430a (in the second step 10) will be aligned with the mark 430b. (The first y is in the private) the label is exactly the same. As a result, the size of each of the overlap marks in the v51〇 will not change (for example, every moment open) 51〇 will still It is 4 microns by 30 microns). As a result, the center of each rectangle 510 (centroid) in the overlap mark is not changed, and the center of mass of the overlap mark is not changed. 15 * Therefore, according to the present invention, when the size of the rectangle 510 in the overlap mark is not owed more, that is, there is no rotation error. Conversely, when the alignment mark 43〇b (from the first step grid) is aligned with the alignment mark 4 (from the second step grid), this also means no rotation error. Therefore, it is not necessary to measure and calculate the rotation error here, so that the manufacturing and processing time is saved, and the productivity of the 20 stepping machine is improved. Figure 6B depicts a standard label (e.g., rectangle 51) in an alignment mark (e.g., rectangle 51) in accordance with an embodiment of the present invention. The situation when the center rotates clockwise. Figure 6B can also describe the condition that the first-step grid is properly aligned (no rotation error) and the second step grid adjacent to 16 1310959 is rotated about its center. As a result of either of the conditions, the alignment marks 43A of the second step are not accurately aligned with the alignment marks 430b of the first step. As a result, one of the (second step) alignment marks 430a (left side) mark number (such as the rectangle 63〇) does not match the (first step) 5 alignment mark 430b (right side) mark number (such as rectangle 632) aligned. Depending on the positive resist process, the result of the overlap of rectangles 630 and 632 will form a rectangle 510 with a diagonal line. Therefore, the rectangle 5 重叠 where the marks overlap will have a reduced size (i.e., the width will be slightly less than 4 microns, depending on the amount of rotation). However, in the case where the rotation occurs around the center of a step, the center of the rectangle 51 has not changed, and thus the center of mass of the overlap mark has not changed. It should be noted that in the case of the negative resist process, the result of the overlap of the rectangles 630 and 632 will increase the size of the rectangle 51A (i.e., its width will be slightly greater than 4 microns, depending on the amount of rotation). Therefore, according to the present invention, if the rotation system is made around the center of a step, the effect of the forcing will be canceled (compensated) because the center of the overlap mark is not changed k. The centroid of each of the overlapping marks in the overlap mark and the centroid of the overlap mark are kept at the same point as the centroid of the step block. Therefore, the rotation of the step grid can be obtained by looking for the center of the overlay marker (4) as if it were not rotated. Therefore, the measurement 20 and the measurement are not required here to determine the rotation error, so that the manufacturing and processing time is saved, and the productivity of the stepper is improved. Figure 6C depicts a specific physical representation of the alignment mark (e.g., the alignment marks of Figures 4 and 4C) in accordance with the present invention. - The situation when the side rotates the clock clockwise. 17 1310959 Figure 6C can also describe, for example, a condition in which the first step is properly aligned (without rotational error) and the adjacent second step is rotated about its left center. As a result of either of the conditions, the alignment marks 430a of the second step are not accurately aligned with the alignment marks 430b of the first step. As a result, one of the (second stepped) 5 alignment marks 430a, the label number (such as the rectangle 640), does not match the label of the first step (labeled) 〇b, such as the rectangle 642. On the rate. Depending on the positive anti-touch procedure, the result of the overlap of rectangles 640 and 642 will form a rectangle 510. Therefore, the rectangle 51 重叠 where the marks overlap will have a reduced size (i.e., the width will be slightly less than 4 microns, depending on the amount of rotation). It should be noted that the result of the overlap of rectangles 630 and 632 will increase the size of the rectangle (i.e., its width will be slightly greater than 4 microns, depending on the amount of rotation). In the scorpion; in the brother, a step is rotated around the center of one side, and the weight is 15 軚 己 己 — — — — — — — — 合成 合成 合成 合成 合成 合成 合成 合成 合成 合成 合成 合成 合成 合成 合成 合成 合成 合成 510 510 Therefore the center of mass of the overlay mark will be different from the center of the step cell. This will be measured and compensated for the rotational error of this rotation. However, the center rotation of one side of the step is not as frequent as the rotation of the center of the step. Furthermore, according to the present invention, the 'rotation error> is reduced by half. Therefore, such rotation errors will not significantly eliminate overlap. Thus, the stepper function will not be adversely affected and improved as compared to the larger number of instances in the prior art. ~ Health 1 According to the present invention, if the rotation of the money - the center of the step grid, the role of the X suspect will be offset (compensation), because the quality of the overlapping mark 1310959 has not changed. In other words, the centroid of each composite rectangle 510, as well as the centroid of the overlay mark, remains at the same point as the centroid of the step. Therefore, measurement and calculation are not required here to determine the rotation error, thereby saving manufacturing and processing time and increasing the productivity of the stepper. In other instances, the 5 rotations are generated around a side of a step, so the magnitude of the rotation error has been reduced, so that the predetermined overlap will not be significantly consumed. Figure 7 is a diagram of a procedure 700 for forming alignment marks (e.g., alignment marks for Figures 4 and 4C) in a wafer 206 (Figs. 4 and 4C) in accordance with an embodiment of the present invention. Many of the instructions of the steps of program 700, as well as the input/output of the material, are utilized to the memory, and the controller hardware shown in Figure 3. For example, wafer 206, platform 208, and signal transceiver 204 can be controlled by memory 214 and processor 212 to achieve the steps required in routine 700. Alternative embodiments in FIG. 3 can also be implemented to perform the steps of program 700. Moreover, although the program 700 in this embodiment is implemented in a 15 stepper device, the present invention is also applicable to other devices requiring wafer alignment. In this particular embodiment, the software in memory 214 need not be modified for program 700. The routine 700 of the present embodiment shows a particular sequence and number of steps, and the present invention is also applicable to other alternative embodiments. For example, the present invention is also applicable to a specific embodiment that is more or less than the steps of the routine 700. Similarly, the order of the steps can be modified depending on the application. Moreover, although the program 700 is displayed in a single sequence of programs, it can also be implemented in a continuous or parallel process. In step 710 of Figure 7, stepper 202 receives a wafer 206 (Fig. 19 1310959 3). In step 720 of Fig. 7 (while referring to Figs. 4A, 4B and 4C), the first step cell 410 is executed. Four alignment marks are formed within the score line 404 of the step grid 410 in accordance with the present invention. In a specific embodiment, the four alignment marks are disposed as shown in FIG. 4B, in other words, the alignment marks 420a and 420b are disposed at the mirror positions of the opposite sides of the step grid 410, and The quasi-markers 430a and 430b are similarly configured. In another embodiment, the four alignment marks are the positions of 44〇a to b as shown in Figure 4C. In step 730 of Figure 7 (also with reference to Figures 4A, 4B and 4C), 10 15 20 performs a second step grid 41 with four alignment marks. A portion of the second stepped line scribe 404 overlaps with a portion of the first step of the scribe line 4 〇 4 'the alignment mark of the 3 second step grid and the first ―The alignment of the step grid 仏α has been weighted by $. For example, the left side of the second stepped cell is torn to the left side of the scribe line 404, and the alignment mark of the first step cell 43〇a will overlap the alignment mark 430b of the first step cell. Align St Ming' if there is no rotation in the step grid, then (on the second step grid) 5 has 43% of the money _—the m on the step is marked on the grid. Where ',, then (the second step of the alignment mark 43^7 will not be able to accurately match the (the first step on the grid) quality will still substituting the step by step X _ _ into the overlapping mark of the rotation error ,~°°°This does not measure or calculate the ..., and the rotation of the second step can be compensated by finding the centroid of the overlap mark 20 1310959. If one or two of the step marks are wound With the center of its edge rotated, the alignment mark 4 (on the second step) will not be exactly aligned with the alignment mark (on the first step). In this case, The overlap of the five-fold overlapping mark must be different from the center of the stepped cell due to the rotation error. However, the magnitude of the rotation error will be reduced by half compared with the conventional method. FIG. 8 is a diagram according to the present invention. A top view of a wafer 83 having a plurality of alignment marks 836 of a specific embodiment. The wafer is divided into a plurality of step cells, represented by a step grid 840 In the eighth figure, for the purpose of explanation, step 10, 850, 852, 860, 862, 870, 872, 88, and 882 each have four alignment marks 836 living at the midpoint of each side thereof, such as It is to be understood from Fig. 4B. However, it should be understood that, in accordance with the present invention, each of the step grids 84A can have four alignment marks 836. Referring again to Fig. 8, only the adjacent step blocks 85 and 852 are used as the real 15 For example, the alignment mark 836 is located on the right side of the step grid 850 and on the left side of the step grid 852. As described above, the alignment mark 836 is marked by the left side of the overlapping step grid 852 and the right side of the step grid 850. Thus, the alignment mark 836 κ is a mixture of marks formed in two different step cells. In general, when the stepper and the crystal are aligned, 20 will be selected for the alignment. A certain number of step grids. Typically, eight step grids may be selected for alignment. However, in accordance with the present invention, adjacent step grids share alignment marks as previously described. Relatively 'such as alignment marks A mark of 836 can actually represent two step cells (such as step blocks 850 and 852). Therefore, in accordance with the present invention, The number of stepped cells can be reduced by half' while still maintaining the current accuracy of 21 1310959. On the other hand, if the number of stepped cells selected is not reduced, the accuracy will be doubled. Another advantage of the present invention is that it can desirably increase productivity without loss of precision, or improve accuracy without loss of productivity. 5 Therefore, the present invention provides a method capable of appropriately compensating for rotational errors in an integrated circuit manufacturing process. And the system. The present invention also provides a method and system for saving measurement and processing time, thereby improving the productivity of the stepper. The above is a preferred embodiment of the present invention, a stepping machine alignment self-compensation label design. The present invention has been described with respect to the specific embodiments thereof, and it should be understood that the invention should not be construed as limited by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a side view of a stepper incorporating a specific embodiment of the present invention. 15 FIGS. 2 and 2 are diagrams showing the arrangement of alignment marks according to the prior art; FIG. 3 is based on A block diagram of a stepper according to an embodiment of the present invention; FIG. 4a shows a general arrangement of an integrated circuit type board according to an embodiment of the present invention; 20b is a diagram according to the present invention. Configuration of the alignment mark of a specific embodiment; FIG. 4c is a configuration of an alignment mark according to another embodiment of the present invention; FIG. 5 is an alignment mark 22 according to an embodiment of the present invention. a marking pattern in 1310959, Figure 6a depicts an alignment mark without rotation error in accordance with an embodiment of the present invention; Figure 6b depicts an alignment label 5 in accordance with an embodiment of the present invention, Rotating clockwise around the center of a stepped cell; Figure 6c depicts an alignment mark according to an embodiment of the present invention, the instrument rotating clockwise around the left center of a stepped cell; 7 is based on the present invention A flow chart of the steps of forming alignment marks on a wafer in one embodiment; and FIG. 8 is a top plan view of a wafer having alignment marks in accordance with an embodiment of the present invention. [Main component symbol description] 23