JPS6350852B2 - - Google Patents
Info
- Publication number
- JPS6350852B2 JPS6350852B2 JP18046583A JP18046583A JPS6350852B2 JP S6350852 B2 JPS6350852 B2 JP S6350852B2 JP 18046583 A JP18046583 A JP 18046583A JP 18046583 A JP18046583 A JP 18046583A JP S6350852 B2 JPS6350852 B2 JP S6350852B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- mask
- resist
- exposure
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000011161 development Methods 0.000 description 6
- 238000005259 measurement Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000000386 microscopy Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体装置の製造方法に関し、更に詳
しくは現像レジストパターンの適正度を極めて容
易に判別し、正確に転写されたパターンを得るよ
うにした半導体装置の製造方法に関する。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for very easily determining the suitability of a developed resist pattern and obtaining an accurately transferred pattern. The present invention relates to a method of manufacturing a semiconductor device.
(2) 技術の背景
半導体装置の製造におけるホトエツチング工程
においては、ワーキングマスクを、ウエーハに塗
布したホトレジストに転写する。この転写はホト
マスクの位置合わせ、密着又は投影による紫外線
露光および現像からなる。この露光・現像におい
て得られたレジスト画像がワーキングマスクのパ
ターンを正確に反映しているかどうかが問題とな
る。(2) Background of the technology In the photoetching process in the manufacture of semiconductor devices, a working mask is transferred to a photoresist coated on a wafer. This transfer consists of photomask alignment, exposure to ultraviolet light by contact or projection, and development. The question is whether the resist image obtained through this exposure and development accurately reflects the pattern of the working mask.
(3) 従来技術と問題点
ホトエツチング工程において露光時間が適正で
あるか否かをチエツツクすることは、ホトレジス
トにワーキングマスクが正確に転写されている否
かという点より極めて重要なことである。すなわ
ち、ホトレジストの膜厚や現像条件などを一定に
しても露光時間が適正時間よりも短い場合は光の
回折等の現象より所望レジスト画像よりも大きく
なり、一方露光時間が適正時間よりも長い場合所
望レジスト画像よりも小さくなる。従つて、露光
時間が適正でない場合、レジストを剥離し再度位
置合わせ、露光および現像を行なわなければなら
ず、このため多大の時間的ロスが生じることとな
る。(3) Prior Art and Problems Checking whether the exposure time is appropriate in the photoetching process is much more important than checking whether the working mask is accurately transferred to the photoresist. In other words, even if the photoresist film thickness and development conditions are constant, if the exposure time is shorter than the appropriate time, the resist image will be larger than the desired resist image due to phenomena such as light diffraction, whereas if the exposure time is longer than the appropriate time, the resist image will be larger than the desired resist image. The resist image becomes smaller than the desired resist image. Therefore, if the exposure time is not appropriate, the resist must be peeled off, repositioned, exposed, and developed, resulting in a large amount of time loss.
従来、露光時間が適正であるか否かを判別する
ためにはホストマスク内のチツプ形成パターン間
のライン上にＬ字形の測長パターンを設け、この
パターンが転写された現像レジストパターンを測
長器および顕微鏡を用い実際測長を行つていた。
このような測定を伴なう顕微鏡検査は相当の時間
を強要するものである。従つて、このような検査
に伴う時間を短縮しより簡便な方法で、得られた
レジストパターンの適正露光度を判定しより精度
の高いICパターンを得る方法が望まれていた。 Conventionally, in order to determine whether the exposure time is appropriate, an L-shaped length measurement pattern is placed on the line between the chip forming patterns in the host mask, and the length of the developed resist pattern to which this pattern is transferred is measured. Actual length measurements were carried out using instruments and microscopes.
Microscopic examinations involving such measurements are quite time consuming. Therefore, there has been a desire for a method that can shorten the time associated with such inspections and that is simpler, determines the appropriate exposure level of the obtained resist pattern, and obtains more accurate IC patterns.
(4) 発明の目的
本発明は、現像レジストパターンの露光適正度
を簡便かつ瞬時に判定しプロセスの効率化を高め
うる半導体装置の製造方法を提供することをその
目的とする。(4) Object of the Invention An object of the present invention is to provide a method for manufacturing a semiconductor device that can easily and instantaneously determine the exposure suitability of a developed resist pattern and improve the efficiency of the process.
(5) 発明の構成
かかる目的達成のため、本発明は少なくとも３
個のパターンから構成される下記の寸法チエツク
用パターンを有するマスクを使用してレジストに
対し露光を行ない、露光後レジストを現像し寸法
チエツク用レジストパターンを得、このレジスト
パターンを顕微鏡を用いて観察し露光の適正度を
判断する工程を有することを特徴とするものであ
り、前記寸法チエツク用パターンは(1)マスクの一
側からマスクの他側に向つて延びる第一パター
ン、(2)該マスクの前記一側から前記他側に向つて
第一パターンと平行に延びる第二パターン、およ
び(3)該マスクの前記他側から前記第一パターンと
第二パターンとの間の間隙内に向つて前記第一パ
ターン及び第二パターンと平行に延びる第三パタ
ーンとからなり、前記第一パターンの他側の先端
辺部が第二パターンの他側の先端辺部よりも一定
距離αだけマスクの前記他側に近接した位置にあ
り、前記第三パターンの先端辺部が前記第一パタ
ーンの他側の先端辺部からα／２＋2β（βは露光シ
フトである。）だけマスクの一側にあることを特
徴とする。なお露光シフトとは、ホトレジスト上
に理想的に投影されたマスクパターンと所定のプ
ロセスをへて実際に形成されるレジストパターン
とのずれを示し、本明細書ではレジストパターン
が縮少する方向へのずれを正の露光シフトとして
いる。この露光シフトβはホトレジストの感光特
性、膜厚、露光光学系の分解能、露光時間、現像
条件等のプロセス条件に依存するもので、一定の
プロセス条件では、定つた値となるものである。(5) Structure of the invention In order to achieve the above object, the present invention comprises at least three
The resist is exposed to light using a mask having the following dimension check pattern consisting of patterns, and after exposure, the resist is developed to obtain a dimension check resist pattern, and this resist pattern is observed using a microscope. The method is characterized by a step of determining the appropriateness of exposure, and the dimension check pattern includes (1) a first pattern extending from one side of the mask to the other side of the mask; (3) a second pattern extending parallel to the first pattern from the one side of the mask toward the other side; and (3) a second pattern extending from the other side of the mask into the gap between the first pattern and the second pattern. and a third pattern extending parallel to the first pattern and the second pattern, and the tip side of the other side of the first pattern is a certain distance α from the tip side of the other side of the second pattern. The third pattern is located close to the other side, and the leading edge of the third pattern is on one side of the mask by α/2+2β (β is an exposure shift) from the leading edge of the other side of the first pattern. It is characterized by Note that exposure shift refers to a shift between a mask pattern ideally projected onto a photoresist and a resist pattern actually formed through a predetermined process. The deviation is considered a positive exposure shift. This exposure shift β depends on process conditions such as the photoresist's photosensitive characteristics, film thickness, resolution of the exposure optical system, exposure time, and development conditions, and takes a fixed value under certain process conditions.
すなわち、本発明はホトマスクの製品となるべ
き領域外の個所、例えばホトマスクの片隔に前述
の３個のパターンから構成される寸法チエツクパ
ターンを形成し、このパターンをホトレジストに
転写して３個のパターンから成るレジストパター
ンを形成し、この３個のレジストパターンの相対
的位置関係によつて、レジスト線幅が許容範囲内
に入つているか否かをチエツクせんとするもので
ある。つまり、露光の進行に従つて得られるレジ
ストパターンはポジ型レジストを用いた場合は、
レジストパターンのエツジ全体がレジスト側に縮
少するように、又ネガ型レジストの場合はこれと
逆に拡大するようになるのであるが、本発明の寸
法チエツクパターンにおいては、その第一パター
ンと第二パターンのエツジは同一方向に縮少又は
拡大するので、第一パターンと第二パターンとの
ピツチαは露光・現像などのプロロセスの条件に
かかわらず常に一定となる。又、レジストパター
ンの第三パターンの一側のエツジは先の第一およ
び第二パターンの他側のエツジとは互いに逆方向
に縮小又は拡大し所定のプロセス条件での露光シ
フトをβとすると、投影されたマスクパターンの
ピツチより2βだけレジストパターンのピツチが
変化するのであるが、本発明では所定のプロセス
条件で適正露光となつたときにレジストパターン
の第一および第二パターンの他側のエツジの中間
の位置に第三パターンの一側のエツジがくるよう
にあらかじめマスクパターンにおいて第三パター
ンを第一および第二パターンに対して2β分相対
的にずらしておくようにしたものである。 That is, in the present invention, a dimension check pattern consisting of the three patterns described above is formed at a location outside the area of the photomask that is to become a product, for example, on one side of the photomask, and this pattern is transferred to a photoresist to form the three patterns. A resist pattern consisting of patterns is formed, and it is checked whether the resist line width is within a permissible range based on the relative positional relationship of the three resist patterns. In other words, when a positive resist is used, the resist pattern obtained as the exposure progresses is
In the dimension check pattern of the present invention, the entire edge of the resist pattern shrinks toward the resist side, and in the case of a negative resist, it expands in the opposite direction. Since the edges of the two patterns are reduced or expanded in the same direction, the pitch α between the first pattern and the second pattern is always constant regardless of process conditions such as exposure and development. Further, the edge on one side of the third pattern of the resist pattern is reduced or expanded in the opposite direction to the edge on the other side of the first and second patterns, and if the exposure shift under predetermined process conditions is β, The pitch of the resist pattern changes by 2β from the pitch of the projected mask pattern, but in the present invention, when proper exposure is achieved under predetermined process conditions, the edges of the other side of the first and second patterns of the resist pattern change. In the mask pattern, the third pattern is shifted relative to the first and second patterns by 2β in advance so that one edge of the third pattern is located in the middle position.
以下、本発明の一実施例を図面に基づいて説明
する。 Hereinafter, one embodiment of the present invention will be described based on the drawings.
(6) 発明の実施例
ホトマスク１の必要パターン領域外、例えばホ
トマスクの片隔に矩形の第一パターン２、矩形の
第二パターン３、および矩形の第三パターン４か
ら構成される寸法制御チエツクパターン（以下、
チエツクパターンという）Ａを形成する。このチ
エツクパターンＡは、例えば電子ビーム描画法に
よりレチクル作製時において同時に作成すること
ができる。(6) Embodiments of the Invention A dimension control check pattern consisting of a rectangular first pattern 2, a rectangular second pattern 3, and a rectangular third pattern 4 outside the required pattern area of the photomask 1, for example, on one side of the photomask. (below,
(referred to as a check pattern) A is formed. This check pattern A can be created at the same time as the reticle is being manufactured, for example, by electron beam lithography.
寸法チエツクパターンを構成する第一パターン
２と第二パターン３は双方ともマスクの一側から
マスクの他側に向つて平行に延びており、該第一
パターン２の他側の先端辺部２ａは第二パターン
３の他側の端辺部３ａよりも一定距離αだけマス
クの他側に近接して位置している。この一定距離
αの上限値はIC設計上必然的に定められる値で
あり、その下限値は顕微鏡により第一パターン２
の先端辺部２ａと第二パターン３の先端辺部３ａ
の差が可視できる値である。従つて、この上限値
と下限値に間にある範囲が許容範囲となる。上記
一定距離α、換言すれば許容範囲αは露光時間に
依存せず一定である。 Both the first pattern 2 and the second pattern 3 constituting the dimension check pattern extend in parallel from one side of the mask to the other side of the mask, and the tip side 2a of the other side of the first pattern 2 is It is located closer to the other side of the mask by a certain distance α than the other end side 3a of the second pattern 3. The upper limit value of this constant distance α is a value inevitably determined in IC design, and the lower limit value is determined by microscopy for the first pattern 2.
The leading edge 2a of the second pattern 3 and the leading edge 3a of the second pattern 3
The difference between the two values is visible. Therefore, the range between the upper limit and the lower limit becomes the permissible range. The above-mentioned constant distance α, in other words, the allowable range α is constant regardless of the exposure time.
第一パターン２と第二パターン３との間には、
マスクの前記他側から一方側に第一パターン及び
第二パターンと平行に（又はほぼ平行に）延びる
第三パターン４が更に前記マスクＡに設けられて
いる。更に第三パターン４の一側の先端辺部４ａ
は第一パターン２の他側の先端辺部２ａの位置よ
りα／２＋2β（βは露光シフトである。）の位置だけ
マスクの一側にある。なお第２図においては、
2βがα／２に比べて小なる場合のマスクパターンを
図示してるが、2βがα／２より大なる場合は第三パ
ターンの先端辺部４ａは第二パターンの先端辺部
３ａよりも一側即ち図の左側へくるようになる。 Between the first pattern 2 and the second pattern 3,
The mask A is further provided with a third pattern 4 extending from the other side of the mask to one side in parallel (or substantially parallel) to the first pattern and the second pattern. Furthermore, the tip side portion 4a on one side of the third pattern 4
is located on one side of the mask by a position α/2+2β (β is an exposure shift) from the position of the tip side 2a on the other side of the first pattern 2. In addition, in Figure 2,
The figure shows a mask pattern in which 2β is smaller than α/2, but if 2β is larger than α/2, the leading edge 4a of the third pattern is smaller than the leading edge 3a of the second pattern. side, that is, to the left side of the figure.
このような位置関係を有するマスクＡ（又はレ
チクル）を用いてホトレジストに対露光時間を３
通り変化させ紫外線露光を行い、次いで現像を行
い現像レジストパターン（第３〜５図）を得る。
すなわち、第一パターン２に対応して第一レジス
トパターン５，５′，５″、第二パターン３に対応
して第二レジストパターン６，６′，６″、および
第三パターンに対応して第三レジストパターン
７，７′，７″を得る。 Using mask A (or reticle) having such a positional relationship, the exposure time for the photoresist is 3.
The resist is exposed to ultraviolet light and then developed to obtain a developed resist pattern (FIGS. 3 to 5).
That is, first resist patterns 5, 5', 5'' correspond to the first pattern 2, second resist patterns 6, 6', 6'' correspond to the second pattern 3, and correspond to the third pattern. Third resist patterns 7, 7', 7'' are obtained.
今、露光時間が適正露光時間よりも短かい場
合、すなわち露光不足である場合第三レジストパ
ターン７の先端辺部７ａは許容範囲αから外れ第
二レジストパターン６側に位置する（第３図）。
これは露光時間が短かく得られるレジストパター
ン５，６，７の縮少値が予じめ定められた縮少値
βよりも少さいことに起因する。 Now, if the exposure time is shorter than the proper exposure time, that is, if the exposure is insufficient, the leading edge portion 7a of the third resist pattern 7 is out of the tolerance range α and is located on the second resist pattern 6 side (FIG. 3). .
This is because the reduction value of the resist patterns 5, 6, and 7 obtained with a short exposure time is smaller than the predetermined reduction value β.
露光時間が適正な露光時間内にある場合、第三
レジストパターン７′の先端辺部７′ａは許容範囲
α内に存在する。つまり必要な露光シフトが許容
範囲内に入つていることを示している。 When the exposure time is within a proper exposure time, the leading edge portion 7'a of the third resist pattern 7' is within the tolerance range α. In other words, this indicates that the necessary exposure shift is within the allowable range.
露光時間が適正露光時間よりも過剰である場
合、第三レジストパターン７″の先端辺部７″ａは
許容範囲α外にあり第一レジストパターン５″お
よび第二レジストパターン６″より隔つた位置に
ある。 When the exposure time is excessive than the proper exposure time, the leading edge 7''a of the third resist pattern 7'' is outside the tolerance range α and is located at a position separated from the first resist pattern 5'' and the second resist pattern 6''. It is in.
本発明では、所定のプロセス条件におけるマス
クパターンとレジストパターンのずれ、即ち露光
シフトを補正するようにあらかじめ、チエツクパ
ターンがマスク上に形成されているので露光条件
の適否の判定にあたつては、露光シフトの多少に
かかわらずレジストパターンが第４図のごとくな
つているか否かだけを見ればよい。 In the present invention, a check pattern is formed on the mask in advance to correct the deviation between the mask pattern and the resist pattern under predetermined process conditions, that is, the exposure shift. It is only necessary to check whether the resist pattern is shaped as shown in FIG. 4, regardless of the degree of exposure shift.
(7) 発明の効果
本発明は以上の説明から明らかなようにマスク
内にわずかに三個のパターンからなる寸法チエツ
ク用パターンを形成し、該マスクを用いて露光・
現像を行なうように構成したものであるから、顕
微鏡観察だけで必要な露光シフトが入つているか
どうか、つまり露光時間が適正であつたが否かを
瞬時に判断し得る効果を奏する。従つて、ICプ
ロセスにおいて全体の作業時間の短縮化・能率化
を図ることが可能となる。又、本発明では、寸法
チエツクパターンの占める面積を少くできるの
で、半導体基板を効率的に利用することができ
る。(7) Effects of the Invention As is clear from the above description, the present invention forms a dimension check pattern consisting of only three patterns in a mask, and performs exposure and
Since it is configured to perform development, it is possible to instantly determine whether the necessary exposure shift has occurred, that is, whether the exposure time is appropriate or not, just by microscopic observation. Therefore, it is possible to shorten the overall working time and improve efficiency in the IC process. Further, in the present invention, since the area occupied by the dimension check pattern can be reduced, the semiconductor substrate can be used efficiently.
第１図は本発明の一実施例を示す平面図、第２
図は第１図の部分拡大図、第３図は露光不足の場
合のレジストパターンを示す平面図、第４図は適
正露光の場合のレジストパターンを示す平面図、
および第５図は露光過剰の場合のレジストパター
ンを示す平面図である。
１……マスク、２，３，４……パターン、Ａ…
…寸法チエツク用パターン。
FIG. 1 is a plan view showing one embodiment of the present invention, and FIG.
The figure is a partially enlarged view of FIG. 1, FIG. 3 is a plan view showing the resist pattern in the case of insufficient exposure, and FIG. 4 is a plan view showing the resist pattern in the case of proper exposure.
and FIG. 5 is a plan view showing a resist pattern in the case of overexposure. 1...Mask, 2, 3, 4...Pattern, A...
...Dimension check pattern.
Claims (1)
びる第一パターン、(2) 該マスクの前記一側から
前記他側に向つて第一パターンと平行に延びる第
二パターン、および(3) 該マスクの前記他側から
前記第一パターンと第二パターンとの間の間〓内
に向つて前記第一パターン及び第二パターンと平
行に延びる第三パターンとからなり、前記第１パ
ターンの他側の先端辺部が第二パターンの他側の
先端辺部よりも一定距離αだけマスクの前記他側
に近接した位置にあり、前記第三パターンの一側
の先端辺部が前記第一パターン他側の先端辺部か
らα／２＋2β（βは露光シフトである）の位置だけ マスクの一側にある、 からなる、寸法チエツク用パターンを有するマス
クを使用してレジストに対し露光を行ない、露光
後レジストを現像し寸法チエツク用レジストパタ
ーンを得、このレジストパターンを顕微鏡により
観察しその第三パターンの一側の先端辺部がその
第一パターンの他側の先端辺部とその第二パター
ンの他側の先端辺部との間に位置するか否かによ
つて露光の適正度を判断する工程を有することを
特徴とする、半導体装置の製造方法。[Claims] 1. The following three patterns: (1) a first pattern extending from one side of the mask toward the other side of the mask; (2) a first pattern extending from the one side of the mask toward the other side of the mask; (3) a second pattern extending parallel to the first pattern; and (3) parallel to the first pattern and the second pattern from the other side of the mask toward the inside between the first pattern and the second pattern. and a third pattern extending from the first pattern to the other side of the mask, the tip side of the other side of the first pattern being closer to the other side of the mask by a certain distance α than the tip side of the other side of the second pattern; A pattern for dimension checking, comprising: a leading edge on one side of the third pattern is located on one side of the mask by a position α/2+2β (β is an exposure shift) from the leading edge on the other side of the first pattern. After exposure, the resist is developed to obtain a resist pattern for dimension checking, and this resist pattern is observed with a microscope, and the leading edge of one side of the third pattern is A semiconductor, characterized by comprising a step of determining the appropriateness of exposure depending on whether the tip side of one pattern is located between the other side of the second pattern and the other side of the second pattern. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58180465A JPS6074525A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58180465A JPS6074525A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6074525A JPS6074525A (en) | 1985-04-26 |
| JPS6350852B2 true JPS6350852B2 (en) | 1988-10-12 |
Family
ID=16083693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58180465A Granted JPS6074525A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6074525A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60145637A (en) * | 1984-01-09 | 1985-08-01 | Mitsubishi Electric Corp | Pattern size measuring method of semiconductor device |
| JPS63281439A (en) * | 1987-05-13 | 1988-11-17 | Fujitsu Ltd | Checking method of displacement of baking |
| JPH08162513A (en) * | 1991-11-08 | 1996-06-21 | Nec Corp | Element dimension check pattern |
| US6507944B1 (en) * | 1999-07-30 | 2003-01-14 | Fujitsu Limited | Data processing method and apparatus, reticle mask, exposing method and apparatus, and recording medium |
| JP4972278B2 (en) * | 2004-11-29 | 2012-07-11 | 富士通セミコンダクター株式会社 | Reticle and semiconductor device manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5427708A (en) * | 1977-08-03 | 1979-03-02 | Pioneer Electronic Corp | Signal compander |
-
1983
- 1983-09-30 JP JP58180465A patent/JPS6074525A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5427708A (en) * | 1977-08-03 | 1979-03-02 | Pioneer Electronic Corp | Signal compander |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6074525A (en) | 1985-04-26 |
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