‘1309457 九、發明說明： 【發明所屬之技術領域】 令赞明係有 促崎联式槓體電路封裝構造，特別係 有關於—種薄膜覆晶封I構造（c〇F paekage，chipmim package) 〇 【先前技術】'1309457 IX. Description of the invention: [Technical field to which the invention pertains] The tribute is a structure of a chain-enhanced circuit package, in particular, a film-on-film package I structure (c〇F paekage, chipmim package) 〇【Prior technology】
在乂在薄膜式積體電路封裝構造中是以電路薄膜承載曰 片’如原申請人於我國專利公告第5〇5315號揭示—種「； 膜覆明封裝構造」。薄膜覆晶封裝構造（c〇f)相對於捲帶承 封裝構k (TCP)具有更薄與引腳微間距之優點，以符先進 體電路封裝之所需H咖捲帶之電路薄膜之厚度約在 5〇微米以下’而TCP捲帶之厚度則約在微米，故c〇F 捲帶之電路薄膜變得更薄。因此，在封裝製程中，特別是點 膠後對熱S]滕體之熟化處理，薄膜覆晶封裝構造會產生嚴重 的的形變勉曲，使得後段SMT組嚴難以施行。 如第1、2及3圖所示，一種習知之薄膜覆晶封裝構造⑽ 係包含-電路薄膜11〇、一晶片12〇以及一點塗形成之熱固 膠體130。如第2圖所示，該電路薄膜ιι〇係具有一軟質介 電層⑴與複數個引腳112，每—引腳ιΐ2係具有一内接指 ⑴與一外接指114，一防銲層115局部覆蓋該些引腳Η] 並使該些内接指113與外接指114為外露。該晶片12〇係具 有複數個凸塊121，苴係接人s兮， '、保接α至該些内接指113。該點塗形 成之熱固膠體13〇係流動並填充在該晶片12()與該電路薄膜 ⑽之間’並加熱以熟化成形。由於該電路薄媒ιι〇相當的 5 .1309457 薄’經常因為受到加熱溫度與熱固膠體13〇固化收縮的影響 會有形變往上翹曲的問顳 t扪問題，特別是在該電路薄膜11〇具有外 接指m之兩側方向（如第3圖所示）。當該電路薄膜no形 變過大導致平坦度太差，後段SMT組襄機台無法接受，故 無法將該電路薄膜m具有外接指114之兩侧貼接至外電路 板(即液晶面板與印刷電路板），引起組裝的良率損失。 【發明内容】In the film-type integrated circuit package structure, the circuit film is used to carry the film, as disclosed in the Chinese Patent Publication No. 5:5315, the "film-covered package structure". The film flip-chip package structure (c〇f) has the advantages of thinner and pin-pitch than the tape-and-reel package k (TCP), in order to meet the thickness of the circuit film of the desired H-roll tape of the advanced body circuit package. The thickness of the TCP tape is about micrometers, and the thickness of the TCP tape is about micrometers, so that the circuit film of the c〇F tape becomes thinner. Therefore, in the packaging process, in particular, the curing of the hot S] body after the dispensing, the film flip-chip packaging structure will cause severe distortion and distortion, making the rear SMT group difficult to implement. As shown in Figures 1, 2 and 3, a conventional film flip chip package structure (10) comprises a circuit film 11A, a wafer 12A, and a one-step formed thermoset 130. As shown in FIG. 2, the circuit film has a soft dielectric layer (1) and a plurality of pins 112. Each pin ι 2 has an internal finger (1) and an external finger 114, and a solder resist 115. The pins 局部 are partially covered and the internal fingers 113 and the external fingers 114 are exposed. The wafer 12 has a plurality of bumps 121, and is connected to the inner finger 113. The dot-formed thermosetting colloid 13 is flowed and filled between the wafer 12 () and the circuit film (10) and heated to be aged. Since the thin film of the circuit is equivalent to 5.11309457 thin 'often because of the influence of the heating temperature and the curing shrinkage of the thermosetting colloid 13〇, there is a problem that the deformation becomes warped, especially in the circuit film 11 〇 has the direction of the two sides of the external finger m (as shown in Figure 3). When the deformation of the circuit film is too large, the flatness is too poor, and the rear SMT group is unacceptable, so that the circuit film m cannot be attached to the outer circuit board on both sides of the external finger 114 (ie, the liquid crystal panel and the printed circuit board) ), causing a loss in yield of the assembly. [Summary of the Invention]
本發明之主要目的係在於提供一種薄膜覆晶封裝構造， 藉由複數個補強條設置於—電路薄膜之形狀以及位置關 係’在熟化-點塗形成之熱固膠體時能減少電路薄膜在具有 外接指兩側之形變麵曲，且該些補強條與該晶片un 可撓曲間隔，以利薄膜覆晶封裝構造之後段組裝。 本發明之次-目的係、在於提供—種膜覆晶封裝構造， 能增進該些補強條之局部抗翹曲特性。 本發明的目的及解決其技術問題是採用以下技術 方案來實現的。一種薄膜覆晶封裝構造主要包含一電路薄 膜、一晶片及一點塗形成之熱固膠體，更包含有複數個補強 條。該電路薄膜係具有一軟質介電層、複數個引腳以及一防 銲層。該些補強條係沿著該些引腳之複數個外接指而設於該 電路薄膜之兩側。該晶片係具有複數個凸塊，該些凸塊係接 合至該些引腳。該點塗形成之熱固膠體係形成於該電路薄膜 與該晶片之間。其中，該些補強條與該晶片之間留有一可撓 曲間隔。 本發明的目的及解決其技術問題還可採用以下技 6 t 1309457 術措施進一步實現。 前述的薄膜覆晶封裝構造，其中該些補強條係為相互 平打’並且至少一之該些補強條係連接有複數個垂直 向肋條’使該些補強條呈L形、I形或為梳形。 前述的薄膜覆晶封裝構造，其中該些補強條係位於該The main object of the present invention is to provide a thin film flip-chip package structure, wherein a plurality of reinforcing strips are disposed on the shape and positional relationship of the circuit film, and the circuit film can be reduced in external connection when forming a thermosetting colloid formed by spotting Refers to the deformation surface curvature on both sides, and the reinforcing strips are flexibly spaced from the wafer un to facilitate assembly of the film flip-chip package structure. The second objective of the present invention is to provide a film-on-film package structure which can improve the local warpage resistance of the reinforcing strips. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. A thin film flip chip package structure mainly comprises a circuit film, a wafer and a thermoset colloid formed by a single coating, and further comprises a plurality of reinforcing strips. The circuit film has a soft dielectric layer, a plurality of leads, and a solder resist layer. The reinforcing strips are disposed on both sides of the circuit film along a plurality of external fingers of the pins. The wafer has a plurality of bumps that are bonded to the pins. The dot-formed thermosetting adhesive system is formed between the circuit film and the wafer. There is a flexible interval between the reinforcing strips and the wafer. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. The above-mentioned thin film flip-chip package structure, wherein the reinforcing strips are flush with each other and at least one of the reinforcing strips is connected with a plurality of vertical ribs 'to make the reinforcing strips L-shaped, I-shaped or comb-shaped . The above-mentioned thin film flip chip package structure, wherein the reinforcing strips are located in the
晶片與同側之外接指之間，且較接近該些外接指。X 前述的薄膜覆晶封裝構造’其中該些補強條係貼附於 該防銲層。 ' • 冑述的薄膜覆晶封装構造，其中該些補強條係貼附於 該軟質介電層。 ' 前述的薄膜覆晶封裝構造，其中該電路薄膜之平坦声 係不大於3毫米。 —& 【實施方式】 依據本發明之第-具體實施例，揭示一種薄膜覆晶封装 構造（COF package)。如第4、5及6圖所示，主要包含—電 路薄膜210、複數個補強條22〇、一晶片23〇及一點塗形成 •之熱囡勝體240。其中，該電路薄膜21〇係用以承載該晶片 230 ’能以捲帶傳輸方式進行封裝作業。該些補強條22〇係 用以減少1亥電路薄膜2 1 0之兩側接合部在封裝過帛中的形變 翹曲。該熱固膠體240係用以局部密封以保護該晶片23〇。 I亥電路薄膜210係具有一軟質介電層211、複數個引聊 212以及-防銲層213。該軟質介電層211之材質係可為聚 醯亞胺（p〇丨yimide，PI)或PET，其係為該電路薄膜之核 心層。該些引腳2丨2係用以電性傳導該晶月23〇之輸入/輸 7 1309457 出訊號、電源、接地等。該防銲層213係局部覆蓋該些引腳 212。該些引腳212之一端係往該軟質介電層211中央扇入 集中，其不被該防銲層213所覆蓋之部分係成為複數個内接 指214 ;該些引腳212之另一端係往該軟質介電層2ιι兩侧 扇出排列，其不被該防銲層213所覆蓋之部分係成為複數個 外接指2 1 5。通常該防銲層2丨3係可選用液態感光性銲罩層 (hquid Ph〇t〇imagable soMer mask，Lpi)、感光性覆蓋層The wafer is between the same side and the outside fingers, and is closer to the external fingers. X The aforementioned film flip chip package structure 'where the reinforcing strips are attached to the solder resist layer. The thin film flip chip package structure described above, wherein the reinforcing strips are attached to the soft dielectric layer. The aforementioned thin film flip chip package structure in which the flat sound of the circuit film is no more than 3 mm. - & [Embodiment] According to a first embodiment of the present invention, a film flip-chip package structure (COF package) is disclosed. As shown in Figures 4, 5 and 6, it mainly comprises a circuit film 210, a plurality of reinforcing strips 22, a wafer 23, and a hot-rolled body 240 formed by a single coating. Wherein, the circuit film 21 is used to carry the wafer 230' and can be packaged in a tape transfer manner. The reinforcing strips 22 are used to reduce the deformation warpage of the joints on both sides of the 1H circuit film 210 in the package. The thermoset colloid 240 is used for partial sealing to protect the wafer 23〇. The I-Hui circuit 210 has a soft dielectric layer 211, a plurality of chats 212, and a solder resist layer 213. The material of the soft dielectric layer 211 may be p〇丨yimide (PI) or PET, which is the core layer of the circuit film. The pins 2丨2 are used to electrically conduct the input/transmission of the crystal 23 309 1 7 1309457 signal, power, ground, and the like. The solder resist layer 213 partially covers the leads 212. One end of the pins 212 is fanned into the center of the soft dielectric layer 211, and the portion not covered by the solder resist layer 213 is a plurality of internal fingers 214; the other ends of the pins 212 are The soft dielectric layer 2 ιι is fanned out on both sides, and the portion not covered by the solder resist layer 213 is a plurality of external fingers 2 15 . Usually, the solder resist layer 2丨3 is selected from a liquid photosensitive solder mask layer (hquid Ph〇t〇imagable soMer mask, Lpi), a photosensitive cover layer.
(ph〇t〇imagabie c〇ver layer ’ pic)、或可為一般非感光性介 電材質之非導電油墨或覆蓋層（c〇ver 。(ph〇t〇imagabie c〇ver layer ’ pic), or a non-conductive ink or cover layer (c〇ver) which is generally non-photosensitive dielectric material.
如第4圖所示，該些補強條22〇係沿著該些引腳2i2之 複數個外接指215而設於該電路薄膜210之兩側。在本實施 例中’該些補強條22〇係位於該晶片23〇與同一側之外 接指2 1 5之間，且較接近該些外接指2 1 5。是以，該些 補強條220之條形與側向位置使該電路薄膜210具有抵抗在 忒些外接指215兩側向之形變翹曲能力，能抵抗在形成該熱 固膠體240的熱製程中（或/及其它可能的熱循環）產生的形 (第6圖所不），並且能不影響該薄臈覆晶封装構造2〇〇 ^後&組裝之可撓曲性（容後料）。如第$圖所*，該電路 薄膜210之平坦度係不大於3毫米（叫。 車乂佳地’再如第4圖所示’該些補強條220係為相互 平行，並且至少_夕杜α，v 〜二補強條220兩端可以各連接 有一垂直向肋條9 9 1 肋條221，使該些補強條220之兩端係為 擴大以呈L形式了花？、 形，以增進該些補強條220之局部抗翹 曲特性。此外，蚌此站从 。亥二補強條220應為剛性材料，可利用貼 8 .1309457 附13刷或其它方法預先在封裝之前固著於該電路薄膜 210。如笛 stsjAs shown in FIG. 4, the reinforcing strips 22 are disposed on the two sides of the circuit film 210 along the plurality of external fingers 215 of the pins 2i2. In the present embodiment, the reinforcing strips 22 are located between the wafer 23 and the outer side of the same finger 2 1 5 and are closer to the external fingers 2 15 . Therefore, the strip shape and the lateral position of the reinforcing strips 220 make the circuit film 210 resistant to deformation warping on both sides of the external fingers 215, and can resist the heat process in forming the thermoset colloid 240. (or / and other possible thermal cycles) generated shape (not shown in Figure 6), and can not affect the flexibility of the thin-film flip-chip package structure 2 after assembly & assembly . As shown in Fig. 1, the flatness of the circuit film 210 is not more than 3 mm (called 乂 乂 佳 佳 'and as shown in Fig. 4 'the reinforcing strips 220 are parallel to each other, and at least _ 夕 Du The ends of the α, v 〜 2 reinforcing strips 220 may be respectively connected with a vertical rib 9 9 1 rib 221, so that the two ends of the reinforcing strips 220 are enlarged to form a flower in the form of L, to enhance the reinforcement. The partial warpage resistance of strip 220. In addition, the station should be a rigid material from the station. The second reinforcing strip 220 should be a rigid material, and can be fixed to the circuit film 210 before being packaged by means of a sticker of 8.301309 or 13 or other methods. Such as flute stsj
乐5圖所示，該些補強條220係貼附於該防銲芦 213。 S 第4圖所示’該晶片230係具有複數個凸塊231，該些 凸鬼231係為該晶片23〇内部積體電路之對外電極。通常該 片23〇係可為一顯示器之驅動1C或其它ASIC等等。可利 用熱壓合、回銲或導電膠接合等方式使該些凸塊231係接合 /二引腳212之該些内接指214。此外，該熱固膠體24〇 • 係以點塗方式形成於該電路薄膜21G與該晶片23()之間。由 於在封裝製程中，該晶片230之接合與該熱固膠體24〇之形 成皆需要使該電路薄膜210經過昇溫與降溫的過程，利用該 些補強條220可以減少該電路薄膜21〇之形變。此外，如第 4圖所示，該些補強條220(包含該些垂直向肋條221之部 位）與該晶片230之間留有一可撓曲間隔s，使該電路薄膜 2 1 〇在該晶片230與該些補強條220之間的區段可以作為 • C〇F撓曲使用，以供後段組裝貼合。另外，在後段組裝之前， 該些補強條220可發揮配重之功效，當該薄膜覆晶封裝構造 200放置於一載台上，能避免該薄膜覆晶封裝構造2⑽在具 有該些外接指215之兩側不當的往上翹起（如第5圖所示卜 如第7及8圖所示，在第二具體實施例中揭示另一種薄 模覆晶封裝構造300,主要包含一電路薄膜31〇、複數個補 強條320、一晶片330及一點塗形成之熱固膠體34〇，其中 電路薄膜310、晶片330與點塗形成之熱固膠體mo可與第 具體實施例相同，不再贅述。該電路薄膜3】〇係具有—軟 1309457 為介電層311、複數個引腳312以及一防銲層313。該些補 強條320係沿著該些引腳312之複數個外接指315而設於該As shown in the music diagram 5, the reinforcing strips 220 are attached to the solder resist 213. S is shown in Fig. 4, and the wafer 230 has a plurality of bumps 231 which are external electrodes of the integrated circuit of the wafer 23A. Typically, the chip 23 can be a display driver 1C or other ASIC or the like. The bumps 231 can be bonded to the inner fingers 214 of the /two pins 212 by means of thermocompression bonding, reflow soldering or conductive bonding. Further, the thermosetting colloid 24 is formed between the circuit film 21G and the wafer 23 () by dot coating. In the packaging process, the bonding of the wafer 230 and the formation of the thermosetting paste 24 需要 require the process of heating and cooling the circuit film 210, and the deformation of the circuit film 21 can be reduced by using the reinforcing strips 220. In addition, as shown in FIG. 4, a gap s is left between the reinforcing strips 220 (the portions including the vertical ribs 221) and the wafer 230, so that the circuit film 2 1 is clamped on the wafer 230. The section between the reinforcing strips 220 can be used as a • C〇F flexing for later assembly and fitting. In addition, before the assembly of the rear stage, the reinforcing strips 220 can function as a counterweight. When the film flip chip package structure 200 is placed on a stage, the film flip chip package structure 2 (10) can be prevented from having the external fingers 215. The two sides are improperly tilted upwards (as shown in FIG. 5, as shown in FIGS. 7 and 8, in another embodiment, another thin-mode flip chip package structure 300 is disclosed, which mainly includes a circuit film 31. 〇, a plurality of reinforcing strips 320, a wafer 330, and a thermoset colloid 34〇 formed by a single coating, wherein the circuit film 310, the wafer 330 and the thermosetting colloid mo formed by spot coating are the same as in the specific embodiment, and are not described again. The circuit film 3 has a soft layer 1309457 as a dielectric layer 311, a plurality of pins 312, and a solder resist layer 313. The reinforcing strips 320 are disposed along the plurality of external fingers 315 of the pins 312. In this
電路薄膜3 10之兩侧。如第7圖所示，在本實施例中，該些 補強條320係貼附於該軟質介電層3丨〖。該晶片33〇之 複數個凸塊331係接合至該些引腳312之内接指314。並以 形成於該電路薄膜310與該晶片33〇之間的該熱固膠體34〇 ，密封該些凸塊331。如第8圖所示’該些補強條32〇與該 曰日片330之間留有_可撓曲間隔。此外’該些補強條η。 二為相互平行，並且至少一之該些補強條3 2 〇係連接 有複數個垂直向肋條32丨，使該些補強條係為梳 形’用以解決習知C〇F產品在封裝製程中受到的熱處 理導致COF產品平坦度不合格的問題。 以上所述’僅是本發明的較佳實施例而已，並非對本發 明作任何形式上的限制’雖然本發明已以較佳實施例揭露如 上’然而並非用以限定本發明，任何熟悉本項技術者在不 脫離本發明之中請專利範圍内，所作的任何簡單修改、等效 ，變化與修飾’皆涵蓋於本發明的技術範圍内。 【圖式簡單說明】 第1圏 第2圖 :習知薄膜覆晶封裝構造之正面示意圖。 .習知薄膜覆晶封裝構造沿第i圖2_2剖線之截面示 意圖。 第3圖： 第4圖： 面示 習知薄膜覆晶封裝構造沿第…。剖線之截 圖。 依據本發明之第_輕伟音始加 校佳實施例，一種薄膜覆晶封裝 10 .1309457 構造之正面示意圖。 第5圖 依據本發明之第一較佳實施例，該薄膜覆晶封骏構 造沿第4圖5_5刻線之截面示意圖。 第6圖 第7圖 依據本發明之第一較佳實施例，該薄膜覆晶封裝構 造沿第4圖6-6剖線之截面示意圖。 第8圖 依據本發明之第二較佳實施例，另一薄膜覆晶封裝 構造沿一較短中心軸剖切之截面示意圖。 依據本發明之第二較佳實施例，繪示該薄膜覆晶封 裝構造之補強條相對位置之示意圖。 主要元件符號說明】 100 薄膜覆晶 封裝構造 110 電路薄膜 111 軟質介電層 112 引腳 113 内接指 115 防銲層 120 晶片 130 點塗形成之熱固膠體 200 薄膜覆晶 封裝構造 210 電路薄膜 211 軟質介電層 212 引腳 213 防鲜層 215 外接指 220 補強條 221 垂直向肋條 230 晶片 231 凸塊 240 點塗形成 之熱固膠體 300 薄膜覆晶 封裝構造 3 10 電路薄膜 311 軟質介電層 114外接指 121凸塊 2 1 4内接指 11 .1309457 312引腳 313防銲層 314内接指 3 15外接指 320補強條 321垂直向肋條 330晶片 331凸塊 340點塗形成之熱固膠體 S 可撓曲間隙Both sides of the circuit film 3 10 . As shown in Fig. 7, in the present embodiment, the reinforcing strips 320 are attached to the soft dielectric layer. A plurality of bumps 331 of the wafer 33 are bonded to the internal fingers 314 of the pins 312. The bumps 331 are sealed by the thermoset colloid 34 形成 formed between the circuit film 310 and the wafer 33A. As shown in Fig. 8, there is a _ flexible interval between the reinforcing strips 32A and the crucible sheet 330. In addition, the reinforcing bars η. The two are parallel to each other, and at least one of the reinforcing strips 3 2 is connected with a plurality of vertical ribs 32 丨, so that the reinforcing strips are comb-shaped 'to solve the conventional C 〇 F product in the packaging process The heat treatment received causes a problem that the flatness of the COF product is unacceptable. The above description is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way. Although the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention. Any simple modifications, equivalents, changes and modifications of the invention are intended to be included within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a front view showing a conventional film flip chip package structure. A conventional thin film flip chip package structure is shown along the cross section of Fig. 2-2. Figure 3: Figure 4: The conventional film flip-chip package structure along the .... A cut-off of the line. According to the first embodiment of the present invention, a front view of a structure of a film flip chip package 10.1309457. Fig. 5 is a cross-sectional view showing the structure of the film on the scribe line of Fig. 4-5 in accordance with a first preferred embodiment of the present invention. Figure 6 is a cross-sectional view of the film flip chip package taken along line 4-6 of Figure 4, in accordance with a first preferred embodiment of the present invention. Figure 8 is a cross-sectional view of another thin film flip chip package structure taken along a shorter central axis in accordance with a second preferred embodiment of the present invention. According to a second preferred embodiment of the present invention, a schematic view of the relative positions of the reinforcing strips of the film flip chip mounting structure is shown. Main component symbol description] 100 film flip chip package structure 110 circuit film 111 soft dielectric layer 112 pin 113 internal finger 115 solder resist layer 120 wafer 130 spot-formed thermoset colloid 200 film flip chip package structure 210 circuit film 211 Soft dielectric layer 212 pin 213 Fresh-keeping layer 215 External finger 220 Reinforcing strip 221 Vertical rib 230 Wafer 231 Bump 240 Spot-formed thermoset colloid 300 Thin film flip-chip package structure 3 10 Circuit film 311 Soft dielectric layer 114 External finger 121 bump 2 1 4 internal finger 11 .1309457 312 pin 313 solder resist layer 314 internal finger 3 15 external finger 320 reinforcing strip 321 vertical rib 330 wafer 331 bump 340 spotted thermoset colloid S Flexible gap
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