TW200743186A - Chip-on film package for lessening deformation of film - Google Patents

Chip-on film package for lessening deformation of film

Info

Publication number
TW200743186A
TW200743186A TW095116536A TW95116536A TW200743186A TW 200743186 A TW200743186 A TW 200743186A TW 095116536 A TW095116536 A TW 095116536A TW 95116536 A TW95116536 A TW 95116536A TW 200743186 A TW200743186 A TW 200743186A
Authority
TW
Taiwan
Prior art keywords
chip
film
wiring film
package
deformation
Prior art date
Application number
TW095116536A
Other languages
Chinese (zh)
Other versions
TWI309457B (en
Inventor
Kuei-Yu Lai
Original Assignee
Chipmos Technologies Inc
Chipmos Technologies Bermuda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc, Chipmos Technologies Bermuda filed Critical Chipmos Technologies Inc
Priority to TW095116536A priority Critical patent/TWI309457B/en
Publication of TW200743186A publication Critical patent/TW200743186A/en
Application granted granted Critical
Publication of TWI309457B publication Critical patent/TWI309457B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A Chip-On-Film (COF) package for lessening deformation of film is disclosed, which mainly includes a wiring film, a bumped chip, a plurality of stiffening bars, and a thermosetting compound by potting. The wiring film has a plurality of external fingers on its two opposing sides. The stiffening bars are attached adjacent the two sides along the external fingers. The chip is bonded to the wiring film. The thermosetting compound is formed between the chip and the wiring film. Additionally, there are flexible spacings between the stiffening bars and the chip. Accordingly, the deformation of the wiring film caused during manufacturing process of the COF package will be lessened and also keep flexible portions for back-end SMT process.
TW095116536A 2006-05-10 2006-05-10 Chip-on film package for lessening deformation of film TWI309457B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW095116536A TWI309457B (en) 2006-05-10 2006-05-10 Chip-on film package for lessening deformation of film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095116536A TWI309457B (en) 2006-05-10 2006-05-10 Chip-on film package for lessening deformation of film

Publications (2)

Publication Number Publication Date
TW200743186A true TW200743186A (en) 2007-11-16
TWI309457B TWI309457B (en) 2009-05-01

Family

ID=45072045

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095116536A TWI309457B (en) 2006-05-10 2006-05-10 Chip-on film package for lessening deformation of film

Country Status (1)

Country Link
TW (1) TWI309457B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI415227B (en) * 2009-01-06 2013-11-11 Raydium Semiconductor Corp Chip packaging structure and lead frame
TWI495061B (en) * 2012-11-20 2015-08-01 Raydium Semiconductor Corp Package structure manufacturing method
CN107492525A (en) * 2016-06-10 2017-12-19 三星显示有限公司 Chip package and include the display device of chip package on the film on film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI415227B (en) * 2009-01-06 2013-11-11 Raydium Semiconductor Corp Chip packaging structure and lead frame
TWI495061B (en) * 2012-11-20 2015-08-01 Raydium Semiconductor Corp Package structure manufacturing method
CN107492525A (en) * 2016-06-10 2017-12-19 三星显示有限公司 Chip package and include the display device of chip package on the film on film
CN107492525B (en) * 2016-06-10 2024-07-05 三星显示有限公司 Chip-on-film package and display device including the same

Also Published As

Publication number Publication date
TWI309457B (en) 2009-05-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees