1308756 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種NAND型‘决閃記憶體元件（NAND flash memory device)之窝入方法（pr〇gram meth〇d)及用以執行該 寫入方法之頁缓衝器（page buffer)，尤指一種應用於每一記 憶胞（memory cell)儲存二位元資料（tw〇_bit data)之多層次 胞（multi-level_cell)NAND型快閃記憶體元件之寫入方法及 用以執行該寫入方法之頁緩衝器。 【先前技術】 在一傳統NAND型㈣記憶體中，每_記憶胞可儲存兩 種資料狀態，意即可儲存「開」狀態（”〇N”崎）或「關」 狀態（OFF state)。資訊的每一位元⑼⑽由個別的記憶胞 之「開」、「關」狀態所定義。在傳統NANDs快閃記憶體中， 為了能儲存N個位元資料（N為大於或等於2之整數），必須使 用N個個別的δ己憶胞。因此，若是使用傳統N颜〇型快間記 憶體，當所要儲存的資料位元個數增加時，記憶胞的個數 也必Θ跟著增加。儲存在單—位元（__bk)記憶胞之資訊係 决疋於°己憶胞之寫入狀態（programmed status)，而該資料 係利1寫入（program)動作儲存至該記憶胞。存有記憶胞狀 〜、之-貝Λ係由一位於該記憶胞中之電晶體之門檻電壓 (threshold voltage)所決^。門檀電壓係施予在該電晶體之 閉極及源極間，可將該電晶體導通（t_〇n)之最小電壓。 圖1係-可儲存二位元資訊之記憶胞電晶體1〇之剖面示 意圖’其係使用在-NAND型快閃記憶體元件中。該記憶胞 108368.doc ^ 1308756 電晶體ίο包含二閘極（即上、下閘極），係疊層於一位於源極 及没極之間之通道區域（channel region)。上閘極稱控制閘 極11 ’而下閘極稱浮動閘極12。該浮動閘極丨2係一被位於 該控制閘極11及該通道區域之間之絕緣材料丨3所包圍之電 荷儲存部（charge storage portion)。因此，儲存在每一記情 胞之資料狀態可利用該記憶胞之門檻電壓加以區分。 圖2係應用在一 NAND型快閃記憶體中之記憶胞陣列 20(memory cell array)中之二記憶胞串（string)示意圖，其中 每一記憶胞1 0係儲存二位元資訊。該記憶胞陣列2〇包含串 接於一位元線BL1或BL2 (bit line)及一地選擇線 GSL(gr〇imd select line)之間之複數個記憶胞1〇。一組與位 元線（BL1 或 BL2)、串選擇電晶體 SST(string select transist〇r) 及地選擇電晶體GST(ground select transistor)相串接之記 憶胞ίο稱為記憶胞串，其中該串選擇電晶體SST及該地選擇 電晶體GST係用以選定用來進行寫入之記憶胞丨〇 ,而串選 擇電日日體SST之導通（turn on)或關閉（turn off)則由一串選擇 線SSL(string select line)之狀態所決定。該串選擇電晶體 SST被選擇性地切換以耦合相關的記憶胞串及位元線；該地 選擇電晶體GST則被選擇性地切換每—記憶胞串及一共源 線 CSL(common source line)之間之電連接（eiectrical connection) ° 圖3顯不根據所寫入的資料，一記憶胞之四種門檻電壓分 佈圖。如圖3所示’所寫入的資料可以以下四種電壓分佈之 一來表不：（1)小於-2.0V之門檻電壓分佈，係代表（11)之二 108368.doc 1308756 位元資料；（2)介於〇.3V及〇.7V之門檻電壓分佈，係代表（1〇) 之一位元資料；（3)介於1.3V及1.7V之門檻電壓分佈，係代 表（01)之二位元資料及（4)介於2.3 V及2.7V之門檻電壓分 佈’係代表（00)之二位元資料。資料可基於上述四種不同門 檻電壓分佈而儲存於一記憶胞中。 關於應用於一多層次胞NAND型快閃記憶體之寫入方法 已有一些方法被提出，將於下文陸續介紹。 美國專利US 5,768，188中（合併作為參考資料，以下稱，188) 揭示一二階段寫入方法（three-phase program operation)(參 閱'188中之圖5)。在寫入方法開始前’所有的記憶胞被重置 (reset)至（11)狀態，接著欲寫入之二位元資料被下載至二暫 存器Q1及Q2(參閱，188之圖1)，該二暫存器Q2及Q1係分別栓 鎖（latch)該二位元資料之最高有效位元（m〇st significant bit ’ MSB)及最低有效位元（ieast signmcant ⑽；LSB)。圖 4(a)至4(c)係顯示該寫入方法中每階段之記憶胞其係分別 代表將記憶胞分別寫入（10)狀態、（01)狀態及（〇〇)狀態。狀 悲轉換示意圖，於圖4(a)(即第一階段）中，欲被寫入至（1 〇) 狀態的記憶胞係自（11)狀態啟始而結束於（1〇)狀態，其係以 實箭號（solid p〇inter)A1表示；欲被寫入至（00)狀態的記憶 胞係自（11)狀態啟始而結束於（〇〇)狀態，其係以虛箭號 (dashedp〇inter)A2表示。然而，欲被寫入至（〇1)狀態的記憶 胞則沒有進行寫入之動作。啟始於狀態而結束於（1〇) 之實箭號A1係表示所有欲被寫入至（1〇)狀態的記憶胞已完 成寫入之動作；然而，啟始於（11)狀態而結束於（〇〇)之虛箭 108368.doc E39981 Ί308756 唬A2係表示部分欲被寫入至（〇〇)狀態的記憶胞仍處在寫入 過程中。於圖4(b)(即第二階段）中，欲被寫入至（01)狀態的 记憶胞係自（11)狀態啟始而直接轉變至（〇1)狀態，其係以實 箭唬A3表示’意即所有欲被寫入至（〇1)狀態的記憶胞已完 成寫入之動作。此時’欲被寫入至（〇〇)狀態的記憶胞係自（1〇) 狀態開始寫入’其係以虛箭號A4表示，係代表部分欲被寫 入至（00)狀態的記憶胞仍處在寫入過程中。根據，188之圖1 之邏輯電路，栓鎖在該二暫存器Q2及(^之^丨）狀態及（〇〇) 狀態將分別被轉換成（U)狀態及（10)狀態（參，188之圖5之第 二階段’驗證（verification)動作將在寫入動作後執行），即 暫存器Q2的狀態將從低位準轉換成高位準。如此，對於已 被寫入至（〇 1)狀態或（00)狀態之記憶胞將無法進行寫入動 作（即寫入禁止（program inhibition))，此乃因暫存器Q2已栓 鎖欲寫入之二位元資料之具高位準之最高有效位元ΰ此 外’當（〇〇)狀態與（01)狀態同時進行寫入之動作時，（〇〇)狀 態並不會發生過渡寫入（overprogram)之情況。於圖4(c)(即 第三階段）中，欲被寫入至（00)狀態的記憶胞係自（〇1)狀態 啟始而結束於（〇〇)狀態’其係以實箭號（solid pointer)A# 示’意即所有欲被寫入至（00)狀態的記憶胞已完成寫入之動 作。 美國專利US 6,411,551(合併作為參考資料，以下稱351) 另揭示一三階段寫入方法。圖5(a)至5(c)係顯示該寫入方法 中每階段之記憶胞狀癌轉換不意圖，其係分別代表將記憶 胞分別寫入（10)狀態、（01)狀態及（00)狀態。揭示於，551之 I08368.doc Ί30Β756 寫入方法係為解決於，188所產生之相鄰門檻電壓分佈過 近之問題。該問題係於，！88中，因欲被被寫入至狀態之 記憶胞係直接自（11)狀態寫入，結果將造成一較寬的門檻電 壓分佈，進而造成與前後相鄰門檻電壓分佈過於接近（即形 成較窄的邊際（narrower margin))。於圖5(a)(即第一階段） 中’在欲被寫入至（10)狀態之記憶胞進行寫入動作（以實箭 號B1表示）的同時，欲被分別寫入至（〇丨）狀態及（〇〇)狀態的 S己憶胞也同時自（1 1 )狀態開始進行寫入的動作（分別以虛箭 號B2及B3表示）。其中虛箭號B2及B3表示其相關記憶胞之 寫入動作尚未完全達成。於圖5(b)(即第二階段）中，欲被寫 入至（00)狀態的記憶胞之寫入動作仍在進行中（以虛箭號B5 表示）；同時，欲被寫入至（01)狀態的記憶胞係自（1〇)狀態 開始且完成其寫入的動作（以實箭號B4表示），意即所有欲 被寫入至（01)狀態、的記憶胞已完成寫入之動作。最後，參考 圖5(c) ’欲被寫入至（00)狀態的記憶胞係自（01)狀態開始且 完成其寫入的動作（以實箭號B6表示）。 美國專利US 5,986,929(合併作為參考資料，以下稱，929) 亦揭示一三階段寫入方法。圖6(a)至6(c)係顯示該寫入方法 中每階段之記憶胞狀態轉換示意圖，其係分別代表將記憶 胞分別寫入（10)狀態、（01)狀態及（00)狀態。於圖6(a)(即第 一階段）中，欲被寫入至（00)狀態的記憶胞之寫入動作被禁 止（program inhibition)，以減少在’188中之（〇〇)狀態過度寫 入情況的發生。意即在此階段僅有欲被寫入至（1〇)狀態的記 憶胞之寫入動作執行（以實箭號C1表示）並完成，於圖 108368.doc -10- '1308756 6(b)(即第二階段;)中，實箭號(：2表示欲被寫入至狀態的 。己憶胞自（11)狀態啟始之寫入動作已執行並完成；然而，虛 箭號C3表示部分欲被寫入至（〇〇)狀態的記憶胞仍處在寫入 過私中。於圖6(c)(即第三階段）中，實箭號以表示欲被寫入 至（00)狀態的記憶胞自（01)狀態啟始之寫入動作已執行並 v> 凡成0 【發明内容】 φ 本發明之主要目的係提供一種多層次胞 (multi-levei_cell)NAND型快閃記憶體元件之寫入方法，係 在寫入操作的第一階段中利用一限制寫入（Umited_pr〇gram) 之技術以減少寫入時間。 本發明之另一目的係提供一應用在一多層次胞NAND型 决閃δ己憶體元件中之頁緩衝區（page buffer)，以實施該寫入 方法該頁缓衝區係應用一互斥電路（excluSi〇n circuit)以實 施一互斥運算（exclusi〇n 〇perati〇n)。藉此，寫入時間得以 0 減少。 為達到上述之目的，本發明揭示一型快閃記憶 體7L件之寫入方法，係應用在一包含複數個記憶胞之多層 次胞NAND型快閃記憶體元件。每一記憶胞與一第_暫存器 及-第二暫存器相互關聯。該複數個記憶胞分為零記憶 月l第°己隐胞、第一記憶胞及第三記憶胞四類。該寫入 方法包含以下步驟：（a)將該複數個零、第一、第二及第三 記憶胞寫入至一零狀態（zer〇 state);⑻藉一第一寫入訊號 將該複數個第—記憶胞由該零狀態寫入至-第-狀態（first 108368.doc •11. E39981 1308756 state)，且藉—第二寫入訊號將該複數個第二記憶胞由該零 狀態寫入至—準第二狀態（quasi_sec〇nd state)及將該複數 個第二§己憶胞由該零狀態寫入至一半第三狀態（semi-third state) ; (0藉該第二寫入訊號將該複數個第二記憶胞由該準 第一狀恶寫入至一第二狀態（sec〇nd state)及將該複數個第 三記憶胞由該半第三狀態寫入至一準第三狀態（quasi_tMrd state);及（d)藉該第一寫入訊號將該複數個第三記憶胞由該 準第—狀恕寫入至一第三狀態（third state)。上述步驟（a)至 (d) το成之後，每—記憶胞均處於零狀態、第一狀態、第二 狀態或第三狀態。 本發明另揭示一種運用於一 NAND型快閃記憶體元件之 頁緩衝區，其包含：一位元線選擇電路、一第一暫存器、 —第二暫存器、一第—輸入電路、一第二輸入電路、一第 驗。且私路、一第二驗證電路及一互斥電路。該位元選擇 電路用以決定一選定位元線（selected bit line)及一遮蔽位 凡線（stueldmg bit line)。該第一暫存器及該第二暫存器係 用乂 ^鎖（latch) —預定寫入該複數個記憶胞之二位元資料 (two-bit data)，該複數個記憶胞係相關於該選定位元線且 該二位元資料係接收自該第一輸入電路及該第二輸入電 路。該第-驗證電路及該第二驗證電路用以驗證(verify)與 該選定位元線相_之該複數個記憶胞。該互斥電路用以 執仃-互斥運算以控制該二位元資料中每一位元之寫入。 【實施方式】 圖7(a)至7(c)係顯 示本發明之寫入方法中每階段之記憶 ,ns^8H( E39981 -12. Ί30δ756 胞狀態轉換示意®i8係本發明—實施例之頁緩衝區之電 路圖。圖9顯示與圖8相關訊號之時序圖。圖7⑷至7(c)所述 之記憶胞狀態轉換示意圖係基於圖8所示之電路，因此以下 將先對圖8作說明。 圖8顯示本發明一實施例之頁缓衝區3〇包含一位元線選 擇電路3〇4、一第一暫存器3〇3、—第二暫存器3〇3,、一第一 驗證電路305、一第二驗證電路3〇6、一第一輸入電路3〇1、 φ 一第二輸入電路301'及一互斥電路307(於本實施例中係一 NAND邏輯閘）該位元線選擇電路3〇4係耦合至二位元線 BL1及BL2。該二位元線肛丨及犯係二條與複數個記憶胞 10相關聯之記憶胞串（參閱圖2)。若與位元線BU相關聯之 複數個記憶胞10被選擇用以儲存資料（即被選擇用以執行 寫入操作），則另一位元線BL2將藉由導通（turn 〇n)電晶體 Μ4、關閉（turnoff)電晶體奶及奶、將訊號v][RpwR接地， 以作為遮蔽位元線（shielding bit line);此時位元線bli _ 稱為選定位i線（selected bit line)。進行寫入操作之前（即 進入第一階段之前，參圖9)，藉由將訊號1>1^〇八〇觸發至低 位準（logic low)、觸發一傳送至該第二驗證電路3〇6之第二 驗§登訊號R2至高位準（i〇gic high)及觸發一傳送至該第一驗 證電路305之第一驗證訊號R00至高位準，將（Q2，Q])之狀態 (係用以表示該第二暫存器303|及該第一暫存器3〇3之輸出 訊號狀態）重置至（U)狀態。於資料輸入時，該第一輸入電 路301及該第二輸入電路3〇Γ中之訊號£]^〇1切換至高位準 以導通電晶體MM及M17。訊號DI1及DI2係二輸入資料（tw〇 I08368.doc •13· •I30S756 one-bit data)。若輸入資料DI1為低位準，則訊號DI1N(為Dll 之互補訊號）為高位準；此時，訊號YDEC也設計成位於高 位準’因此訊號Q1將藉由導通電晶體M22、M23及M24而接 地（處在低位準）。若輸入資料DI1為高位準，則訊號DI1N為 低位準，因此訊號Q1將保持在高位準。同理，相同的資料 輸入方法也適用於訊號Q2，於此不再贅述。 、針對記憶胞進行（10)狀態、（01)狀態及（〇〇)狀態之寫入動 作’係由一第一寫入訊號PGM1及一第二寫入訊號PGM2所 控制。於本實施例中，（11)狀態、（10)狀態、（〇1)狀態及（〇〇) 係分別被稱為零狀態、第一狀態、第二狀態及第三狀態； 欲被寫入至零狀態、第一狀態、第二狀態及第三狀態之記 憶胞則分別稱為零記憶胞、第一記憶胞、第二記憶胞及第 二5己憶胞。參考圖9所示之寫入操作，其包含三階段係分別 對應於圖7(a)、7(b)及7(c)。P1〜P3及VI〜V3分別表示在各階 丰又之寫入期間（Program period)及驗證期間（verify period)。 於P1期間，第一記憶胞藉由該第一寫入訊號1>〇]^1進行寫入 動作（參圖7(a)之實箭號D1)，其中該第一寫入訊號PGMh$ 、、足由複數個第一寫入擊發（first programming shot)而觸發至 南位準；同時，該第二寫入訊號PGM2係經由複數個第二寫 入擊發（Sec〇nd Programming shot)而觸發至高位準（參圖9第 一階段之LP期間其中第二寫入擊發之數目小於或等於第 一寫入擊發之數目。注意圖9第一階段之LP期間之上緣係以 虛線繪製’其係表示LP期間之時間長度可以調整。Nand 邏輯閘307係用以限制訊號Q2,以避免訊號Q2及Qi(即第— 108368.doc -14· E39981 Ί308756 暫存器303及第二暫存器3〇3ι之輸出訊號）產生資料衝突（即 互斥運算），因為此時訊號Q2&Qi係分別位於高位準及低位 、準。因此，NAND邏輯閘307可用於控制栓鎖於該第一及第 二暫存器303及303’之二位元資料之各位元之寫入。另， NAND邏輯閘307限制訊號Q2送至一節點s〇e藉此，該第二 記憶胞及第三記憶胞在寫入完成之前可先被寫入至一準第 二狀態（quaSi-second state)及一半第三狀態（semi_third state)。該準第二狀態係表示部分第二記憶胞在第一階段已 被寫入且完成寫入之動作；該半第三狀態係表示部分第三 記憶胞在第一階段已被寫入且完成寫入之動作。為了驗證 第一記憶胞是否寫入成功，接著進入V1期間；此時施加在 選定字元線SWL(selected word line)上之電壓降至〇3伏 特，其係小於（10)狀態之門檻電壓分佈（參圖3)。意即，若 於第一階段中被寫入之記憶胞之門檻電壓已達到一特定值 (例如大於0.3伏特），則該第一記憶胞便無法導通。接著， 藉由導通電晶體M2及Ml將該選定位元線BL1預充電 (pre-charge)至一電壓源位準vcc。之後（參考圖9之¥1期間） 该第一驗證訊號R00被脈衝觸發（impulse-activated)以導通 電晶體1^119，而電晶體1\)118及1^14則分別因訊號(^2及該節點 SO之高位準而被導通。藉此，訊號(^將切換至高位準，意 即（Q2，Q1)狀態由（10)狀態轉換成（11)狀態，以驗證（1〇)狀態 之寫入動作已完成'此外，處於（〇1)狀態或（〇〇)狀態的記憶 胞將保持訊號Q1之狀態不變，其係因其訊號q2為低位準而 將電晶體Ml8關閉。復參圖7(a)，鋸齒箭號D2及D3係分別 108368.doc -15- E39981 Ί308756 二記憶胞已完成寫入動作 表示部分第二記憶胞及部分第 然而部分則未完成寫入動作。1308756 IX. Description of the Invention: [Technical Field] The present invention relates to a NAND flash memory device ( 〇 meth meth 〇 及 及 及 及 及 及 及 及 及 及 及 及 及A page buffer of a write method, especially a multi-level_cell NAND type that is applied to each memory cell to store two-bit data (tw〇_bit data). A method of writing a flash memory component and a page buffer for executing the write method. [Prior Art] In a conventional NAND type (four) memory, each data cell can store two kinds of data states, and it is possible to store an "on" state ("〇N") or an "off state". Each bit (9) (10) of the information is defined by the "on" and "off" states of the individual memory cells. In conventional NANDs flash memory, in order to store N bit data (N is an integer greater than or equal to 2), N individual δ cells must be used. Therefore, if the traditional N-type flash memory is used, when the number of data bits to be stored increases, the number of memory cells must also increase. The information stored in the single-bit (__bk) memory cell is determined by the programmed status of the memory, and the data is stored in the memory cell. The presence of a memory cell is determined by the threshold voltage of a transistor located in the memory cell. The gate voltage is applied between the closed and source of the transistor to turn on the minimum voltage of the transistor (t_〇n). Fig. 1 is a cross-sectional view of a memory cell transistor that can store two-bit information. It is used in a -NAND type flash memory device. The memory cell 108368.doc ^ 1308756 transistor ίο includes two gates (ie, upper and lower gates) stacked in a channel region between the source and the gate. The upper gate is called the control gate 11' and the lower gate is called the floating gate 12. The floating gate 丨 2 is a charge storage portion surrounded by an insulating material 丨 3 between the control gate 11 and the channel region. Therefore, the state of the data stored in each cell can be distinguished by the threshold voltage of the cell. 2 is a schematic diagram of two memory strings used in a memory cell array in a NAND type flash memory, wherein each memory cell 10 stores binary information. The memory cell array 2 includes a plurality of memory cells 1 串 connected in series between a bit line BL1 or BL2 (bit line) and a ground selection line GSL (gr〇imd select line). A set of memory cells 串 connected in series with a bit line (BL1 or BL2), a string select transist 〇r, and a ground select transistor (GST) is called a memory cell string. The string selection transistor SST and the ground selection transistor GST are used to select a memory cell for writing, and the turn-on or turn off of the string selection solar day SST is performed by a The state of the string select line SSL (string select line) is determined. The string selection transistor SST is selectively switched to couple the associated memory cell string and bit line; the ground selection transistor GST is selectively switched between each memory cell string and a common source line CSL (common source line) The electrical connection between the two (Fig. 3) shows the voltage distribution of the four thresholds of a memory cell based on the data written. As shown in Figure 3, the data written can be expressed in one of the following four voltage distributions: (1) the threshold voltage distribution less than -2.0V, which represents the (108) bis 108368.doc 1308756 bit data; (2) The threshold voltage distribution between 〇.3V and 〇.7V, which represents one bit data of (1〇); (3) the threshold voltage distribution between 1.3V and 1.7V, which is representative of (01) The two-bit data and (4) the threshold voltage distribution between 2.3 V and 2.7 V is the two-dimensional data representing (00). The data can be stored in a memory cell based on the four different threshold voltage distributions described above. A method for writing to a multi-level cell NAND type flash memory has been proposed and will be introduced later. A three-phase program operation (see Figure 5 in '188) is disclosed in U.S. Patent No. 5,768,188, the disclosure of which is incorporated herein by reference. Before the start of the write method, all the memory cells are reset to the (11) state, and then the two-bit data to be written is downloaded to the two registers Q1 and Q2 (see, Figure 1 of Figure 188). The two registers Q2 and Q1 respectively latch the most significant bit (MSB) and the least significant bit (ieast signmcant (10); LSB) of the two-bit data. 4(a) to 4(c) show that the memory cells of each stage in the writing method respectively represent that the memory cells are written to the (10) state, the (01) state, and the (〇〇) state, respectively. In the diagram of FIG. 4(a) (ie, the first stage), the memory cell to be written to the (1 〇) state starts from the (11) state and ends in the (1〇) state, It is represented by solid p〇inter A1; the memory cell to be written to the (00) state starts from the (11) state and ends in the (〇〇) state, which is marked with a virtual arrow ( Dashedp〇inter) A2 said. However, the memory to be written to the (〇1) state has no write operation. The real arrow A1, which starts at the state and ends at (1〇), indicates that all the cells that are to be written to the (1〇) state have completed the writing operation; however, they start at the (11) state and end. The virtual arrow of (〇〇) 108368.doc E39981 Ί308756 唬A2 indicates that some of the memory cells to be written to the (〇〇) state are still in the process of writing. In FIG. 4(b) (ie, the second stage), the memory cell to be written to the (01) state starts from the (11) state and directly transitions to the (〇1) state, which is a real arrow.唬A3 means 'meaning that all the cells that are to be written to the (〇1) state have completed the writing operation. At this time, the memory cell to be written to the (〇〇) state starts to write from the (1〇) state, and the system is represented by the virtual arrow A4, which represents the memory to be written to the (00) state. The cell is still in the process of writing. According to the logic circuit of FIG. 1 of FIG. 1, the latched state and the (〇〇) state of the two registers Q2 and (^) are respectively converted into a (U) state and a (10) state (parameter, The second stage of Fig. 5, 'verification action, will be executed after the write action), that is, the state of register Q2 will be converted from a low level to a high level. Thus, for a memory cell that has been written to the (〇1) state or the (00) state, the write operation (ie, program inhibition) cannot be performed, because the scratchpad Q2 is latched and written. The most significant bit of the high-order data of the binary data is in addition to the 'when (state) state and the (01) state are simultaneously written, the (〇〇) state does not occur in the transition write ( Overprogram). In FIG. 4(c) (ie, the third stage), the memory cell to be written to the (00) state starts from the (〇1) state and ends in the (〇〇) state. (solid pointer) A# indicates that all memory cells that are to be written to the (00) state have completed the write operation. U.S. Patent No. 6,411,551 (which is incorporated herein by reference in its entirety in its entirety in its entirety in in in in in in in 5(a) to 5(c) show the memory cell type transition intention at each stage in the writing method, which respectively represents writing the memory cell to the (10) state, the (01) state, and (00), respectively. )status. Rev. 551, I08368.doc Ί30Β756 The writing method is to solve the problem that the adjacent threshold voltage distribution generated by 188 is too close. The problem is tied to! In 88, the memory cell that is to be written to the state is directly written from the (11) state, and as a result, a wider threshold voltage distribution is generated, thereby causing the voltage distribution of the adjacent thresholds to be too close (ie, forming a comparison). Narrower margin). In Fig. 5(a) (i.e., the first stage), 'when the memory cell to be written to the (10) state performs a write operation (indicated by the actual arrow B1), it is to be separately written to (〇丨) The state and the (〇〇) state of the S memory are also simultaneously written from the (1 1 ) state (indicated by the virtual arrows B2 and B3, respectively). Among them, the virtual arrows B2 and B3 indicate that the writing action of the relevant memory cells has not been fully achieved. In FIG. 5(b) (ie, the second phase), the write operation of the memory cell to be written to the (00) state is still in progress (indicated by the virtual arrow B5); at the same time, to be written to (01) The memory cell of the state starts from the (1〇) state and completes its writing operation (indicated by the real arrow B4), meaning that all the memory cells to be written to the (01) state have completed writing. Into the action. Finally, referring to Fig. 5(c), the memory cell to be written to the (00) state starts from the (01) state and completes its writing operation (indicated by the solid arrow B6). A three-stage writing method is also disclosed in U.S. Patent No. 5,986,929, the disclosure of which is incorporated herein by reference. 6(a) to 6(c) are diagrams showing the state transition of the memory cell at each stage in the writing method, which respectively represent writing the memory cells to the (10) state, the (01) state, and the (00) state, respectively. . In FIG. 6(a) (ie, the first stage), the write operation of the memory cell to be written to the (00) state is inhibited (program) to reduce the (〇〇) state in '188. The occurrence of a write situation. That is, at this stage, only the write operation of the memory cell to be written to the (1〇) state is performed (indicated by the solid arrow C1) and is completed, as shown in Fig. 108368.doc -10- '1308756 6(b) (ie, the second stage;), the real arrow number (: 2 indicates that the writing is to be written to the state. The writing operation initiated by the (11) state has been executed and completed; however, the virtual arrow C3 indicates Some of the memory cells that are to be written to the (〇〇) state are still in the private state. In Figure 6(c) (ie, the third phase), the real arrow indicates that it is to be written to (00). The write operation initiated by the state of the memory cell from the (01) state has been performed and v> 凡成 0 [Summary] φ The main object of the present invention is to provide a multi-levei_cell NAND type flash memory. The method of writing the component utilizes a technique of limiting write (Umited_pr〇gram) in the first stage of the write operation to reduce the write time. Another object of the present invention is to provide an application in a multi-level cell NAND. a page buffer in the type of flash memory to implement the write method. The page buffer is applied with a mutual repulsion. (excluSi〇n circuit) to implement a mutually exclusive operation (exclusi〇n 〇perati〇n), whereby the write time is reduced by 0. To achieve the above object, the present invention discloses a type of flash memory 7L The writing method is applied to a multi-level cell NAND type flash memory component including a plurality of memory cells, and each memory cell is associated with a first_storage register and a second temporary register. The plurality of memories are associated with each other. The cell is divided into four categories: the first crypto cell, the first memory cell, and the third memory cell. The writing method includes the following steps: (a) the plurality of zeros, the first, the second, and the third The memory cell is written to a zero state (zer〇state); (8) the first number of memory cells are written to the -state by the first write signal (first 108368.doc •11. E39981 1308756 state), and by the second write signal, the plurality of second memory cells are written from the zero state to a quasi_second state (quasi_sec〇nd state) and the plurality of second § memories are The zero state is written to a semi-third state; (0 by the second write signal Writing a plurality of second memory cells from the quasi-first state to a second state (sec〇nd state) and writing the plurality of third memory cells from the semi-third state to a quasi-third state ( Quasi_tMrd state); and (d) by the first write signal, the plurality of third memory cells are written from the quasi-first state to a third state. The above steps (a) to (d) After το, each memory cell is in a zero state, a first state, a second state, or a third state. The invention further discloses a page buffer applied to a NAND type flash memory component, comprising: a bit line selection circuit, a first register, a second register, a first input circuit, A second input circuit, a second test. And a private circuit, a second verification circuit and a mutual exclusion circuit. The bit selection circuit is used to determine a selected bit line and a stueldmg bit line. The first register and the second register are programmed to write two-bit data of the plurality of memory cells, wherein the plurality of memory cells are related to The positioning bit line is selected and the binary data is received from the first input circuit and the second input circuit. The first verification circuit and the second verification circuit are configured to verify the plurality of memory cells that are associated with the selected positioning element. The mutual exclusion circuit is configured to perform a mutual-mutation operation to control the writing of each bit in the two-bit data. [Embodiment] Figs. 7(a) to 7(c) show the memory of each stage in the writing method of the present invention, ns^8H (E39981 -12. Ί30δ756 cell state transition indication® i8 is the present invention - an embodiment The circuit diagram of the page buffer. Figure 9 shows the timing diagram of the signal associated with Figure 8. The memory cell state transition diagrams shown in Figures 7(4) through 7(c) are based on the circuit shown in Figure 8, so the following will be made for Figure 8 Figure 8 shows a page buffer 3 of an embodiment of the present invention comprising a bit line selection circuit 3〇4, a first register 3〇3, a second register 3〇3, and a a first verification circuit 305, a second verification circuit 3〇6, a first input circuit 3〇1, a second input circuit 301′, and a mutual exclusion circuit 307 (in this embodiment, a NAND logic gate) The bit line selection circuit 3〇4 is coupled to the two bit lines BL1 and BL2. The two bit lines anal fistula and two lines of memory associated with a plurality of memory cells 10 (see Fig. 2). The plurality of memory cells 10 associated with the bit line BU are selected for storing data (ie, selected to perform a write operation), and another bit line BL2 By turning on the transistor Μ4, turning off the transistor milk and milk, the signal v][RpwR is grounded as a shielding bit line; at this time, the bit line bli _ is called To select the selected bit line. Before the write operation (ie before entering the first stage, refer to Figure 9), trigger the signal 1 >1^〇八〇 to the low level (logic low), trigger The second verification signal R2 to the high level (i〇gic high) sent to the second verification circuit 3〇6 and the first verification signal R00 transmitted to the first verification circuit 305 to the high level will be triggered. The state of (Q2, Q)) is used to indicate that the second register 303| and the output signal state of the first register 3〇3 are reset to the (U) state. The signal in the first input circuit 301 and the second input circuit 3〇Γ is switched to a high level to conduct the transistors MM and M17. The signals DI1 and DI2 are two input data (tw〇I08368.doc •13 · • I30S756 one-bit data). If the input data DI1 is low, the signal DI1N (complementary signal of Dll) is at a high level; The YDEC is also designed to be at a high level. Therefore, the signal Q1 will be grounded (at a low level) by conducting the conductive crystals M22, M23 and M24. If the input data DI1 is at a high level, the signal DI1N is at a low level, so the signal Q1 In the same way, the same data input method is also applicable to the signal Q2, which will not be described here. The write operation of the (10) state, the (01) state, and the (〇〇) state for the memory cell ' is controlled by a first write signal PGM1 and a second write signal PGM2. In the present embodiment, the (11) state, the (10) state, the (〇1) state, and the (〇〇) system are referred to as a zero state, a first state, a second state, and a third state, respectively; The memory cells of the zero state, the first state, the second state, and the third state are respectively referred to as a zero memory cell, a first memory cell, a second memory cell, and a second five memory cells. Referring to the write operation shown in Fig. 9, the three-stage system corresponds to Figs. 7(a), 7(b) and 7(c), respectively. P1 to P3 and VI to V3 respectively indicate the program period and the verify period in each step. During P1, the first memory cell performs a write operation by using the first write signal 1 > 〇]^1 (refer to the solid arrow D1 of FIG. 7(a)), wherein the first write signal PGMh$, Triggering to a south level by a plurality of first programming shots; at the same time, the second write signal PGM2 is triggered to be high by a plurality of second write shots (Sec〇nd Programming shots) Level (refer to the number of second write shots in the LP period of the first stage of Figure 9 is less than or equal to the number of first write shots. Note that the upper edge of the LP period of the first stage of Figure 9 is drawn with a dashed line. The length of time during the LP period can be adjusted. The Nand logic gate 307 is used to limit the signal Q2 to avoid the signals Q2 and Qi (ie, the first 108368.doc -14 · E39981 Ί 308756 register 303 and the second register 3 〇 The output signal of 3ι generates data conflict (ie, mutual exclusion operation), because the signals Q2 &Qi are respectively located at the high level and the low level, and the NAND logic gate 307 can be used to control the latches in the first and second. Write the bits of the two-bit data of the registers 303 and 303'. The NAND logic gate 307 limits the signal Q2 to a node s〇e, whereby the second memory cell and the third memory cell can be written to a quasi-second state (quaSi-second state) and before the writing is completed. a semi-third state. The quasi-second state indicates that a portion of the second memory cell has been written and completed writing in the first phase; the semi-third state indicates that a portion of the third memory cell is in the A phase has been written and the write operation is completed. In order to verify whether the first memory cell is successfully written, it then enters the V1 period; at this time, the voltage applied to the selected word line SWL (the selected word line) falls to 〇3. Volt, which is less than the threshold voltage distribution of the (10) state (see Figure 3), that is, if the threshold voltage of the memory cell written in the first stage has reached a certain value (for example, greater than 0.3 volts), then The first memory cell cannot be turned on. Then, the selected positioning element line BL1 is pre-charged to a voltage source level vcc by the conducting current crystals M2 and M1 (refer to the period of ¥1 in FIG. 9). The first verification signal R00 is triggered by a pulse (impulse-acti Vated) is used to conduct the crystal 1^119, and the transistors 1\)118 and 1^14 are turned on by the signal (^2 and the high level of the node SO respectively). Thereby, the signal (^ will switch to the high level) , that is, the (Q2, Q1) state is converted from the (10) state to the (11) state, to verify that the (1〇) state of the write action has been completed 'in addition, in the (〇1) state or (〇〇) state The memory cell will keep the state of the signal Q1 unchanged, which is turned off by the transistor M18 due to the low level of the signal q2. Referring to Fig. 7(a), the sawtooth arrows D2 and D3 are respectively 108368.doc -15-E39981 Ί308756 Two memory cells have completed the write operation. The partial memory cells and the partial portions have not completed the write operation.
/針對將資料寫人第二記憶胞之動作，參圖9之第二階段， 该第二寫入訊號PGM2mP2期間係位於高位準。之後，第二 記憶胞係自該準第二狀態開始寫入並完成寫入動作(參圖 :⑻之實箭號D4)。為了驗證第二記憶胞是否寫入成功，接 者進入V2期間；此時施加在選定字元線swl上之電壓降至 h3伏特，其係小於（01)狀態之門檻電1分佈（參圖3)。意 即，若於第二階段中被寫入之記憶胞之門檻電壓已達到一 特定值（例如大於1>3伏特），則該第二記憶胞便無法導通。 接著，藉&導通電晶體M2及⑷將該選定位元線犯預充電 (―rge)至一電壓源位準Vee。注意在第二階段中並不需 要觸發該第-寫人訊號PGM1，因已無處於⑽狀態的記憶 胞存在’因其相關聯之第二暫存器303,之輸出訊號(即訊號 Q2)及第一暫存器303之輸出訊號（即訊號Q1)在第一階段時 已經由（10)狀態轉換成（11)狀態。之後（參考圖9之¥2期間） 該第二驗證訊號R2被脈衝觸發以導通電晶體Μι〗；而電晶 體M10則因該節點SO之高位準（即電壓源位準Vc。）而被導 通。藉此’ §fl號Q2將切換至咼位準，意即與第二記憶胞及 第三記憶胞相關聯之（Q2，Q1)狀態將分別由（〇1)狀態及（〇〇) 狀態轉換成（11)狀態及（1 〇)狀態。於第二階段中，部分第二 s己憶胞將自该半弟·=狀態被寫入至該準第三狀雜，：s：係以 鑛齒箭5虎D5表示（參圖7(b))。在本實施例中，該準第三狀離 係指該第二狀態。 108368.doc -16- *130*8756 針對將 > 料寫人剩餘的第三記憶胞之動作（注意部分第 二§己憶胞已在第—階段及第二階段完成寫人的動作），參圖 9之第二階段，該第一寫入訊號pGMi於巧期間係位於高位 準。之後，第三記憶胞係自該準第三狀態（於本實施例中， 該準第三狀態係指該第二狀態）開始寫入並完成寫入動作 (參圖7(C)之實箭號〇6)。為了驗證第三記憶胞是否寫入成 力接著進入V3期間；此時施加在選定字元線SWL上之電 # 壓降至2·3伏特，其係小於（〇〇)狀態之門檻電壓分佈（參圖 3)思即，若於第三階段中被寫入之記憶胞之門檻電壓已 達到一特定值（例如大於2.3伏特），則該第三記憶胞便無法 導通。之後，藉由導通電晶體M2及該選定位元線BU 及該節點SO預充電（pre_charge)至一電壓源位準ν^。當該第 一驗證訊號R〇〇被脈衝觸發以導通電晶體Ml9 ;而電晶體 M18則因訊號Q2之高位準（訊號似於第二階段中已被切換 至高位準）而被導通；同時，電晶體M14則因該節點s〇之高 隹 位準而被導通。藉此，訊號Q1將由低位準而轉換至高位準。 相較於習知之寫入方法，本發明之多層次胞nand型快 閃記憶體元件之寫入方法，在寫入操作的第一階段中利用 一限制寫入之技術（意即，於第一階段即先執行部分第二記 憶胞及部分第三記憶胞之寫入動作，而非等到第二階段及 第三階段再執行），另配合本發明所另外揭示之頁緩衝區， 經上述之詳細說明後，確能達到本發明減少寫入時間之預 期目的。 本發明之技術内容及技術特點已揭示如上，炒 108368.doc -17-/ For the action of writing data to the second memory cell, referring to the second stage of FIG. 9, the second write signal PGM2mP2 is at a high level. Thereafter, the second memory cell starts writing from the quasi-second state and completes the writing operation (see Fig.: (8) the actual arrow number D4). In order to verify whether the second memory cell is successfully written, the receiver enters the V2 period; at this time, the voltage applied to the selected word line sw1 is reduced to h3 volt, which is less than the threshold of the (01) state (see FIG. 3). ). That is, if the threshold voltage of the memory cell written in the second stage has reached a certain value (for example, greater than 1 > 3 volts), the second memory cell cannot be turned on. Then, the selected positioning element is pre-charged (-rge) to a voltage source level Vee by & conducting the crystals M2 and (4). Note that it is not necessary to trigger the first-writer signal PGM1 in the second phase, because the memory cell in the (10) state has no 'output signal (ie, signal Q2) due to its associated second register 303 and The output signal of the first register 303 (ie, the signal Q1) has been converted from the (10) state to the (11) state in the first phase. Thereafter (refer to the period of ¥2 in FIG. 9), the second verification signal R2 is pulse-triggered to conduct the transistor Μι; and the transistor M10 is turned on due to the high level of the node SO (ie, the voltage source level Vc). . Therefore, the §fl number Q2 will switch to the 咼 level, meaning that the (Q2, Q1) state associated with the second memory cell and the third memory cell will be converted from the (〇1) state and the (〇〇) state, respectively. In the (11) state and (1 〇) state. In the second stage, part of the second s-remembered cell will be written to the quasi-third-like genre from the half-dead state, and the s: is represented by the mined-toothed arrow 5 tiger D5 (see Figure 7 (b). )). In the present embodiment, the quasi-third-order separation refers to the second state. 108368.doc -16- *130*8756 The action of the third memory cell that will be written by the > (note that the second part of the memory has completed the writing action in the first stage and the second stage), Referring to the second stage of FIG. 9, the first write signal pGMi is at a high level during the smart period. Thereafter, the third memory cell starts writing and completes the writing operation from the quasi-third state (in the embodiment, the quasi-third state refers to the second state) (refer to the solid arrow of FIG. 7(C) No. 6). In order to verify whether the third memory cell is written into the force and then enters the V3 period; at this time, the voltage applied to the selected word line SWL is reduced to 2.3 volts, which is less than the threshold voltage distribution of the (〇〇) state ( Referring to Fig. 3), if the threshold voltage of the memory cell written in the third stage has reached a certain value (for example, greater than 2.3 volts), the third memory cell cannot be turned on. Thereafter, the conductive source crystal M2 and the selected positioning element line BU and the node SO are pre-charged to a voltage source level ν^. When the first verification signal R is triggered by the pulse to conduct the crystal M11, the transistor M18 is turned on because of the high level of the signal Q2 (the signal seems to be switched to the high level in the second stage); The transistor M14 is turned on due to the high level of the node s〇. Thereby, the signal Q1 will be switched from a low level to a high level. Compared with the conventional writing method, the writing method of the multi-level cell nand type flash memory device of the present invention utilizes a technique of limiting writing in the first stage of the writing operation (ie, first The stage first performs the writing operation of the part of the second memory cell and the part of the third memory cell, and does not wait until the second stage and the third stage are performed again, and further cooperates with the page buffer additionally disclosed by the present invention. After the description, the intended purpose of reducing the write time of the present invention can be achieved. The technical content and technical features of the present invention have been disclosed as above, and the speculation 108368.doc -17-
Ί303756 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修飾。因此，本發明之保護範圍 應不限於實施例所揭示者，而声句 叩應β括各種不背離本發明之 替換及修飾’並為以下之中請專利範圍所涵蓋。 【圖式簡單說明】 圖1係-可儲存二位元資訊之記憶胞電晶體之剖面示意 圖； 圖2係應用在一NAND型快閃記憶體中之記憶胞陣列中 之二記憶胞串示意圖； 圖3係一記憶胞之四種門檻電壓分佈圖； 圖4⑷至4⑷係顯示第一習知技藝中之寫入方法中各階 士又之§己憶胞狀態轉換示意圖； 圖5⑷至5⑷係顯示第二習知技藝中之寫入方法中各階 I又之§己憶胞狀態轉換示意圖； 圖6⑷至6⑷係顯示第三習知技藝中之寫以法中各階 段之記憶胞狀態轉換示意圖； 圖7⑷至7⑷係顯示本發明之寫人方法中各階段之記憶 胞狀態轉換示意圖； 圖8係本發明一實施例之頁緩衝區之電路圖；以及 圖9係顯示與圖8相關訊號之時序圖。 【主要元件符號說明】 10記憶胞電晶體 11控制閘極 12 浮動閘極 13 絕緣材料 108368.doc Ί308756 20 記憶胞陣列 30 301 第一輸入電路 30Γ 303 第一暫存器 303' 304 位元線選擇電路 305 306 第二驗證電路 307 BL1 、BL2 位元線 CSL GSL 地選擇線 GST Ml〜 M24 電晶體 SO SSL 串選擇線 SST WL1 〜WL16 字元線 頁緩衝區 第二輸入電路 第二暫存器 第一驗證電路 互斥電路 共源線 地選擇電晶體 節點 串選擇電晶體A person skilled in the art of 303,756 may still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is not limited by the scope of the invention, and the scope of the invention is not limited by the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a memory cell transistor capable of storing two-bit information; FIG. 2 is a schematic diagram of two memory cell strings used in a memory cell array in a NAND-type flash memory; 3 is a four-thickness voltage distribution diagram of a memory cell; FIGS. 4(4) to 4(4) are diagrams showing the state transitions of each of the steps in the writing method in the first prior art; FIG. 5(4) to 5(4) show the first FIG. 6(4) to FIG. 6(4) show schematic diagrams of memory cell state transitions at various stages in the writing process of the third conventional technique; FIG. 7(4) shows a schematic diagram of the state transition of each phase I in the writing method of the prior art; 7(4) shows a schematic diagram of memory cell state transitions at various stages in the writer method of the present invention; FIG. 8 is a circuit diagram of a page buffer according to an embodiment of the present invention; and FIG. 9 is a timing chart showing signals associated with FIG. [Main component symbol description] 10 memory cell 11 control gate 12 floating gate 13 insulating material 108368.doc Ί308756 20 memory cell array 30 301 first input circuit 30Γ 303 first register 303' 304 bit line selection Circuit 305 306 second verification circuit 307 BL1 , BL2 bit line CSL GSL ground selection line GST M1 ~ M24 transistor SO SSL string selection line SST WL1 ~ WL16 word line page buffer second input circuit second register A verification circuit mutual exclusion circuit common source line selects a transistor node string selection transistor
108368.doc -19-108368.doc -19-