TWI307889B - Data input device for use in semiconductor memory device - Google Patents

Data input device for use in semiconductor memory device Download PDF

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Publication number
TWI307889B
TWI307889B TW095123960A TW95123960A TWI307889B TW I307889 B TWI307889 B TW I307889B TW 095123960 A TW095123960 A TW 095123960A TW 95123960 A TW95123960 A TW 95123960A TW I307889 B TWI307889 B TW I307889B
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Taiwan
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data
output
signal
synchronization
latch
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TW095123960A
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Chinese (zh)
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TW200717523A (en
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Beom-Ju Shin
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Description

1307889 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體裝置設計技術，且更特定而言係關 於一種使用於執行一預取操作以輸入資料之半導體記憶裝 置中的資料輸入裝置。 【先前技術】 為改良資料處理效能，已發展一種可執行預取操作之半 導體記憶裝置。大體而言，該預取操作為一種用於動態隨 機存取記憶體（DRAM)之資料轉移方法，其中資料位元以一 時脈之一上升緣及一下降緣進行同步化。 預取操作技術已得到改良以用於預取更多資料位元。 即，在雙倍資料速率（DDR)SDRAM中，基於2位元預取執行 預取操作。在DDR2 SDRAM及DDR3 SDRAM中，分別基於 4位元預取及8位元預取執行預取操作。 圖1為展示習知DDR2 SDRAM之方塊圖。 如圖示，揭露一用於接收按逐個位元循序輸入之資料的 資料輸入裝置。該資料輸入裝置將循序輸入之資料對準為4 位元並列資料，且隨後輸出該經對準之4位元資料 (ALGN0、ALGN1、ALGN2、ALGN3)。如以上所述，將對 準過程（即，將按逐個位元循序輸入之資料對準為並列形式） 稱為預取操作。 舉例而言，在突發長度為4之情況下，在最末之第四資料 位元輸入之後，循序輸入之4個資料位元同時儲存至記憶體 單元中。因此，在最末之第四資料位元輸入之前，先前輸 112669.doc 1307889 入之三個資料位元儲存於該資料輸入裝置中之一移位暫存 器中。由於一資料位元與一資料選通訊號DQS同步輸入， 因此該移位暫存器與資料選通訊號DQS同步操作，使得新 輸入之資料位元不會覆寫先前輸入之資料位元。 圖2為描述習知資料輸入裝置之方塊圖。 如圖示，習知資料輸入裝置包括第一緩衝器10、同步控 制單元40及一同步單元。 第一缓衝器1 0回應於驅動訊號EN，接收資料DIN。同步 控制單元40回應於驅動訊號EN，產生在資料選通訊號DQS 之一邊緣處啟動之第一同步訊號DQSRP4D及第二同步訊號 DQSFP4D。該同步單元與第一同步訊號DQSRP4D及第二同 步訊號DQSFP4D同步，儲存輸出自第一緩衝器10之内部資 料IN，並輸出所儲存資料為經對準之並列資料ALGN0、 ALGN1、ALGN2及 ALGN3。 同步控制單元40包括：第二緩衝器42，其用以回應於驅 動訊號EN，接收資料選通訊號DQS及反相資料選通訊號 DQSB ;訊號產生單元44,其用於產生在第二緩衝器42之輸 出訊號之一上升緣及一下降緣處分別啟動之第一預同步訊 號DQSRP4及第二預同步訊號DQSFP4 ;第一延遲元件46， 其用於藉由使第一預同步訊號DQSRP4延遲一預定延遲時 間，來產生第一同步訊號DQSRP4D ;及第二延遲元件48， 其用於藉由使第二預同步訊號DQSFP4延遲一預定延遲時 間，來產生第二同步訊號DQSFP4D。 該同步單元包括鎖存器單元20及延遲單元30。 112669.doc 1307889 鎖存器單元20回應於第一同步訊號DqSRP4D&第二同 步讯號DQSFP4D，以兩列並列形式儲存内部資料IN。延遲 單元30使鎖存器單元20之輪出資料延遲—預定延遲時間， 從而產生4位元經對準之資料alGNO、ALGN1、ALGN2及 ALGN3。 鎖存器單元20包括：第一鎖存器21，其用於與第一同步 訊號DQSRP4D之一邊緣同步，來儲存内部資料IN;第二鎖 存器22，其用於與第二同步訊號DQSFP4D之一邊緣同步， 儲存第一鎖存器21之資料，及輸出所儲存資料作為第一輸 出資料D2;帛三鎖存器23,其用於與第二同步訊號 DQSFP4D同步，儲存内部f料…，及輸出所儲存資料作為 第二輸出資料D3;第四鎖存器24 ’其用於與第—同步訊號 DQSRP4D之-邊緣同步，來儲存第二鎖存器之資料 五鎖存器25 I 用於 I 馇 _r=i 士一#______1307889 IX. Description of the Invention: Field of the Invention The present invention relates to semiconductor device design techniques, and more particularly to a data input device for use in a semiconductor memory device for performing a prefetch operation to input data. [Prior Art] In order to improve data processing performance, a semiconductor memory device capable of performing a prefetch operation has been developed. In general, the prefetch operation is a data transfer method for dynamic random access memory (DRAM) in which data bits are synchronized with one rising edge and one falling edge of a clock. Prefetching techniques have been improved for prefetching more data bits. That is, in Double Data Rate (DDR) SDRAM, a prefetch operation is performed based on 2-bit prefetching. In DDR2 SDRAM and DDR3 SDRAM, prefetch operations are performed based on 4-bit prefetching and 8-bit prefetching, respectively. 1 is a block diagram showing a conventional DDR2 SDRAM. As shown, a data input device for receiving data sequentially input on a bit by bit basis is disclosed. The data input device aligns the sequentially input data into 4-bit side-by-side data, and then outputs the aligned 4-bit data (ALGN0, ALGN1, ALGN2, ALGN3). As described above, the alignment process (i.e., aligning the data sequentially input one by one in a side-by-side format) is referred to as a prefetch operation. For example, in the case where the burst length is 4, after the last fourth data bit is input, the 4 data bits sequentially input are simultaneously stored in the memory unit. Therefore, before the last fourth data bit is input, the three data bits previously input 112669.doc 1307889 are stored in one of the shift registers in the data input device. Since a data bit is synchronously input with a data selection communication number DQS, the shift register is synchronized with the data selection communication number DQS, so that the newly input data bit does not overwrite the previously input data bit. Figure 2 is a block diagram depicting a conventional data input device. As shown, the conventional data input device includes a first buffer 10, a synchronization control unit 40, and a synchronization unit. The first buffer 10 receives the data DIN in response to the drive signal EN. The synchronization control unit 40 generates a first synchronization signal DQSRP4D and a second synchronization signal DQSFP4D activated at one edge of the data selection communication number DQS in response to the driving signal EN. The synchronization unit synchronizes with the first synchronization signal DQSRP4D and the second synchronization signal DQSFP4D, stores the internal data IN output from the first buffer 10, and outputs the stored data as aligned parallel data ALGN0, ALGN1, ALGN2 and ALGN3. The synchronization control unit 40 includes a second buffer 42 for receiving the data selection communication number DQS and the inverted data selection communication number DQSB in response to the driving signal EN. The signal generating unit 44 is configured to generate the second buffer. The first pre-synchronization signal DQSRP4 and the second pre-synchronization signal DQSFP4 respectively activated by one rising edge and one falling edge of the output signal of 42; the first delay element 46 is configured to delay the first pre-synchronization signal DQSRP4 by one The predetermined delay time is used to generate the first synchronization signal DQSRP4D, and the second delay element 48 is configured to generate the second synchronization signal DQSFP4D by delaying the second pre-synchronization signal DQSFP4 by a predetermined delay time. The synchronization unit includes a latch unit 20 and a delay unit 30. 112669.doc 1307889 The latch unit 20 stores the internal data IN in two columns in parallel in response to the first synchronization signal DqSRP4D & second synchronization signal DQSFP4D. Delay unit 30 delays the wheeled data of latch unit 20 by a predetermined delay time, thereby producing 4-bit aligned data alGNO, ALGN1, ALGN2, and ALGN3. The latch unit 20 includes a first latch 21 for synchronizing with one edge of the first synchronization signal DQSRP4D to store the internal data IN, and a second latch 22 for the second synchronization signal DQSFP4D. One edge synchronization, storing the data of the first latch 21, and outputting the stored data as the first output data D2; the third latch 23 for synchronizing with the second synchronization signal DQSFP4D, storing the internal f... And outputting the stored data as the second output data D3; the fourth latch 24' is used for synchronizing with the edge of the first synchronization signal DQSRP4D to store the data of the second latch, the fifth latch 25 I On I 馇_r=i 士一#______

資料作為第四輸出資料D1。The data is used as the fourth output data D1.

D1及D3延遲—預定延遲時間。 圖3為描述圖2中所示之習知 資料輸入裝置之操作的波形 112669.doc 1307889 圖。 參看圖2及圖3，以下描述習知資料輸入裝置之操作。 資料DIN與資料選通訊號DQS之一上升緣及一下降緣同 步輸入。此處，以輸入時序之次序對資料DIN編號。 第一缓衝器10在驅動訊號EN啟動時接收資料DIN並輸出 所接收的資料，作為内部資料IN，其中内部資料IN具有一 内部電壓位準。同步控制單元40分別經由接收資料選通訊 號DQS及反相資料選通訊號DQSB之第二緩衝器42及訊號 產生單元44，依次與資料選通訊號DQS之一上升緣及一下 降緣同步而使第一預同步訊號DQSRP4及第二預同步訊號 DQSFP4啟動兩次。 其後，第一預同步訊號DQSRP4及第二預同步訊號 DQSFP4分別由第一及第二延遲元件46及48延遲，以滿足一 内部資料之設定時間及保持時間。 其後，包括於鎖存器單元20中之第一至第七鎖存器21至 27回應於循序啟動之第一同步訊號DQSRP4D及第二同步訊 號DQSFP4D，鎖存4位元内部資料AO、Al、A2及A3。即， 鎖存器單元20藉由使用由第一同步訊號DQSRP4D及第二同 步訊號DQSFP4D操作之第一至第七鎖存器21至27，將經由 第一緩衝器10循序輸入之内部資料AO、Al、A2及A3對準為 並列形式。 其後，延遲單元30另外延遲輸出自第二、第三、第六及 第七鎖存器22、23、26及27之第一至第四輸出資料D2、D3、 D0及 D1。 112669.doc 1307889 同時，根據習知資料輪入裝 入杳粗斜、-隹* # , 為在無損失情況下將輸D1 and D3 delay - predetermined delay time. Figure 3 is a diagram of waveform 112669.doc 1307889 depicting the operation of the conventional data input device shown in Figure 2. Referring to Figures 2 and 3, the operation of the conventional data input device will be described below. The data DIN is selected as one of the rising edge and the falling edge of the data selection communication number DQS. Here, the data DIN number is given in the order of the input timing. The first buffer 10 receives the data DIN when the drive signal EN is activated and outputs the received data as the internal data IN, wherein the internal data IN has an internal voltage level. The synchronization control unit 40 sequentially synchronizes the rising edge and the falling edge of the data selection communication number DQS with the second buffer 42 and the signal generating unit 44 of the data selection communication number DQS and the inverted data selection communication number DQSB, respectively. The first pre-sync signal DQSRP4 and the second pre-sync signal DQSFP4 are activated twice. Thereafter, the first pre-sync signal DQSRP4 and the second pre-sync signal DQSFP4 are delayed by the first and second delay elements 46 and 48, respectively, to satisfy the set time and hold time of an internal data. Thereafter, the first to seventh latches 21 to 27 included in the latch unit 20 are in response to the sequentially activated first synchronization signal DQSRP4D and the second synchronization signal DQSFP4D, and latch the 4-bit internal data AO, Al. , A2 and A3. That is, the latch unit 20 sequentially inputs the internal data AO, which is sequentially input via the first buffer 10, by using the first to seventh latches 21 to 27 operated by the first synchronizing signal DQSRP4D and the second synchronizing signal DQSFP4D, Al, A2, and A3 are aligned in a side-by-side form. Thereafter, the delay unit 30 additionally delays the first to fourth output data D2, D3, D0, and D1 output from the second, third, sixth, and seventh latches 22, 23, 26, and 27. 112669.doc 1307889 At the same time, according to the customary data, the wheel is loaded into the slanting slant, -隹* #, which will be lost without loss.

入資科對4為剌H n个 〗入一資料位元時，資料應 、.坐移位而加以儲存。此時， ’、' b η :資料移位與一資料選通訊 唬之上升緣及一下降緣同步勃 續的資# # # 、d: β # 執订，因此功率則歸因於連 ^ 需要大尺寸驅動器以便驅 動一同步訊號以用於資料移位。 ^ ^ 、 因此，功率消耗增加。 資料的率消耗發生於用以對準經由資料墊而輸入之 問題。、，—貝枓輸人裝置處，因此上述功率消耗成為嚴重 【發明内容】 因此，本發明之一 資料輪入裝置。 目標為提供一種用於減少功率消耗之 根據本發明之—態樣，提供—種使用於半導體記憶裝置 :之資料輸入裝置，其包括：一同步控制單元，其用於回 應於了驅動訊號而接收一同步於一資料位元之資料選通訊 號以便產生-同步訊號；及一同步單元，其用於將按逐 個位元循序輸入之内部資料儲存至複數個同步儲存元件及 非同步儲存元件中，且用於以同步於該同步訊號方式，同 時輸出該經儲存之資料作為並列對準的資料。 根據本發明之一態樣，提供一種半導體記憶裝置，其包 括：—内部資料選通訊號產生器，其用以回應於—資料選 通訊號而產生一内部資料選通訊號；一第一資料對準單 几’其用以回應於該内部資料選通訊號而將循序輪入之資 料的一部分對準為第一並列資料；一延遲單元，其用於使 112669.doc 1307889 該第一並列資料延遲一預定時間以輸出經延遲之資料；— 第二資料對準單元’其用以回應於該内部資料選通訊號而 將該經延遲之資料對準為第二並列資料；及一第三資料對 準單元，其用於將該第一並列資料及該第二並列資料對準 為第三並列資料。 【實施方式】 下文中將參看附圖來詳細描述根據本發明之資料輸入裝 置。 ’ 圖4為根據本發明之較佳實施例之使用於半導體記憶裝 置中之資料輸入裝置的方塊圖。 如圖示，該資料輸入裝置包括第一緩衝器1〇〇、同步控制 單元400及一同步單元。 第一緩衝器100回應於驅動訊號εν，接收資料DIN。同步 控制單元400回應於驅動訊號EN，產生在資料選通訊號DQS 之一邊緣處啟動之第一同步訊號DQSRP4D及第二同步訊號 DQSFP4D。該同步單元藉由使用一同步延遲元件及一非同 步延遲元件’來對準自第一緩衝器1〇〇按逐個位元循序輸出 之内部資料IN，且隨後藉由使複數個位元之資料同步於第 一同步訊號DQSRP4D及第二同步訊號DQSFP4D，來同時輸 出並列型經對準之資料ALGNO、ALGN1、ALGN2及ALGN3。 此處，由於同步延遲元件以同步於對應同步訊號方式來 接收並儲存資料，因此使資料延遲對應同步訊號之一個循 環。可用諸如移位元件或正反器之儲存元件來體現同步延 遲元件。 112669.doc -10- 1307889 非同步延遲元件接收資料而不受歸因於特定訊號之操作 限制。由於非同步延遲元件亦延遲一對應資料位元，因此 可用交叉耦合之鎖存器或電容器與反相器來體現非同步延 遲元件。 同步控制單元400包括：第二缓衝器420，其用以回應於 驅動訊號EN，接收資料選通訊號DQS及反相資料選通訊號 DQSB ;訊號產生單元440，其用於產生在第二緩衝器420 之輸出訊號之一上升緣及一下降緣處分別啟動之第一預同 步訊號DQSRP4及第二預同步訊號DQSFP4 ;第一延遲元件 460，其用於藉由使第一預同步訊號DQSRP4延遲一預定延 遲時間，產生第一同步訊號DQSRP4D ;及第二延遲元件 480，其用於藉由使第二預同步訊號DQSFP4延遲一預定延 遲時間，產生第二同步訊號DQSFP4D。 該同步單元包括鎖存器單元200及延遲單元300。 鎖存器單元200藉由由第一同步訊號DQSRP4D及第二同 步訊號DQSFP4D操作之非同步延遲元件及同步延遲元件， 以成兩列之並列形式儲存内部資料IN。延遲單元300使鎖存 器單元200之第一至第四輸出資料D0至D3延遲一預定延遲 時間，從而產生4位元經對準之資料ALGN0、ALGN1、 ALGN2及 ALGN3。 鎖存器單元200包括：第一鎖存器210，其用於與第一同 步訊號DQSRP4D之一邊緣同步，來儲存内部資料IN;第二 鎖存器220，其用於與第二同步訊號DQSFP4D之一邊緣同 步，來儲存第一鎖存器210之資料，且輸出所儲存資料作為 I12669.doc -11 - 1307889 第一輸出資料D2 ;筮-μ DQSFP4D之-邊緣門牛+胃咖’其用於與第二同步訊號 資料作為第二輸出資仙3;第—n讀出所儲存 於儲存輸出自第二鎖存器 步^遲几件240,其用 步延遲元_，其用於儲存=第出資_;第二非同 輸出資⑽；第四鎖存器260,其用於第- DQSFP4D之一邊緣鬥牛A 、 、/、第一同步訊號 之資料_ 來儲存第一非同步延遲元㈣〇 之貝料（D〇5)’且輪出 第五鎖存器27〇,科作為第三輸出資料D〇;及 同步，來儲存[非同步訊號DQSFP4D之一邊緣 存第一非同步延遲元件250之資料（D15)，且輸 出所儲存資料作為第四輸出資料m。 L遲單7G300包括第三至第六延遲元件咖至彻該等延 遲元件分別用於使第-、第三、第四及第二輸出資細、 D〇、D1及D3延遲一預定延遲時間。 因此根據本發明之較佳實施例，包括非同步延遲元件 從而可儲存循序輪入之資料’直至輸入最末之第四資料位 兀藉由使用非同步延遲元件’可防止與第-同步訊號 DQSRP4D>® ^ - n u 久卑一同步訊號DQSFP4D同步之鎖存器之連續 操作所引起的功率消耗。 圖5為展不圖4中所示之第一非同步延遲元件240的示意 電路圖此處’第二非同步延遲元件250之結構相同於第 一非同步延遲元件240之結構。 如圖不’第—非同步延遲元件240包括：第一反相器II， 其用於使經由—輪入節點輸入之輸入訊號（IN)反相；第一 112669.doc 1307889 電合裔CPI，其係用p型金屬氧化物_導體（pM〇s)電晶體予 以體現’帛切換器SW1，其用於將第一電容器CP1連接至 第反相器II之-輸出節點；第二電容器CN1，其係用η型 金屬氧化物半導體（Ν刪）電晶體^以體現；第二切換器 SW2,其用於將第二電容器⑽連接至第—反相㈣之該輸 出節點’第一反相崙12’其用於使第一反相器η之輸出反 相；第三切換器SW3，其用於將該輸入節點連接至第二反 相器12之—輸出節點；第三反相器π，其用於使第二反相器 12之輸出反相’第二電容器cp2，其係用電晶體予以 體現；第四切換器請4,其用於將第三電容器cp2連接至第 三反相器13之一輪出節點；第四電容器CN4,其以NM0S電 曰曰體予以體現’第五切換器SW5，其用於將第四電容器⑶2 連接至第三反相器13之該輪㈣點；第四反相器其用於 使第三反相器13之輸出反相；第六切換器SW6,其用於將 第四反相器14之一輸出節點連接至用於輸出一輸出訊號 out的輸出節點；及第七切換器sw7’其用於將輸入節點 連接至輪出節點。 〃有上述結構之第—非同步延遲元件24q藉由閉合/斷開 切換器來增加或不增加歸因於電容器之額外延遲。因此， 藉由控制切換窃’可控制當訊號自輸入節點到達輪出節點 時所產生之延遲時間。 ” 圖^為圖4中所示之第一鎖存器21〇之示意性電路圖。此 :二二至第五鎖存器之每-結構皆相同於第-鎖存器21〇 之結構。 112669.doc -13- 1307889 如圖示’第一鎖存器210包括：差動放大器212，其用於 在時脈訊號CK啟動時接收輸入訊號D作為差動輸入；驅動 器214’其用於驅動差動放大器212之一輸出；及輸出單元 216’其用於儲存並輸出驅動器214之輸出。 第鎖存器210接收第一同步訊號DQ SRP 4 D作為時脈訊 號（：&，且接收輸出自第一缓衝器100之内部資料IN作為輪 入訊號D。因此，第一鎖存器210在時脈訊號CK啟動時儲存 並輸出輸入訊號D。 圖7為展示圖4中所示之資料輸入裝置之操作的波形圖。 參看圖4至圖7’以下描述該資料輸入裝置之操作。 第一緩衝器100在啟動驅動訊號EN時接收資料din並輸 出所接收之資料作為内部資料IN，其中内部資料IN具有一 内部電壓位準。同步控制單元4〇〇分別經由反相第二緩衝器 420(其接收資料選通訊號dqs及反相資料選通訊號dqSB) 及訊號產生單元440,依次與資料選通訊號dqs之一上升緣 及一下降緣同步’以使第一預同步訊號DQSRP4及第二預同 步訊號DQSFP4兩次啟動。 其後，第一預同步訊號DQSRP4及第二預同步訊號 DQSFP4分別由第一延遲元件460及第二延遲元件480予以 延遲’使付内部資料IN滿足對應於第一同步訊號DQSRP4D 及第一同步訊號DQSFP4D之設定時間及保持時間。經延遲 之預同步訊號DQSRP4及DQSFP4分別輸出作為第一同步訊 號DQSRP4D及第二同步訊號DQSFP4D。 其後’第一鎖存器210回應於第一同步訊號DQSRp4D之 112669.doc •14· 1307889 啟動，儲存内部資料位元AO。 其後，當第二同步訊號DQSFP4D啟動時，第二鎖存器220 儲存第一鎖存器210之輸出資料位元（A0)，且第三鎖存器 230儲存内部資料位元A卜在一預定時間之後，第一非同步 延遲元件240及第二非同步延遲元件250分別儲存並輸出内 部資料位元A0及A1。 因此，在第一鎖存器210至第三鎖存器230以同步於第一 同步訊號DQSRP4D及第二同步訊號DQSFP4D方式接收資 料時，在第二鎖存器220及第三鎖存器230儲存資料之後之 一預定延遲時間之後，第一非同步延遲元件240及第二非同 步延遲元件250儲存資料，而不需同步於一同步訊號。 其後，當第一同步訊號DQSRP4D啟動時，第一鎖存器210 儲存新輸入之内部資料位元A2。 其後，當第二同步訊號DQSFP4D啟動時，第二鎖存器220 儲存第一鎖存器210之輸出資料位元（A2)，且第三鎖存器 230儲存新輸入之内部資料位元A3。第四鎖存器260儲存第 一非同步延遲元件240之輸出資料位元（A0)，且第五鎖存器 270儲存第二非同步延遲元件250之輸出資料位元（A1)。 延遲單元300將一附加延遲加至儲存於第二、第三、第六 及第七鎖存器220、230、260及270中之資料位元A2、A3、 A0及A1，以產生第一至第四並列資料位元ALGN0至 ALGN3。 包括第一非同步延遲元件240及第二非同步延遲元件 250，以使得第四及第五鎖存器260及270可穩定接收資料。 112669.doc -15- 1307889 即，在無第一非同步延遲元件240及第二非同步延遲元件 250之情況下，當第二鎖存器220及第三鎖存器23〇儲存並輸 出與第二同步訊號DQSFP4D同步之内部資料位元八〇及A1 咬’因為無足夠之時間容限，所以第四及第五鎖存器26〇及 270不能儲存輸出自第二鎖存器220及第三鎖存器23〇之内 部資料位元A0及A1。即，對於將接收資料位元之鎖存器而When the capital account is 4 for 剌H n 〗 into a data bit, the data should be stored and transferred. At this time, ', ' b η : data shift and a data selection communication 唬 rising edge and a falling edge synchronous continuation of the capital # # #, d: β # binding, so the power is attributed to even ^ need A large size driver drives a sync signal for data shifting. ^ ^ , therefore, power consumption increases. The rate of data consumption occurs in order to align with the input via the data pad. The above-mentioned power consumption becomes serious. Therefore, one of the present invention is a wheel-in device. The object is to provide a data input device for use in a semiconductor memory device according to the present invention for reducing power consumption, comprising: a synchronous control unit for receiving in response to a driving signal Synchronizing a data transmission number of a data bit to generate a synchronization signal; and a synchronization unit for storing the internal data sequentially input one by one in a plurality of synchronous storage elements and non-synchronous storage elements, And used to synchronize the synchronous signal mode, and simultaneously output the stored data as side-by-side aligned data. According to an aspect of the present invention, a semiconductor memory device is provided, comprising: an internal data selection communication number generator for generating an internal data selection communication number in response to the data selection communication number; a first data pair A portion of the information that is used to align the sequential data into the first parallel data in response to the internal data selection communication number; a delay unit for delaying the first parallel data of 112669.doc 1307889 a predetermined time to output the delayed data; - a second data aligning unit operative to align the delayed data with the second data in response to the internal data selection communication number; and a third data pair a quasi unit for aligning the first parallel data and the second parallel data into a third parallel data. [Embodiment] Hereinafter, a material input device according to the present invention will be described in detail with reference to the accompanying drawings. Figure 4 is a block diagram of a data input device for use in a semiconductor memory device in accordance with a preferred embodiment of the present invention. As shown, the data input device includes a first buffer 1 , a synchronization control unit 400, and a synchronization unit. The first buffer 100 receives the data DIN in response to the drive signal εν. The synchronization control unit 400 generates a first synchronization signal DQSRP4D and a second synchronization signal DQSFP4D activated at one edge of the data selection communication number DQS in response to the driving signal EN. The synchronization unit aligns the internal data IN sequentially outputted from the first buffer 1 by bit by bit by using a synchronous delay element and an asynchronous delay element ', and then by making the data of the plurality of bits Simultaneously outputting the parallel-type aligned data ALGNO, ALGN1, ALGN2, and ALGN3 simultaneously with the first synchronization signal DQSRP4D and the second synchronization signal DQSFP4D. Here, since the synchronous delay element receives and stores data in synchronization with the corresponding synchronous signal mode, the data is delayed corresponding to one cycle of the synchronous signal. The synchronous delay element can be embodied by a storage element such as a shifting element or a flip-flop. 112669.doc -10- 1307889 Non-synchronous delay elements receive data without being restricted by the operation due to a particular signal. Since the asynchronous delay element is also delayed by a corresponding data bit, the non-synchronous delay element can be represented by a cross-coupled latch or capacitor and an inverter. The synchronization control unit 400 includes a second buffer 420 for receiving the data selection communication number DQS and the inverted data selection communication number DQSB in response to the driving signal EN. The signal generating unit 440 is configured to generate the second buffer. The first pre-synchronization signal DQSRP4 and the second pre-synchronization signal DQSFP4 respectively activated at one rising edge and one falling edge of the output signal of the device 420; the first delay element 460 is configured to delay the first pre-synchronization signal DQSRP4 The first synchronization signal DQSRP4D is generated for a predetermined delay time, and the second delay element 480 is configured to generate the second synchronization signal DQSFP4D by delaying the second pre-synchronization signal DQSFP4 by a predetermined delay time. The synchronization unit includes a latch unit 200 and a delay unit 300. The latch unit 200 stores the internal data IN in a parallel arrangement of two columns by the asynchronous delay element and the synchronous delay element operated by the first synchronization signal DQSRP4D and the second synchronization signal DQSFP4D. The delay unit 300 delays the first to fourth output data D0 to D3 of the latch unit 200 by a predetermined delay time, thereby generating 4-bit aligned data ALGN0, ALGN1, ALGN2, and ALGN3. The latch unit 200 includes a first latch 210 for synchronizing with one edge of the first synchronization signal DQSRP4D to store the internal data IN, and a second latch 220 for the second synchronization signal DQSFP4D. One edge is synchronized to store the data of the first latch 210, and the stored data is output as I12669.doc -11 - 1307889 first output data D2; 筮-μ DQSFP4D - edge gate cattle + stomach coffee' And the second synchronization signal data is used as the second output resource 3; the -n readout is stored in the storage output from the second latch step later, and the step delay element_ is used for storing = The first non-synchronous delay element (4) is used for the first non-synchronous delay element (4) of the first edge of the first DQSFP4D. 〇的贝料(D〇5)' and the fifth latch 27〇 is rotated, the section is used as the third output data D〇; and the synchronization is stored to store the first asynchronous delay element of one edge of the non-synchronous signal DQSFP4D 250 data (D15), and the stored data is output as the fourth output data m. The L-single 7G300 includes third to sixth delay elements until the delay elements are used to delay the first, third, fourth, and second output coefficients, D, D1, and D3 by a predetermined delay time, respectively. Therefore, according to a preferred embodiment of the present invention, the asynchronous delay element is included to store the sequentially rotated data 'until the last fourth data bit is input, and the first synchronization signal DQSRP4D> can be prevented by using the asynchronous delay element. ;® ^ - nu The power consumption caused by the continuous operation of the synchronous latch DQSFP4D synchronous latch. 5 is a schematic circuit diagram of the first asynchronous delay element 240 shown in FIG. 4 where the structure of the second asynchronous delay element 250 is the same as that of the first asynchronous delay element 240. The non-synchronous delay element 240 includes: a first inverter II for inverting an input signal (IN) input via the wheel-in node; the first 112669.doc 1307889 electric CPI, It is embodied by a p-type metal oxide-conductor (pM〇s) transistor, which is used to connect the first capacitor CP1 to the output node of the inverter II; the second capacitor CN1, It is embodied by an n-type metal oxide semiconductor (TFT) transistor; the second switch SW2 is used to connect the second capacitor (10) to the output node of the first-inverting (four) 'first reverse lun 12' is used to invert the output of the first inverter η; a third switch SW3 is used to connect the input node to the - output node of the second inverter 12; the third inverter π, It is used to invert the output of the second inverter 12 'the second capacitor cp2, which is embodied by a transistor; the fourth switch 4 is used to connect the third capacitor cp2 to the third inverter One of the 13 rounds of the node; the fourth capacitor CN4, which is embodied by the NM0S electric body, the fifth switch SW5, which Connecting the fourth capacitor (3) 2 to the wheel (four) point of the third inverter 13; the fourth inverter for inverting the output of the third inverter 13; and a sixth switch SW6 for An output node of the fourth inverter 14 is connected to an output node for outputting an output signal out; and a seventh switcher sw7' is used to connect the input node to the wheel-out node. The first-asynchronous delay element 24q having the above structure increases or does not increase the additional delay due to the capacitor by closing/disconnecting the switch. Therefore, the delay time generated when the signal arrives at the round-out node from the input node can be controlled by controlling the switching. Fig. 2 is a schematic circuit diagram of the first latch 21A shown in Fig. 4. Here, the structure of each of the second to fifth latches is the same as that of the first latch 21〇. .doc -13- 1307889 As shown, the first latch 210 includes a differential amplifier 212 for receiving an input signal D as a differential input when the clock signal CK is activated, and a driver 214' for driving the difference One output of the dynamic amplifier 212; and an output unit 216' for storing and outputting the output of the driver 214. The latch 210 receives the first synchronization signal DQ SRP 4 D as a clock signal (: & The internal data IN of the first buffer 100 is used as the round signal D. Therefore, the first latch 210 stores and outputs the input signal D when the clock signal CK is activated. FIG. 7 shows the data input shown in FIG. Waveform diagram of the operation of the device. The operation of the data input device is described below with reference to Figures 4 to 7. The first buffer 100 receives the data din when the drive signal EN is activated and outputs the received data as the internal data IN, wherein the internal The data IN has an internal voltage level. The control unit 4 is respectively connected to the second buffer 420 (which receives the data selection communication number dqs and the inverted data selection communication number dqSB) and the signal generation unit 440, and sequentially rises with one of the data selection communication numbers dqs and The falling edge synchronization is performed to enable the first pre-synchronization signal DQSRP4 and the second pre-synchronization signal DQSFP4 to be started twice. Thereafter, the first pre-synchronization signal DQSRP4 and the second pre-synchronization signal DQSFP4 are respectively caused by the first delay element 460 and the second delay. The component 480 is delayed to 'send the internal data IN to meet the set time and hold time corresponding to the first synchronization signal DQSRP4D and the first synchronization signal DQSFP4D. The delayed pre-sync signals DQSRP4 and DQSFP4 are respectively output as the first synchronization signal DQSRP4D and the first Second synchronization signal DQSFP4D. Thereafter, the first latch 210 is activated in response to 112669.doc •14·1307889 of the first synchronization signal DQSRp4D, and stores the internal data bit AO. Thereafter, when the second synchronization signal DQSFP4D is activated, The second latch 220 stores the output data bit (A0) of the first latch 210, and the third latch 230 stores the internal data bit A for a predetermined time. The first asynchronous delay element 240 and the second asynchronous delay element 250 respectively store and output internal data bits A0 and A1. Therefore, the first to third latches 210 to 230 are synchronized to the first synchronization. When the signal DQSRP4D and the second synchronization signal DQSFP4D receive data, after the predetermined delay time after the second latch 220 and the third latch 230 store the data, the first asynchronous delay element 240 and the second asynchronous delay Component 250 stores data without having to synchronize to a sync signal. Thereafter, when the first synchronization signal DQSRP4D is activated, the first latch 210 stores the newly input internal data bit A2. Thereafter, when the second synchronization signal DQSFP4D is activated, the second latch 220 stores the output data bit (A2) of the first latch 210, and the third latch 230 stores the newly input internal data bit A3. . The fourth latch 260 stores the output data bit (A0) of the first asynchronous delay element 240, and the fifth latch 270 stores the output data bit (A1) of the second asynchronous delay element 250. The delay unit 300 adds an additional delay to the data bits A2, A3, A0, and A1 stored in the second, third, sixth, and seventh latches 220, 230, 260, and 270 to generate the first to The fourth parallel data bits ALGN0 to ALGN3. The first asynchronous delay element 240 and the second asynchronous delay element 250 are included to enable the fourth and fifth latches 260 and 270 to stably receive data. 112669.doc -15- 1307889 That is, in the case where there is no first asynchronous delay element 240 and second asynchronous delay element 250, when the second latch 220 and the third latch 23 are stored and output The internal data bit of the two synchronous signals DQSFP4D is synchronized and the A1 bite 'because there is not enough time tolerance, the fourth and fifth latches 26 and 270 cannot store the output from the second latch 220 and the third. The latches 23 have internal data bits A0 and A1. That is, for the latch that will receive the data bit

言，資料應滿足將一同步訊號之一上升緣作為參考點之設 定時間及保持時間。 因此由於第一及第二非同步延遲元件260及270使第二 鎖存器22G及第三鎖存！| 23G之輸出資料延遲—預定延遲時 間’因此輸出資料位元（AO、A1)可滿足下—啟動之第二同 步訊號DQSFP4D之設定時間及保持時間，且目此，第四及 第五鎖存器260及270接收資料。 一因此’根據本發明之較佳實施例，藉由使用非同步延遲 元件來儲存資料，可姑小你 減夕與一矾諕之一上升緣及一下降緣 …仃之連續移位操作。因此，功率消耗可減少。 :外’由於使用同步訊號之區塊之數目減 由使用具有較小，驅叙私ή J精 此，驅動器之尺寸可话又之驅動器來產生同步訊號。因 因此，藉由使用且功率消耗亦可減少。 裝置之尺寸及“據本發明之資料輸入裝置，資料輸入 尺寸及功率消耗可減小。 本申請幸冷w女H9 2005-26483號之主Γ韓國專利巾請㈣簡，882號及第 日申請於韓國專利^分別於咖6年9月29日及_年3月23 。）’該等專利申請案之全部内容以引用 112669.doc •16- l3〇7889 的方式併入本文中。 雖然已關於特定實施例描述了本發明，但熟習此項技術 者將瞭解，可在不偏離以下申請專利範圍所界定之本發明 之精神與範疇的情況下，做出各種改變及修改。 【圓式簡單說明】 圖1為展示一習知DDR2 SDRAM之方塊圖； 圖2為描述習知資料輸入裝置之方塊圖； # 圖3為描述圖2中所示之習知資料輸入裝置之操作的波形 圖； 圖4為根據本發明之較佳實施例之使用於半導體記憶裝 、 置中之資料輸入裝置的方塊圖； 圖5為展示圖4中所示之第一非同步延遲元件的示意性電 路圖； 圖6為圖4中所示之第一鎖存器之示意性電路圖；及 圖7為展示圖4中所示之資料輸入裝置之操作的波形圖。 • 【主要元件符號說明】 10, 100 第一緩衝器 20, 200 鎖存器單元 21,210 第一鎖存器 22, 220 第二鎖存器 23, 230 第三鎖存器 24, 260 第四鎖存器 25, 270 第五鎖存器 26 第六鎖存器 112669.doc 1307889 27 第七鎖存器 30, 300 延遲單元 32, 320 第三延遲元件 34, 340 第四延遲元件 36, 360 第六延遲元件 38, 380 第八延遲元件 40, 400 同步控制單元 42, 420 第二緩衝器 44, 440 訊號產生單元 46, 460 第一延遲元件 48, 480 第二延遲元件 212 差動放大器 214 驅動器 216 輸出單元 240 第一非同步延遲元件 250 第二非同步延遲元件 CPI, CP2, CN1, CN2 電容器 11, 12, 13, 14 反相器 SW1, SW2, SW3, SW4, SW5, SW6, SW7 切換器 112669.doc -18-In other words, the data should satisfy the set time and hold time of using one of the rising edges of a synchronous signal as a reference point. Therefore, the second latch 22G and the third latch are enabled by the first and second asynchronous delay elements 260 and 270! | 23G output data delay - predetermined delay time 'so the output data bit (AO, A1) can meet the set time and hold time of the second-start second synchronization signal DQSFP4D, and for this purpose, the fourth and fifth latches The devices 260 and 270 receive the data. Thus, in accordance with a preferred embodiment of the present invention, by using an asynchronous delay element to store data, it is possible to minimize the continuous shift operation of one of the rising edges and one falling edge. Therefore, power consumption can be reduced. : Outside 'Because the number of blocks using the sync signal is reduced by the use of the driver, the size of the drive can be used to generate the sync signal. Therefore, by use and power consumption can also be reduced. The size of the device and "according to the data input device of the present invention, the data input size and power consumption can be reduced. This application is fortunately cold female W9 2005-26483 main Korean patent towel please (4) Jane, 882 and the first application The Korean patents are respectively available on September 29, 2006 and March 23, 2013.) The entire contents of these patent applications are incorporated herein by reference to 112669.doc • 16-l3〇7889. The present invention has been described with respect to the specific embodiments, and those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the following claims. 1 is a block diagram showing a conventional DDR2 SDRAM; FIG. 2 is a block diagram showing a conventional data input device; FIG. 3 is a waveform diagram for describing the operation of the conventional data input device shown in FIG. 4 is a block diagram of a data input device for use in a semiconductor memory device in accordance with a preferred embodiment of the present invention; and FIG. 5 is a schematic circuit diagram showing the first asynchronous delay element shown in FIG. 6 is shown in Figure 4. A schematic circuit diagram of the first latch; and FIG. 7 is a waveform diagram showing the operation of the data input device shown in FIG. 4. • [Major component symbol description] 10, 100 First buffer 20, 200 latch Unit 21, 210 first latch 22, 220 second latch 23, 230 third latch 24, 260 fourth latch 25, 270 fifth latch 26 sixth latch 112669.doc 1307889 27 seventh latch 30, 300 delay unit 32, 320 third delay element 34, 340 fourth delay element 36, 360 sixth delay element 38, 380 eighth delay element 40, 400 synchronization control unit 42, 420 second Buffer 44, 440 signal generating unit 46, 460 first delay element 48, 480 second delay element 212 differential amplifier 214 driver 216 output unit 240 first asynchronous delay element 250 second asynchronous delay element CPI, CP2, CN1 , CN2 Capacitor 11, 12, 13, 14 Inverters SW1, SW2, SW3, SW4, SW5, SW6, SW7 Switcher 112669.doc -18-

Claims (1)

13 078 8S i2396〇號專利申請案 、 中文申請專利範圍替換本(9'7年8月） . 十、申請專利範圍： -種使用於半導體_置中之資料輸 -同步控制單元，其用於接收一：、包含: 通訊號，以便產生-同步訊號；及；貝料之資料選 -同步早兀’其用於將按逐個位 料儲存至複數個同步儲存元件及非：入之内部資 用於以同步於該同步訊號方式，同時輸出：：件中’且 料作為並列對準的資料。 X A儲存之資 2.如請求们之資料輸入裝置，其中該同 一鎖存器單元，其用於以一兩列並列匕= 料，該鎖存器單元具有依—第一或一第二同 之該錄個同步儲存元件及該複數個非同步儲存。元件:、及 位元=1:料Γ於使輸出自該鎖存器單…數個 從而於貝;' 之每一位元延遲每一預定延遲時間， ^ 之遲之貝枓作為該並列對準的資料。 3 ·如明求項2之資料輸入梦晋. — ㈣人裝置’其巾該非同步儲存元件係用 父又耦合的反相器予以組態。 :明求項3之資料輸人裝置’其中該同步儲存元件係用— 移位兀件或一正反器予以組態。 5·如^項4之資料輸人裝置，其中該鎖存器單元包括： 第金貞存器，其用於以同步於該第一同步訊號之一 邊緣方式儲存該内部資料； 第一鎖存斋，其用於以同步於該第二同步訊號之— 、緣方式儲存该第—鎖存器之資料及輸出該經儲存之資 112669-970804.doc l3〇788913 078 8S i2396 nickname patent application, Chinese application patent scope replacement (9'7 August). X. Patent application scope: - Data transmission-synchronization control unit for semiconductor _ centering, used for Receiving a:, including: a communication number for generating a -synchronization signal; and; selecting a material for the material of the bedding material - synchronizing as early as possible - it is used to store the plurality of synchronous storage elements on a bit by bit basis and non-input internal resources In order to synchronize with the synchronous signal mode, at the same time output:: and the material is used as the data aligned in parallel. XA storage resource 2. The data input device of the requester, wherein the same latch unit is used for juxtaposing the data in one or two columns, the latch unit having the first or the second The recording of the synchronous storage element and the plurality of asynchronous storage. Component: and bit = 1: the output is delayed from the latch by a number of times and thus each bit is delayed by each predetermined delay time, ^ is the late pair as the parallel pair Quasi-information. 3 · Enter the data of Ming 2 as input into the dream. — (4) Human device 'The towel's non-synchronous storage element is configured with the parent coupled inverter. : The data input device of the item 3 is in which the synchronous storage element is configured with a shifting element or a flip-flop. 5. The data input device of item 4, wherein the latch unit comprises: a gold buffer for storing the internal data in an edge manner synchronized with one of the first synchronization signals; Fast, which is used to store the data of the first latch in synchronization with the second synchronous signal, and output the stored capital 112669-970804.doc l3〇7889 第一輪出資料； 年月日修正替換頁! SXH----i 第二同步訊號之一 儲存之資料作為第 第二鎖存器，其用於以同步於該 % y式儲存該内部資料及輸出該經 二輪出資料； 弟—非同步儲存元件，其用於儲存輸出自該 αο 。之該第一輸出資料，並在使該經儲存之資料延遲一 預疋延遲時間之後輸出該經儲存之資料； • :第二非同步儲存元件，其用於儲存輪出自該第三鎖 =之》亥第二輸出資料，並在使該經儲存之資料延遲一 預定延遲時間之後輸出該經儲存之資料； 、一第四鎖存器，其用於以同步於該第二同步訊號之一 邊緣方式儲存該第—非同步儲存元件之:#料及輸出該經 儲存之資料作為第三輸出資料；及 第五鎖存益，其用於以同步於該第二同步訊號之一 邊緣方；切存該第：非同步儲存元件之資料及輸出該經 鲁儲存之資料作為第四輸出資料。 6.如請求項5之資料輸入裝置，其中該同步控制單元包括： 、：緩衝器，其用以回應於一驅動訊號，接收該資料選 通訊號及一反相資料選通訊號； ―-訊號產生單元，其用於產生分別同步於該緩衝器之 :輸出訊號之-上升緣及-下降緣之第―及第二預同少 ^ ^ 了只/口J 遲一預定延遲時間而產生該第一同步訊號；及 112669-970804.doc 1307889 _ J 一第二延遲元件，其用於藉由使該第二預同步訊號延 遲一預定延遲時間而產生該第二同步訊號。 7. —種使用於半導體記憶裝置中之資料輸入裝置，其包含： 一同步控制單元’其用於回應於一驅動訊號而接收— 同步於一資料之資料選通訊號，以便產生一同步訊號；及 一同步單元’其用於將按逐個位元循序輸入之内部資 料儲存至複數個同步延遲元件及非同步延遲元件中，且 用於以同步於該同步訊號方式同時輸出該經儲存之資料 作為並列對準的資料。 8·如請求項7之資料輸入裝置，其中該同步單元包括： 鎖存器單元m以—兩列並狀形式儲存該資 料，該鎖存器單元具有依一第一或一第二同步訊號操作 之該複數個同步延遲元件及該複數個非同步延遲元件；及 一延遲單元，其綠使輸出自該鎖存器單元之複數個 位凡的輸出資料中之每-位元延遲每—預定延遲時間， 從而輸出該經延遲之資料作為該並列對準的資料。 9·如請求項8之資料 ㈤ 具宁。亥非同步延遲元件係用 电合盗及一反相器予以體現。 10.如請求項9之資料輸入裝置， 冋步延遲元件係用一 移位TL件或一正反器予以體現。 Π.如請求項i 〇之資料輪裝 貝斜輸入忒置’其中該鎖存器單元包括. 第—鎖存器，其用於以同步於 邊绦7於°亥弟—同步訊號之一 遭緣方式儲存該内部資料； 第二鎖存器，其用於以同步於 …亥弟一同步訊號之一 112669-970804.doc ，/889 、、方式儲存該第一鎖^ 資料作為u h 貝枓及輸出該經儲存之 第一輪出資料； 邊緣方式儲：：其用於以同步於該第二同步訊號之-第二輸出資：：部資料及輸出該經儲存之資料作為一 c步儲存元件’其用於儲存輪出自該第二鎖The first round of data; the year and month to correct the replacement page! SXH----i one of the second synchronization signals stored as the second latch, which is used to store the internal data in synchronization with the % y And outputting the second round of output data; the younger-non-synchronous storage element for storing output from the αο. The first output data, and outputting the stored data after delaying the stored data by a predetermined delay time; • a second asynchronous storage element for storing the wheel from the third lock= a second output data, and outputting the stored data after delaying the stored data for a predetermined delay time; a fourth latch for synchronizing to one of the edges of the second synchronization signal And storing the stored data of the first asynchronous storage component as a third output data; and a fifth latching benefit for synchronizing to one edge of the second synchronous signal; The data of the non-synchronous storage component and the output of the data stored as the fourth output data. 6. The data input device of claim 5, wherein the synchronization control unit comprises: a buffer for responding to a driving signal, receiving the data selection communication number and an inverted data selection communication number; ―-signal a generating unit for generating synchronization with the buffer: an output signal - a rising edge and a falling edge - and a second pre-synchronization ^ ^ only / port J is delayed by a predetermined delay time to generate the first a synchronization signal; and 112669-970804.doc 1307889 _J a second delay element for generating the second synchronization signal by delaying the second pre-synchronization signal by a predetermined delay time. 7. A data input device for use in a semiconductor memory device, comprising: a synchronization control unit for receiving in response to a driving signal - synchronizing with a data selection communication number of a data to generate a synchronization signal; And a synchronization unit for storing internal data sequentially input bit by bit to a plurality of synchronous delay elements and asynchronous delay elements, and for simultaneously outputting the stored data in synchronization with the synchronous signal Parallel alignment of the information. 8. The data input device of claim 7, wherein the synchronization unit comprises: the latch unit m stores the data in a two-column form, the latch unit having a first or a second synchronization signal The plurality of synchronous delay elements and the plurality of asynchronous delay elements; and a delay unit, the green of which delays each-bit delay of each of the plurality of bits of the output data of the latch unit Time, thereby outputting the delayed data as the data of the parallel alignment. 9. According to the information in item 8 (5) with Ning. The non-synchronous delay element is embodied by an electric thief and an inverter. 10. The data input device of claim 9, wherein the step delay element is embodied by a shift TL or a flip flop.如.If the request item i 〇 轮 轮 斜 斜 斜 ' 其中 其中 其中 其中 其中 其中 其中 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存 锁存The edge mode stores the internal data; the second latch is configured to store the first lock data as a uh shellfish and the like in synchronization with one of the sync signals 112669-970804.doc, /889 Outputting the stored first round of data; edge mode storage:: for synchronizing with the second synchronization signal - the second output resource:: part data and outputting the stored data as a c step storage element 'It is used to store the wheel from the second lock 預定征：t輸出貝料’並在使該經儲存之資料延遲〆 、蚪間之後輪出該經儲存之資料； :第二非同步儲存元件，其用於儲存輸出自該第三鎖 :之该第二輸出資料’並在使該經儲存之資料延遲〆 疋L遲時間之後輸出該經儲存之資料； 第四鎖存^ ’其用於以同步於該第二同步訊號之〆 广緣方式儲存該第—非同步儲存元件之—資料及輸出該 經館存之資料作為一第三輸出資料；及Predetermined sign: t output bedding 'and rotates the stored data after delaying the stored data, and the second non-synchronized storage element for storing output from the third lock: The second output data 'and outputting the stored data after delaying the stored data 〆疋L; the fourth latch ^' is used to synchronize with the second synchronization signal Storing the data of the first asynchronous storage component and outputting the data stored in the library as a third output data; 第五鎖存态，其用於以同步於該第二同步訊號之一 邊緣方式儲存该第二非同步儲存元件之一資料及輸出該 經儲存之資料作為一第四輸出資料。 2·如明求項11之資料輸入裝置，其中該非同步延遲元件包 括： —第一反相器，其用於使經由一輸入節點輸入之一輸 入訊號反相； 第一電容器’其係用一 P型金屬氧化物半導體（PM〇s) 電晶體予以體現； 一第一切換器’其用於將該第一電容器連接至該第一 112669-970804.docAnd a fifth latched state, configured to store one of the second asynchronous storage elements and output the stored data as a fourth output data in an edge manner synchronized with one of the second synchronization signals. 2. The data input device of claim 11, wherein the asynchronous delay element comprises: - a first inverter for inverting an input signal via an input of an input node; the first capacitor 'using a A P-type metal oxide semiconductor (PM〇s) transistor is embodied; a first switcher 'which is used to connect the first capacitor to the first 112669-970804.doc 1307889 反相器之一輸出節點； 一第二電容器，其係用一η型金屬氧化物半導體（NMOS) 電晶體予以體現； 一第二切換器，其用於將該第二電容器連接至該第一 反相器之該輸出節點； 一第二反相器，其用於使該第一反相器之一輸出反相； 一第三切換器，其用於將該輸入節點連接至該第二反 相器之一輸出節點； 一第三反相器，其用於使該第二反相器之一輸出反相； 一第三電容器，其係用一 PMOS電晶體予以體現； 一第四切換器，其用於將該第三電容器連接至該第三 反相器之一輸出節點； 一第四電容器，其係用一 NMOS電晶體予以體現； 一第五切換器，其用於將該第四電容器連接至該第三 反相器之該輸出節點； 一第四反相器，其用於使該第三反相器之一輸出反相； 一第六反相器，其用於將該第四反相器之一輸出節點 連接至一輸出節點，以用於輸出一輸出訊號；及 一第七切換器，其用於將該輸入節點連接至該輸出節 13.如請求項12之資料輸入裝置，其中該同步控制單元包括： 一緩衝器，其用以回應於該驅動訊號，接收該資料選 通訊號及一反相資料選通訊號； 一訊號產生單元，其用於產生與該緩衝器之一輸出訊 112669-970804.doc 1307889 — 一 年月日修正\ , 口 97. h A_____—— ^ 唬之—上升緣及一下降緣分別同步之一第一及—第二預 同步訊號； 一第一延遲元件，其用於藉由使該第一預同步訊號延 遲一預定延遲時間而產生該第一同步訊號；及 第二延遲元件，其用於藉由使該第二預同步訊號延 遲一預定延遲時間而產生該第二同步訊號。 14.如凊求項13之資料輸入裝置，其中該延遲單元包括一第 一至一第六延遲元件，用於將一預定延遲時間加至該第 一至該第四輸出資料。 1 5.如凊求項14之資料輸入裝置，其中每個該第—至第五 存器包括： 一差動放大器，其用於在該同步訊號啟動時 入訊號作為一差動輸入； ^ 驅動器，其用於驅動該差動放大器之一輸出訊號；及 輸出單元，其用於儲存並輸出該驅動器之—輸出訊 • 號。 16·如請求項7之資料輸入裝£，其進一步包含一緩衝器，該 緩衝器用以回應於該驅動訊號，接收該資料及輸出該接 收到的資料作為該内部資料。 17. —種半導體記憶裝置，其包含： -内邛=貝料選通訊號產生器，其用以回應於—資料選 通訊號而產生一内部資料選通訊號； 第資料對準單元，其用以回應於該内部資料選通 訊號而將循序輸入之資料的-部分對準為-第-並列資 112669-970804.doc 1307889 « - 料； 年月日修正替换頁 97. ..ft ., Λ__________________ 一延遲單元，其用於使該第一並列資料延遲一預定時 間以輸出一經延遲之資料；及 一第二資料對準單元，其用以回應於該内部資料選通 訊號而將該經延遲之資料對準為一第二並列資料。1307889 an output node of an inverter; a second capacitor embodied by an n-type metal oxide semiconductor (NMOS) transistor; a second switch for connecting the second capacitor to the first An output node of an inverter; a second inverter for inverting an output of one of the first inverters; a third switch for connecting the input node to the second One of the output nodes of the inverter; a third inverter for inverting the output of one of the second inverters; a third capacitor, which is embodied by a PMOS transistor; a third capacitor connected to an output node of the third inverter; a fourth capacitor, which is embodied by an NMOS transistor; a fifth switch for the first a fourth capacitor coupled to the output node of the third inverter; a fourth inverter for inverting an output of one of the third inverters; a sixth inverter for One of the fourth inverters is connected to an output node for output An output signal; and a seventh switch for connecting the input node to the output section 13. The data input device of claim 12, wherein the synchronization control unit comprises: a buffer for responding to The driving signal receives the data selection communication number and an inverted data selection communication number; a signal generation unit is configured to generate an output signal 112669-970804.doc 1307889 with one of the buffers. Port 97. h A_____——^ 唬—the rising edge and the falling edge respectively synchronizing one of the first and second pre-synchronization signals; a first delay element for delaying the first pre-synchronization signal Generating the first synchronization signal with a predetermined delay time; and a second delay element for generating the second synchronization signal by delaying the second pre-synchronization signal by a predetermined delay time. 14. The data input device of claim 13, wherein the delay unit comprises a first to a sixth delay element for adding a predetermined delay time to the first to fourth output data. 1 5. The data input device of claim 14, wherein each of the first to fifth registers comprises: a differential amplifier for inputting a signal as a differential input when the synchronization signal is activated; And for outputting one of the differential amplifier output signals; and an output unit for storing and outputting the output signal of the driver. 16. The data input of claim 7 further comprising a buffer responsive to the drive signal, receiving the data and outputting the received data as the internal data. 17. A semiconductor memory device, comprising: - an internal 邛 = shell selection communication number generator for generating an internal data selection communication number in response to a data selection communication number; a data alignment unit for use In response to the internal data selection communication number, the - part of the data entered in the order is aligned to - the first and the capital 112669-970804.doc 1307889 « - material; year, month and day correction replacement page 97. .. ft ., Λ__________________ a delay unit for delaying the first parallel data for a predetermined time to output a delayed data; and a second data aligning unit for delaying the response to the internal data selection communication number The data is aligned to a second side-by-side data. 112669-970804.doc112669-970804.doc
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