TWI305929B - Low dark current image sensors with epitaxial sic and/or carbonated channels for array transistors - Google Patents

Low dark current image sensors with epitaxial sic and/or carbonated channels for array transistors Download PDF

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TWI305929B
TWI305929B TW094127945A TW94127945A TWI305929B TW I305929 B TWI305929 B TW I305929B TW 094127945 A TW094127945 A TW 094127945A TW 94127945 A TW94127945 A TW 94127945A TW I305929 B TWI305929 B TW I305929B
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pixel unit
isolation layer
conductive isolation
region
substrate
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TW200629348A (en
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Chandra Mouli
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Micron Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14654—Blooming suppression

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  • Computer Hardware Design (AREA)
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Description

1305929 九、發明說明： 【發明所屬之技術領域】 本發明大體係關於半導體裝置，且更特定言之係關於用 於半導體裝置之光電二極體電晶體隔離技術，包括CMOS 影像感測器。 【先前技術】 CMOS影像感測器曰益用作低成本成像裝置。一 CMOS影 像感測器電路包括像素單元之聚焦平面陣列，每個單元包 括一個光閘（photogate)、光電導體元件或在一基板内具有 一相關電荷積聚區域以聚集光產生之電荷的光電二極體。 每一像素單元可包括用於自電荷積聚區域向一感測節點轉 移電荷之電晶體及用於重設該感測節點至電荷轉移前一預 定電荷水平之一電晶體。像素單元亦可包括用於接收並放 大來自感測節點之電荷的源極隨耦器電晶體及用於控制來 自該源極隨耦器電晶體之單元内容之讀出的存取電晶體。 在CMOS影像感測器中，像素單元之主動性元件執行以下 必需功能：（1)光至電荷的轉換；（2)聚集影像電荷；（3)電荷 轉移至感測節點，伴隨著電荷放大；（4)重設感測節點至電 荷轉移至其以前之已知狀態；（5)選擇用於讀出之像素；及 (6)輸出並放大代表來自該感測節點之像素電荷的訊號。 通常已知上述類型之CMOS影像感測器，如（例如）Nixon #Ai"256x256 CMOSActivePixelSensorCamera-on-a-Chip”，IEEE Journal of Solid-State Circuits，第 31(12)卷， 第 2046-2050 頁（1996);及 Mendis 等人之"CMOS Active Pixel 104142-961225.doc 13059291305929 IX. Description of the Invention: Field of the Invention The present invention relates to semiconductor devices, and more particularly to photodiode transistor isolation techniques for semiconductor devices, including CMOS image sensors. [Prior Art] A CMOS image sensor is advantageously used as a low-cost imaging device. A CMOS image sensor circuit includes a focus plane array of pixel units, each unit including a photogate, a photoconductor element, or a photodiode having an associated charge accumulation region in a substrate to concentrate the charge generated by the light. body. Each of the pixel units may include a transistor for transferring charge from a charge accumulation region to a sensing node and a transistor for resetting the sensing node to a predetermined charge level before charge transfer. The pixel unit can also include a source follower transistor for receiving and amplifying charge from the sense node and an access transistor for controlling readout of the cell contents from the source follower transistor. In a CMOS image sensor, the active elements of the pixel unit perform the following necessary functions: (1) light-to-charge conversion; (2) image charge accumulation; (3) charge transfer to the sensing node, accompanied by charge amplification; (4) resetting the sense node to charge transfer to its previously known state; (5) selecting a pixel for reading; and (6) outputting and amplifying a signal representative of pixel charge from the sense node. CMOS image sensors of the above type are generally known, such as, for example, Nixon #Ai"256x256 CMOS ActivePixelSensorCamera-on-a-Chip", IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al."CMOS Active Pixel 104142-961225.doc 1305929

Image Sensors"，IEEE Transactions on Electron Devices，第 41(3)卷’第452-453頁（1994)中所討論。亦參見第6,i77,333 及6,204,524號美國專利，其描述習知CMOS影像感測器之 運作且讓渡於Micron Technology，lnc.，該等專利之内容以 引用的方式併入本文中。 圖1展示習知CMOS像素單元1〇之示意圖。所說明CM〇s 像素單元10為四個電晶體（4T)單元。CM0S像素單元1〇通常 包含用於產生並收集由光入射於像素單元1〇上而產生之電 荷的光轉換裝置23及用於自光轉換裝置23轉移光電荷至一 感測節點（通常為浮動擴散區（fl〇ating diffusj〇n regi〇n)5)之 一轉移電晶體17。浮動擴散區5電連接至一輸出源極隨耦器 電晶體19之閘極。像素單元1〇亦包括用於重設浮動擴散區5 至一預定電壓之一重設電晶體16及用於響應一位址訊號將 來自源極隨耦器電晶體19之訊號輸出至一輸出端子的一列 選擇電晶體1 8。 圖2為圖1之像素單元1〇之一部分之橫截面圖，展示光轉 換裝置23、轉移電晶體17及重設電晶體16。例示性CM〇s 像素單元ίο具有可形成為固定光電二極體（pinned photodiode)之光轉換裝置23。光電二極體23具有p_n_p構 造，其在p型活性層U内包含—p型表層22&n型光電二極體 區21。光電二極體23連接至轉移電晶體17並部分在轉移電 晶體17下面。重設電晶體16在轉移電晶體17之與光電二極 體23相對一側上。如圖2所示，重設電晶體16包括一源極/ 没極區2。浮動擴散區5在轉移電晶體17與重設電晶體16之 間。 104142-961225.doc 1305929 在圖1及2中描述之CMOS像素單元10中，電子由入射於光 轉換裝置23上之光產生且儲存於n型光電二極體區21中。當 轉移電晶體17被啟動時此等電荷被轉移電晶體17轉移至浮 動擴散區5。源極隨耗器電晶體19自轉移電荷產生一輸出訊 號。最大輸出訊號與自η型光電二極體區21提取之電子數目 成比例。 按照慣例，鄰近電荷收集區21之淺渠溝隔離（STI)區3係用 於將像素單元10與其它像素單元及影像感測器裝置隔離。 STI區3係通常使用習知STI製程形成。STI區3通常以氧化物 襯料38裝襯且以介電材料37填充。同樣，STI區3亦可包括 氮化物襯料39。該氮化物襯料39提供幾個好處，包括改良 STI區3之拐角處之拐角之園整性、減少鄰近STI區3之應力 及減少轉移電晶體17之、;^漏。 與像素單元關聯之一普遍問題為暗電流-即使像素上沒 有光也會發生像素單元電容之放電。暗電流可由多個不同 因素引起，包括：光電二極體接合洩漏、沿隔離邊緣之洩 漏、電晶體亞臨限值洩漏、汲極引發之障壁下洩漏（drain induced barrier lower leakage)、閘極引發之汲極洩漏（gate induced drain leakage)、陷阱輔助穿隧及其它像素缺陷。該 工業中之明顯傾向為按比例減小電晶體在閘極長度及閘極 寬度方面之尺寸（如”按比例縮放"）。隨著裝置逐漸按比例減 小，暗電流效應通常增加。 因此，需要具有改良之隔離結構以減小暗電流及固定圖 案雜訊（fixed pattern noise)。 104142-961225.doc 1305929 【發明内容】 本發明提供一種像素單元，其具有含在本發明之例示性 實施例中提供之高碳濃度Sic之導電隔離層的基板。在該像 素單兀之基板中以層上方提供包含SiC或碳化矽之通道以 減少暗電流洩漏。 【實施方式】 在以下詳細描述中，參考附隨圖示，此等附隨圖示形成 本文-部分且說明本發明可實施於其中之特定實施例。在 該等圖*巾，類似參考數字在數個視圖中大體上描述相似 組件。足夠詳細地描述此等實施例以使熟習此項技術者能 夠實施本發明，且應瞭解可利用其它實施例且可進行結 構邏輯及電氣修改而不偏離本發明之精神及範嘴。 術語"晶圓"及"基板"應理觫為包括矽、絕緣物上矽 (SOI)、藍寶石上邦〇s)及純邦⑽)技術、摻雜及未推雜 半導體纟纟底半導體基礎支撐之矽磊晶層以及其它半 導體結構。此外，當在下列描述中參考"晶圓"及"基板"時， 可利用先前製程步驟以在基底半導體結構或基礎中形成區 域或接面。此外，該半導體不需要基於石夕，但可基於石夕_鍺、 鍺或砷化鎵。 術語"像素"或"像素單元，，指圖像元件單元，其含有光轉換 裝置及用於將電磁輻射轉換為電訊號之電晶體。為說明之 目的’在本文圖式及描述中說明了一部分代表性像素單 P且通常影像感測器中所有像素單元之製造會同時且以 相似方式進行。 104142-961225.doc 1305929 圖3為根據本發明之例示性實施例之像素單元300之橫截 面圖。像素單元300類似圖1及2中描述之像素單元10，此外 像素單元3 00包括在矽層311上方之一導電隔離層301。導電 隔離層301較佳由SiC或槽形碳化矽構成。使用富碳之材料 層增加了該裝置之帶隙。導電隔離層301具有比Si高之帶 隙，通常比Si低十六（16)個數量級，且所得像素單元300具 有低本質載體濃度。因此，導電隔離層301降低了暗電流水 平。Image Sensors ", IEEE Transactions on Electron Devices, Vol. 41 (3) pp. 452-453 (1994). See also U.S. Patent Nos. 6, i. FIG. 1 shows a schematic diagram of a conventional CMOS pixel unit. The illustrated CM〇s pixel unit 10 is a four transistor (4T) unit. The CMOS pixel unit 1A generally includes a light converting device 23 for generating and collecting charges generated by light incident on the pixel unit 1 and for transferring light charges from the light converting device 23 to a sensing node (usually floating) One of the diffusion regions (fl〇ating diffusj〇n regi〇n) 5) transfers the transistor 17. The floating diffusion region 5 is electrically coupled to the gate of an output source follower transistor 19. The pixel unit 1A further includes a resetting transistor 16 for resetting the floating diffusion region 5 to a predetermined voltage and for outputting the signal from the source follower transistor 19 to an output terminal in response to the address signal. A column selects the transistor 18. 2 is a cross-sectional view of a portion of the pixel unit 1 of FIG. 1 showing the light converting device 23, the transfer transistor 17, and the reset transistor 16. The exemplary CM〇s pixel unit ίο has a light conversion device 23 that can be formed as a pinned photodiode. The photodiode 23 has a p_n_p structure including a p-type surface layer 22 & n-type photodiode region 21 in the p-type active layer U. The photodiode 23 is connected to the transfer transistor 17 and partially under the transfer transistor 17. The resetting transistor 16 is on the side of the transfer transistor 17 opposite to the photodiode 23. As shown in FIG. 2, the reset transistor 16 includes a source/no-pole region 2. The floating diffusion region 5 is between the transfer transistor 17 and the reset transistor 16. 104142-961225.doc 1305929 In the CMOS pixel unit 10 described in Figs. 1 and 2, electrons are generated by light incident on the light converting device 23 and stored in the n-type photodiode region 21. These charges are transferred to the floating diffusion region 5 by the transfer transistor 17 when the transfer transistor 17 is activated. The source follower transistor 19 produces an output signal from the transferred charge. The maximum output signal is proportional to the number of electrons extracted from the n-type photodiode region 21. Conventionally, the shallow trench isolation (STI) region 3 adjacent to the charge collection region 21 is used to isolate the pixel unit 10 from other pixel units and image sensor devices. The STI Zone 3 series is typically formed using conventional STI processes. The STI region 3 is typically lined with an oxide liner 38 and filled with a dielectric material 37. Similarly, the STI region 3 may also include a nitride liner 39. The nitride liner 39 provides several benefits, including improved roundness of the corners at the corners of the STI region 3, reduced stress in the adjacent STI regions 3, and reduced transfer transistor 17; One common problem associated with pixel cells is the dark current - even if there is no light on the pixel, the discharge of the pixel cell capacitance occurs. Dark current can be caused by a number of different factors, including: photodiode junction leakage, leakage along the isolation edge, transistor sub-limit leakage, drain induced barrier lower leakage, gate induced Gate induced drain leakage, trap assisted tunneling, and other pixel defects. A clear tendency in the industry is to scale down the size of the transistor in terms of gate length and gate width (eg, "scaled"). As the device is gradually scaled down, the dark current effect typically increases. There is a need for an improved isolation structure to reduce dark current and fixed pattern noise. 104142-961225.doc 1305929 SUMMARY OF THE INVENTION The present invention provides a pixel unit having exemplary implementations included in the present invention The substrate of the conductive isolation layer of the high carbon concentration Sic is provided in the example. The channel containing SiC or tantalum carbide is provided above the layer in the substrate of the pixel unit to reduce dark current leakage. [Embodiment] In the following detailed description, The accompanying drawings, which are incorporated in the drawings, are in the The embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is understood that other embodiments may be utilized And electrical modifications without departing from the spirit and scope of the present invention. The terms "wafer" and "substrate" should be considered to include 矽, SOI, sapphire and sapphire Pure state (10)) technology, doped and undoped semiconductor bottom-layer semiconductor support for epitaxial layers and other semiconductor structures. In addition, when referring to "wafer" and "substrate" Previous process steps may be utilized to form regions or junctions in the base semiconductor structure or foundation. Furthermore, the semiconductor need not be based on Shi Xi, but may be based on Shi Xi 锗, 锗 or gallium arsenide. The term "pixel " Or "pixel unit," an image element unit containing a light converting device and a transistor for converting electromagnetic radiation into an electrical signal. For illustrative purposes, a portion of representative pixels are illustrated in the figures and description herein. The fabrication of all pixel cells in a single P and typically image sensor will occur simultaneously and in a similar manner. 104142-961225.doc 1305929 FIG. 3 is a cross section of a pixel unit 300 in accordance with an exemplary embodiment of the present invention. The pixel unit 300 is similar to the pixel unit 10 described in FIGS. 1 and 2. Further, the pixel unit 300 includes a conductive isolation layer 301 over the germanium layer 311. The conductive isolation layer 301 is preferably composed of SiC or trench tantalum carbide. The use of a carbon-rich material layer increases the band gap of the device. The conductive isolation layer 301 has a higher band gap than Si, typically sixteen (16) orders of magnitude lower than Si, and the resulting pixel unit 300 has a low intrinsic carrier concentration. The conductive isolation layer 301 reduces the dark current level.

直至最近，生長高品質SiC係非常昂貴的，且因而SiC僅 用於選擇性應用。磊晶成長SiC之最近的技術進步使其較不 昂貴且減少了缺陷密度。此等進步使在習知應用中使用SiC 基板更加可能。由於可在習知Si層上建立或生長SiC通道並 作為習知Si製程之部分，故其可倂入亦形成CMOS光電二極 體之製程中。最近在形成SiC層之技術進步可發現於（例 ^〇)"A new Si:C epitaxial channel nMosfet Architecture with improved drivability and short-channel characteristics" » T. Ernest等人，2003 Symposium on VLSI Technology Digest of Technical Papers，第 92-93 頁；"Fabrication of a novel strained SiGeiC-channel planar 55nm nMosfet for High Performance CMOS"，T. Ernest等人，2002 Symposium on VLSI Technology Digest of Technical Papers » 第 92-93 頁； 及"Selective growth of high-quality 3C-SiC using a Si02 sacrificial layer technique"，Thin Solid Films.第 345(2)卷 (1999)，第 19-99頁中。 104142-961225.doc 1305929 在像素單元中使用Sic或碳化石夕通道作為導電隔離層降 氐日電流水平。因為降低了暗電流水平，本發明允許像素 單元陣列上之更大縮放比例。更大縮放比例使更大填充因 數可行。 ' 在像素單元中使用Sic或碳化石夕通道作為導電隔離層由 於該等物質之本質特性而亦產生額外優勢。具體言之，碳 化矽材料允許高溫運作且使像素單元能夠耐受高電場。此 外’此等物質亦具有有效散熱之特性。 圖4A-4J描述根據本發明之例示性實施例之像素單元3〇〇 之形成。本文描述之步驟除了彼等邏輯上需要先前動作之 結果的步驟之外不必以任何特定順序執行。因此，雖然描 述以下步驟以通用順序執行，但該順序僅為例示性且若需 要可改變。 如圖4A所說明，一襯墊氧化物層441(其可為熱生長氧化 物）形成於基板311上。一犧牲層442形成於襯墊氧化物層 441上。犧牲層442可為氮化物或介電抗反射塗覆 層。 圖4B描述一渠溝430在基板311中形成且穿過基板311上 之層44卜442。可由任何已知技術形成渠溝43〇。舉例而言， 圖案化光阻層（未圖示）用作触刻製程之一光罩。利用乾式 電漿條件及二氟甲烷/四氟化碳化學物質實施 第一蝕刻。此蝕刻有效蝕刻氮化矽層442及襯墊氧化物層 441以形成一穿過其中之開口，該開口到達基板3ιι時停 止。實施第一蝕刻以將該等開口延伸入基板3丨丨。該第二蝕 104142-961225.doc -10- 1305929 剡為利用二氟甲烷/溴化氫（CHJVHBr)化學物質之乾式電 聚钮刻。該#刻之時序以在基板311内形成渠溝咖至 所需深度。較短蝕刻時間產生較淺渠溝43〇。使用標準光阻 剝離技術（較佳藉由電漿蝕刻）移除光阻光罩（未圖示）。 如圖4C所示，薄絕緣層338(在約5〇 a與約25〇 a厚度之間） 形成於渠溝430側壁336a、336b及底部3〇8上。在圖4c中所 描述之實施例中，絕緣層338為一氧化物層338，其較佳藉 由熱氧化而生長。 渠溝430可以障壁薄膜339裝襯。在圖4(：中展示之實施例 中障壁/專膜339為氮化物概料’例如氮化妙。氮化物襯料 339係藉由任何適當技術形成至5〇 a至約250 A範圍内之厚 度。如在該技術中所已知，氮化矽襯料339可藉由沉積氨 (NH3)及矽烷（SiH4)而形成。 如圖4C所示，以介電材料337填充渠溝430。介電材料337 可為氧化物材料’例如梦氧化物，諸如Si〇或二氧化碎 (Si〇2);氧氮化物；氮化物材料，諸如氮化^夕；碳化梦；高 溫聚合物；或其它適當之介電材料。在所說明之實施例中， 介電材料337為高密度電漿（HDP)氧化物。 如圖4E所示，實施化學機械研磨（CMP)步驟以移除渠溝 430以及氮化物層442之外、基板311之表面上的氮化物層 339。同樣（例如）使用場濕緩衝氧化物姓刻（field wet buffered-oxide etch)步驟及清理步驟來移除襯墊氧化物層 441 ° 圖4F描述導電隔離層301之形成。磊晶導電隔離層3〇1較 104142-961225.doc 11 1305929 佳由習知方式生長(如之前Ernst概述之方法)。在一較佳實 ^ ，中該磊曰曰通道在低溫時生長。在一較佳實施例中導 電隔離層3〇 i較佳為Sic或碳化通道碎（㈤。讀d η— ^山叫。導電隔離層3()1不需要均勻生長；因而場區域（如 木溝430)上之導電隔離層3〇1之深度可較非場區域上之導 電隔離層之深度小。 在一較佳實施例中，調節導電隔離層301中之碳濃度。已 头控制Sl.C生長之溫度影響導電隔離層301之碳濃度。 、在本發明之一個實施例中，導電隔離層僅位於電晶體區 域。^本發明之另一實施例中，導電隔離層生長在基板之 另一區域上，如光電二極體區域。在另一實施例中，導電 隔離層生長在吾人期望單元之外圍陣列上。在另—實施例 中，導電隔離層生長在數個區域上，意即前述提及位置之 組合，例如下述圖5及6中所示。儘管未展示，但一氮化物 層在導電隔離層形成前形成。對氮化物沉積進行圖案化以 視本發明之態樣對導電隔離層3〇1之形成曝露特定區域。 在導電隔離層301上進行平坦化，產生如圖4(}中所見相對 均勻高度之層。該層高度可介於100 A至500 A範圍内，其 中典型高度為約250A。在本發明之一個實施例中，在非場 區域上方導電隔離層301之高度為約25〇 A，且在場區域上 方導電隔離層301之高度為小於約250 A。 在平坦化步驟之後’在導電隔離層301形成前沉積之氮化 物層藉由化學機械研磨（CMP)步驟移除。該氮化物可視本發 明之實施例而選擇性移除。舉例而言，在一特定實施例中， 104142-961225.doc -12- 1305929 可不需要移除沿單元外圍之氮化物層。 圖4H描述轉移電晶體317(圖3)閘極堆疊407及重設電晶 體316(圖3)閘極堆疊406之形成。雖未展示，但源極隨耦器 電晶體及列選擇電晶體19、18(圖1)可分別如下描述同時與 轉移電晶體及重設電晶體317、3 16一起形成。 為形成圖4H中所示之電晶體閘極堆疊4〇7、4〇6，使（例如） 氧化矽之一第一絕緣層4〇 ia生長或沉積於基板311上。在一 較佳實施例中，閘極氧化係藉由快速熱氧化（"RT〇")或臨場 蒸氣產生（ISSG)而形成。第一絕緣層4〇la用作隨後形成之 電晶體閘極401b之閘極氧化物層。接著使一導電材料層 4〇lb沉積於氧化物層4〇13上。導電層4〇比用作電晶體317、 316(圖3)之閘電極。導電層4〇lb可為一多晶矽層，可將其摻 雜為第二導電型，如11型。使一第二絕緣層4〇lc沉積於導電 層4011»上。第二絕緣層4〇1(;可由（例如）氧化物（8丨〇2)、氮化 物（氮化矽）、氮氧化物（氮氧化矽）、〇N(氮化氧）、N〇(氧化 氮）或ΟΝΟ(氧·氮·氧）形成。 閘極堆疊層401a、401b、401c可藉由習知沉積方法形成， 諸如化學氣相沉積（CVD)或電漿增強化學氣相沉積 (PECVD)。然後將層4〇1&、4〇lb、4〇1〇圖案化並蝕刻以形 成圖4F中所示之多層閘極堆疊407、406。 本發明不限於上述閘極堆疊407、406之結構。根據需要 及此項技術中已知之技術，可添加額外層或者可改變閘極 堆疊407、406。舉例而言，可在閘電極4〇lb與第二絕緣層 401c之間形成矽化物層（未圖示）。該矽化物層可包括於閘極 104142-961225.doc •13· 1305929 堆疊407、406中或者影像感測器電路中之所有電晶體閘極 堆疊結構中，且其可為矽化鈦、矽化鎢、矽化鈷、矽化鉬 或矽化鈕。此額外導電層亦可為障壁層/折射金屬，諸如氮 化鈦/鎢（TiN/W)或氮化鎢/鎢（WNx/w)，或者其可完全由氮 化鎢（WNX)形成。 如圖41所示將摻雜之p型阱334、335植入基板311内。第 一 P型阱334形成於基板31〗中包圍隔離區333並在隔離區 333以下延伸。第二p型阱335形成於基板311中自轉移閘極 堆疊407下之一點在基板311中遠離待形成光電二極體 323(圖3)之處之方向上延伸。 藉由已知方法形成p阱334、335。舉例而言，可在具有待 形成P拼334、335之區域上之開口的基板311上將一光阻材 料層（未圖示）圖案化。可將？型摻雜物（諸如硼）穿過光阻材 料中之開口植入基板311中。形成p% 334、335具有高於基 板311之鄰近部分之p型摻雜物濃度。或者，可在形成渠溝 430之前形成p阱334、335。 如圖4J所示，將摻雜之n型區321植入基板3ιι中（對於圖3 之光電一極體323)。舉例而言，可在待形成光電二極體 阳（圖3)之基板311表面上具有一開口之基板3ιι上將一光 阻材料層（未圖示）圖帛化。可將n型播雜物（諸如鱗、坤或錄） 穿過該開口植入基板311中。多種植入物可用來調整區域 之輪廓。若需要’可實施成角度之植入 卿Nation)以形成摻雜區321，藉此以相對基板3ιι之表面 除90度之外之其它角進行植入。 104142-961225.doc -14 - 1305929 如圖4J所示，n型區321自鄰近轉移閘極堆疊4〇7之點形成 並在基板3 11中延伸於閘極堆疊407與隔離區333之間。區域 321形成一用於收集光產生之電荷之感光電荷積聚區域。 藉由已知方法植入浮動擴散區305及源極/汲極區3〇2以 達成圖4J中所示結構。浮動擴散區3〇5及源極/汲極區3〇2形 成為η型區域。可使用任何適當之摻雜物（諸如磷、砷或 銻）。浮動擴散區305形成於轉移閘極堆疊4〇7與11型光電二 極體區域321相對之一側上。源極/汲極區3〇2形成於重設閘 極堆疊406之與浮動擴散區305相對之一側上。 圖4K描述一介電層307之形成。如圖所示，層3〇7為一氧 化物層，但層307可為藉由該技術中已知方法形成之任何適 當介電材料，諸如二氧化矽、氮化矽、氮氧化物或正矽酸 四乙酯（TEOS)。 如圖4L所示，植入光電二極體323之摻雜表層322。將摻 雜表層322形成為一高摻雜p型表層且形成為約〇1 之厚 度。可使用Ρ型摻雜物（諸如硼、銦或任何其它口型摻雜物） 以形成ρ型表層322。 可藉由已知技術形成ρ型表層322。舉例而言，可藉由穿 過光阻層中之開口植入ρ型離子而形成層322。或者，可藉 由氣源電漿摻雜製程形成層322,或藉由自臨場摻雜層或摻 雜氧化物層（其在待形成層322之區域上沉積彡將卩型摻雜物 擴散入基板311内而形成層322。 蝕刻氧化物層307，使得殘留部分在重設閘極堆疊4〇6之 側壁上形成侧壁間隔。層307保留在轉移閘極堆疊4〇7 '光 104142-961225.doc -15- 1305929 電二極體323、浮動擴散區3〇5及一部分重設閉極堆疊刪之 上以達成圖3中所示結構。或者，可實施乾絲刻步驟以触 刻部分氧化物層307，使得僅側壁間隔（未圖示）殘留在轉移 閘極堆疊407及重設閘極堆疊4〇6上。 丄可使用習知處理方法以形成像素鳩之其它結構。舉例而 έ ’可形成絕緣層、屏蔽層及將閘極線及其它連接器連接 至像素300之金屬化層。亦可以（例如）二氧切、财玻璃 (BSG)、磷矽玻璃（PSG)或硼磷矽玻璃⑺psG)之鈍化層覆蓋 整個表面，該鈍化層被⑽平面化並㈣以提供接觸孔， 然後將其金屬化以提供接觸。f知導體及絕緣體層亦可用 來相互連接該等結構並連接像素3〇〇至外圍電路。 圖5描述根據本發明之另一例示性實施例之像素單元 500。 像素單疋5〇〇類似於像素單元細（圖此外導電隔離 層507僅應用於像素單元5⑽之影像感測器陣列之—部分。 圖6描述根據本發明之另一例示性實施例之像素單元 501。 像素單凡5()1類似於像素單元则⑽此外導電隔離 層517僅應用於像素單元5〇1之影像感測器陣列之一部分。 如圖6中所見’在一個較佳實施例中’導電隔離層517應用 於包圍障列電晶體且在光電二極體3〇3之表面區上之源極/ 沒極區。 雖然以上實施例係聯繫Ρ-η-Ρ型光電二極體之形成而描 述，但本發明不限於此等實施例。本發明亦可應用於其它 類！之光轉化裝置，諸如在基板中之η-ρ或η-ρ-η區域形成之 光電一極體、光閘或光電導體。若形成η-ρ-η型光電二極體， 104142-961225.doc -16- 1305929 則所有結構之摻雜劑及導電類型將因此而改變。 儘管聯繫4T像素單元300描述以上實施例，但像素單元 300之組態僅為例示性的，且亦可將本發明倂入具有不同數 篁電晶體之其它像素電路中。不加限制地，此一電路可包 括二電晶體（3T)像素单元、五電晶體（5T)像素單元、六電晶 體（6T)像素單元及七電晶體（7T)像素單元。3T單元省去轉移 電晶體，但可具有鄰近光電二極體之重設電晶體。5T、6T 及7T像素單元藉由分別添加一個、兩個或三個電晶體（諸如 快門電晶體（shutter transistor)、CMOS光閘電晶體及抗過度 曝光電晶體（anti-blooming transistor))而不同於4T像素單 元。此外’雖然聯繫CMOS像素單元300描述以上實施例， 但本發明亦可應用於電荷耦合裝置（CCD)影像感測器中之 像素單元。 由圖7之方塊圖說明典型單芯片CMOS影像感測器600。影 像感測器600包括具有上述一或多個像素單元3 〇〇、5 〇〇或 5〇1(分別為圖3、圖5或圖6)之像素單元陣列680。以預定數 目之行和列排列陣列680之像素單元。 一個接一個讀出陣列680中之像素單元列。因此，皆選擇 一列陣列680之像素單元以同時由一列選擇線讀出，且所選 列中每一像素單元提供代表接收光的訊號至其行之一讀出 線。在陣列680中，每一行亦具有一選擇線，且響應行選擇 線而選擇性讀出每一行之像素單元。 由列驅動器682響應列位址解碼器681而選擇性啟動陣列 680中之列線。由行驅動器684響應行位址解碼器685而選擇 104142-961225.doc •17- 1305929 性啟動行選擇線。藉由時序及控制電路683運作陣列680， 該時序及控制電路683控制位址解碼器68卜685以為像素讀 出選擇適當之列及行線。 行讀出線上之訊號通常包括每一像素單元之像素重設訊 號（Vrst)及像素影像訊號（Vph()t。）。響應行驅動器684將兩訊 號讀入一取樣與保持電路（S/H)686中。由每一像素單元之 差分放大器（AMP)687產生差分訊號（Vrst - Vphc)t。），且每一 像素單元之差分訊號藉由類比/數位轉換器（ADC)688而數 位化。類比/數位轉換器688供給數位化像素訊號至一影像 處理器689,其在提供定義影像輸出之數位訊號前執行適當 影像處理。 圖8說明包括圖7之影像感測器600的基於處理器之系統 700。該基於處理器之系統700為具有數位電路（可包括影像 感測器裝置）之例示性系統。不加限制地，此一系統可包括 電腦系統、相機系統、掃描儀、機械視覺、車用導航、視 訊電話、監視系統、自動對焦系統、星體跟蹤系統（star tracker system)、動態 4貞測系統（motion detection system)及 需要影像獲取之其它系統。 基於處理器之系統700(例如相機系統）通常包含一中央處 理單元（CPU)795(諸如一微處理器），其經由一匯流排793與 輸入/輸出（I/O)裝置791通信。影像感測器600亦經由匯流排 793與CPU 795通信。基於處理器之系統700亦包括隨機存儲 記憶體（RAM)792，且可包括可移除記憶體（removable memory)794，諸如快閃記憶體，其亦可經由匯流排793與 104142-961225.doc -18- 1305929 CPU 795通信。影像感測器600亦可與一處理器（諸如cpu、 數位訊號處理器或微處理器）組合，記憶儲存器在或不在單 一積體電路上或在除處理器之外之不同芯片上。 再次注意以上描述及圖示為例示性且說明達成本發明之 目的、特徵及優勢之較佳實施例。本發明不懲限制於所說 明之實施例。任何處於下列申請專利範圍之精神及範疇内 的本發明之修正應認為是本發明之一部分。舉例而言，儘 管所描述例示性實施例係參照CM0S 13_11_13像素單元描述， 但本發明不限制於彼結構（如，且可應用於像素單元之其它 構型，主動性及被動性），本發明亦不限制於彼技術（如，且 亦可應用於CCD技術）。 【圖式簡單說明】 自本發明t下料細描述將更好地理解本發明之前述及 其它態樣，其與附隨圖示相關而提供，其中： 圖1為習知像素單元之示意圖。 圖2為習知像素單元之橫截面圖。 圖3為依照本發明之例示性實施例之習知像素單元之橫 截面圖。 圖4 A描述處理之起始階段時圖3之像素單元。 圖4B-4L描述處理之中間階段時圖3之像素單元。 圖5為依照本發明之另一例示性實施例之習知像素單元 之橫戴面圖。 一圖6為依照本發明之仍另一例示性實施例之習知像素單 元之橫戴面圖。 104142.96l225.do, 1305929 圖7為依照本發明之例示性實施例之CMOS影像感測器之 方塊圖；及 圖8為併入圖3或5之CMOS影像感測器的電腦處理器系統 之示意圖。 【主要元件符號說明】Until recently, the growth of high quality SiC systems was very expensive, and thus SiC was only used for selective applications. Recent technological advances in epitaxial growth of SiC have made it less expensive and reduced defect density. These advances have made it more likely to use SiC substrates in conventional applications. Since the SiC channel can be formed or grown on the conventional Si layer and is part of the conventional Si process, it can be incorporated into the process of forming a CMOS photodiode. Recent advances in the formation of SiC layers can be found in (Examples) "A new Si:C epitaxial channel nMosfet Architecture with improved drivability and short-channel characteristics" » T. Ernest et al., 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 92-93; "Fabrication of a novel strained SiGeiC-channel planar 55nm nMosfet for High Performance CMOS", T. Ernest et al., 2002 Symposium on VLSI Technology Digest of Technical Papers » Pages 92-93; And "Selective growth of high-quality 3C-SiC using a Si02 sacrificial layer technique", Thin Solid Films. Vol. 345(2) (1999), pp. 19-99. 104142-961225.doc 1305929 Sic or carbonized stone channels are used in the pixel unit as the conductive isolation layer to reduce the current level. The present invention allows for a larger scaling on the pixel cell array because the dark current level is reduced. Larger scaling allows for a larger fill factor. The use of Sic or carbonized stone channels in a pixel cell as a conductive isolation layer also provides an additional advantage due to the nature of the materials. In particular, the tantalum carbide material allows high temperature operation and enables the pixel unit to withstand high electric fields. In addition, these substances also have the characteristics of effective heat dissipation. 4A-4J depict the formation of pixel cells 3A in accordance with an exemplary embodiment of the present invention. The steps described herein are not necessarily performed in any particular order except those that logically require the results of the prior actions. Accordingly, while the following steps are described in a general order, the order is merely illustrative and can be changed as needed. As illustrated in Fig. 4A, a pad oxide layer 441 (which may be a thermally grown oxide) is formed on the substrate 311. A sacrificial layer 442 is formed on the pad oxide layer 441. The sacrificial layer 442 can be a nitride or dielectric anti-reflective coating. 4B depicts a trench 430 formed in substrate 311 and passing through layer 44 442 on substrate 311. The trenches 43 can be formed by any known technique. For example, a patterned photoresist layer (not shown) is used as one of the etch masks. The first etch is performed using dry plasma conditions and difluoromethane/carbon tetrafluoride chemistry. This etch effectively etches the tantalum nitride layer 442 and the pad oxide layer 441 to form an opening therethrough that stops when it reaches the substrate 3 ι. A first etch is performed to extend the openings into the substrate 3A. The second etch 104142-961225.doc -10- 1305929 is a dry electropolymerized button using a difluoromethane/hydrogen bromide (CHJVHBr) chemistry. The timing of the engraving is to form a trench in the substrate 311 to a desired depth. A shorter etch time results in a shallower trench 43 〇. The photoresist mask (not shown) is removed using standard photoresist stripping techniques, preferably by plasma etching. As shown in FIG. 4C, a thin insulating layer 338 (between about 5 〇 a and about 25 〇 a thickness) is formed on sidewalls 336a, 336b and bottom 3〇8 of trench 430. In the embodiment depicted in Figure 4c, insulating layer 338 is an oxide layer 338 which is preferably grown by thermal oxidation. The trench 430 may be lined with a barrier film 339. In the embodiment shown in Figure 4 (the barrier/film 339 is a nitride profile, such as a nitride), the nitride liner 339 is formed by any suitable technique to a range of 5 〇a to about 250 Å. Thickness. As is known in the art, the tantalum nitride liner 339 can be formed by depositing ammonia (NH3) and decane (SiH4). As shown in Fig. 4C, the trench 430 is filled with a dielectric material 337. The electrical material 337 can be an oxide material such as a dream oxide such as Si bis or bismuth dioxide (Si 〇 2); an oxynitride; a nitride material such as nitriding; a carbonized dream; a high temperature polymer; A suitable dielectric material. In the illustrated embodiment, the dielectric material 337 is a high density plasma (HDP) oxide. As shown in Figure 4E, a chemical mechanical polishing (CMP) step is performed to remove the trench 430 and A nitride layer 339 on the surface of the substrate 311 other than the nitride layer 442. The pad oxide layer is also removed, for example, using a field wet buffered-oxide etch step and a cleaning step. 441 ° Figure 4F depicts the formation of a conductive isolation layer 301. The epitaxial conductive isolation layer 3〇1 is compared to 104142 -961225.doc 11 1305929 is preferably grown in a conventional manner (as previously outlined by Ernst). In a preferred embodiment, the epitaxial channel is grown at low temperatures. In a preferred embodiment, the electrically isolating layer 3 〇i is preferably Sic or carbonized channel broken ((5). Read d η - ^山叫. Conductive isolation layer 3 () 1 does not need to grow uniformly; thus the conductive isolation layer on the field region (such as wood trench 430) 3〇1 The depth may be smaller than the depth of the conductive isolation layer on the non-field region. In a preferred embodiment, the carbon concentration in the conductive isolation layer 301 is adjusted. The temperature at which the growth of Sl. C has been controlled affects the carbon of the conductive isolation layer 301. Concentration. In one embodiment of the invention, the conductive isolation layer is only located in the transistor region. In another embodiment of the invention, the conductive isolation layer is grown on another region of the substrate, such as a photodiode region. In another embodiment, the electrically conductive isolation layer is grown on a peripheral array of desired cells. In another embodiment, the electrically conductive isolation layer is grown over a plurality of regions, meaning a combination of the aforementioned locations, such as the following Shown in 5 and 6. Although not shown, one The nitride layer is formed prior to formation of the conductive isolation layer. The nitride deposition is patterned to expose a specific region to the formation of the conductive isolation layer 3〇1 according to aspects of the present invention. Flattening is performed on the conductive isolation layer 301 to produce A layer of relatively uniform height as seen in Figure 4 (}. The layer height may range from 100 A to 500 A with a typical height of about 250 A. In one embodiment of the invention, the conductive isolation layer is over the non-field region The height of 301 is about 25 A and the height of the conductive isolation layer 301 above the field region is less than about 250 A. After the planarization step, the nitride layer deposited before the formation of the conductive isolation layer 301 is removed by a chemical mechanical polishing (CMP) step. The nitride can be selectively removed depending on the embodiment of the invention. For example, in a particular embodiment, 104142-961225.doc -12- 1305929 may not require removal of the nitride layer along the periphery of the cell. Figure 4H depicts the formation of a transfer transistor 317 (Figure 3) gate stack 407 and a reset transistor 316 (Figure 3) gate stack 406. Although not shown, the source follower transistor and column select transistors 19, 18 (Fig. 1) can be formed simultaneously with the transfer transistor and reset transistors 317, 3 16 as described below, respectively. To form the transistor gate stacks 4〇7, 4〇6 shown in FIG. 4H, for example, one of the first insulating layers 4A ia of the yttria is grown or deposited on the substrate 311. In a preferred embodiment, the gate oxidation is formed by rapid thermal oxidation ("RT〇") or on-site vapor generation (ISSG). The first insulating layer 4?la is used as a gate oxide layer of the subsequently formed transistor gate 401b. A layer of conductive material 4?lb is then deposited on the oxide layer 4?13. The conductive layer 4 turns is used as the gate electrode of the transistors 317, 316 (Fig. 3). The conductive layer 4?lb may be a polysilicon layer which may be doped into a second conductivity type such as type 11. A second insulating layer 4?lc is deposited on the conductive layer 4011». The second insulating layer 4〇1 (; can be, for example, an oxide (8丨〇2), a nitride (tantalum nitride), an oxynitride (niobium oxynitride), 〇N (nitriding oxygen), N〇 ( Nitric oxide) or yttrium (oxygen, nitrogen, oxygen) is formed. The gate stack layers 401a, 401b, 401c can be formed by conventional deposition methods such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). The layers 4〇1&, 4〇lb, 4〇1〇 are then patterned and etched to form the multilayer gate stacks 407, 406 shown in Figure 4F. The invention is not limited to the above-described gate stacks 407, 406 Structures. Additional layers may be added or gate stacks 407, 406 may be modified as desired. For example, a germanide layer may be formed between the gate electrode 4〇1b and the second insulating layer 401c. (not shown). The germanide layer may be included in all of the transistor gate stack structures in the gates 104142-961225.doc • 13· 1305929 stacks 407, 406 or in the image sensor circuit, and Titanium telluride, tungsten telluride, cobalt telluride, molybdenum molybdenum or niobium button. This additional conductive layer can also be a barrier layer/fold Metal, such as titanium nitride/tungsten (TiN/W) or tungsten nitride/tungsten (WNx/w), or it may be entirely formed of tungsten nitride (WNX). Doped p-type well as shown in FIG. 334, 335 are implanted in the substrate 311. The first P-type well 334 is formed in the substrate 31 to surround the isolation region 333 and extends below the isolation region 333. The second p-type well 335 is formed in the substrate 311 from the self-transfer gate stack 407. The next point extends in the direction of the substrate 311 away from where the photodiode 323 (Fig. 3) is to be formed. The p wells 334, 335 are formed by known methods. For example, there may be a P 334 to be formed. A photoresist layer (not shown) is patterned on the substrate 311 of the opening on the region 335. A dopant such as boron may be implanted into the substrate 311 through an opening in the photoresist. The p% 334, 335 is formed to have a p-type dopant concentration higher than the adjacent portion of the substrate 311. Alternatively, the p-wells 334, 335 may be formed before the trench 430 is formed. As shown in Fig. 4J, the doped n-type is formed. The region 321 is implanted in the substrate 3 (in the photodiode 323 of Fig. 3). For example, the substrate 311 to be formed into the photodiode (Fig. 3) can be formed. A photoresist layer (not shown) is patterned on the substrate 3 ι having an opening on the surface. An n-type pod (such as a scale, Kun or recorded) can be implanted into the substrate 311 through the opening. The implant can be used to adjust the contour of the region. If it is desired to perform an angled implant Nation to form the doped region 321, the implant can be implanted at an angle other than 90 degrees from the surface of the substrate 3ι. 104142-961225.doc -14 - 1305929 As shown in Fig. 4J, the n-type region 321 is formed from a point adjacent to the transfer gate stack 4?7 and extends between the gate stack 407 and the isolation region 333 in the substrate 311. The region 321 forms a photosensitive charge accumulation region for collecting the charge generated by the light. The floating diffusion region 305 and the source/drain regions 3〇2 are implanted by a known method to achieve the structure shown in Fig. 4J. The floating diffusion region 3〇5 and the source/drain region 3〇2 are formed into an n-type region. Any suitable dopant such as phosphorus, arsenic or antimony may be used. The floating diffusion region 305 is formed on one side of the transfer gate stack 4?7 and the 11-type photodiode region 321 side. The source/drain region 3〇2 is formed on one side of the reset gate stack 406 opposite to the floating diffusion region 305. Figure 4K depicts the formation of a dielectric layer 307. As shown, layer 3〇7 is an oxide layer, but layer 307 can be any suitable dielectric material formed by methods known in the art, such as hafnium oxide, tantalum nitride, oxynitride or positive Tetraethyl phthalate (TEOS). As shown in FIG. 4L, the doped surface layer 322 of the photodiode 323 is implanted. The doped surface layer 322 is formed into a highly doped p-type skin layer and formed to a thickness of about 〇1. A erbium type dopant such as boron, indium or any other die dopant may be used to form the p-type skin layer 322. The p-type skin layer 322 can be formed by known techniques. For example, layer 322 can be formed by implanting p-type ions through openings in the photoresist layer. Alternatively, the process formation layer 322 may be doped by a gas source plasma, or may be diffused into the germanium dopant by a germanium doped layer or a doped oxide layer deposited on the region of the layer 322 to be formed. A layer 322 is formed in the substrate 311. The oxide layer 307 is etched such that the remaining portions form sidewall spacers on the sidewalls of the reset gate stack 4〇6. The layer 307 remains on the transfer gate stack 4〇7 'light 104142-961225 .doc -15- 1305929 Electric diode 323, floating diffusion zone 3〇5 and part of the reset closed-pole stack are added to achieve the structure shown in Figure 3. Alternatively, a dry wire engraving step can be performed to etch the partial oxidation. The layer 307 is such that only sidewall spacers (not shown) remain on the transfer gate stack 407 and the reset gate stack 4A. 习 Other conventional structures can be used to form other structures of the pixel. For example, An insulating layer, a shielding layer, and a metallization layer connecting the gate lines and other connectors to the pixel 300 may be formed. Alternatively, for example, dioxin, glass (BSG), phosphorous bismuth (PSG) or borophosphonium The passivation layer of glass (7) psG) covers the entire surface, and the passivation layer is planarized by (10) And (iv) to provide a contact hole and then metallize it to provide contact. The conductor and insulator layers can also be used to interconnect the structures and connect the pixels 3 to the peripheral circuitry. FIG. 5 depicts a pixel unit 500 in accordance with another exemplary embodiment of the present invention. The pixel unit 5 is similar to the pixel unit thin (the conductive isolation layer 507 is only applied to the image sensor array of the pixel unit 5 (10). FIG. 6 depicts a pixel unit according to another exemplary embodiment of the present invention. 501. Pixel single 5()1 is similar to pixel unit (10) Furthermore, conductive isolation layer 517 is only applied to one of the image sensor arrays of pixel unit 5〇1. As seen in Figure 6, 'in a preferred embodiment 'The conductive isolation layer 517 is applied to the source/no-polar region surrounding the barrier transistor and on the surface region of the photodiode 3〇3. Although the above embodiment is related to the Ρ-η-Ρ type photodiode It is described and described, but the present invention is not limited to the embodiments. The present invention is also applicable to other types of light conversion devices, such as a photodiode formed in a η-ρ or η-ρ-η region in a substrate, Photoreceptor or photoconductor. If η-ρ-η type photodiode is formed, 104142-961225.doc -16-1305929, the dopant and conductivity type of all structures will change accordingly. Although described in connection with 4T pixel unit 300 The above embodiment, but the group of pixel units 300 For illustrative purposes only, the invention may also be incorporated into other pixel circuits having different numbers of transistors. Without limitation, such a circuit may include a two transistor (3T) pixel unit, a five transistor (5T). a pixel unit, a six-electrode (6T) pixel unit, and a seven-electrode (7T) pixel unit. The 3T unit eliminates the transfer transistor, but may have a reset transistor adjacent to the photodiode. 5T, 6T, and 7T pixels The unit is different from the 4T pixel unit by adding one, two or three transistors, such as a shutter transistor, a CMOS shutter transistor, and an anti-blooming transistor, respectively. Although the above embodiment is described in connection with the CMOS pixel unit 300, the present invention is also applicable to a pixel unit in a charge coupled device (CCD) image sensor. A typical single chip CMOS image sensor 600 is illustrated by the block diagram of FIG. The image sensor 600 includes a pixel unit array 680 having one or more of the above-described one or more pixel units 3 〇〇, 5 〇〇 or 5 〇 1 (Fig. 3, Fig. 5 or Fig. 6, respectively). Column array a pixel unit of 680. The pixel unit columns in the array 680 are read one by one. Therefore, a column of pixel units of the array 680 is selected to be simultaneously read by a column of selection lines, and each pixel unit in the selected column provides representative reception light. The signal is to one of the row readout lines. In array 680, each row also has a select line, and the row cells of each row are selectively read in response to the row select lines. Column column driver 682 responds to the column address decoder 681 selectively activates the column lines in array 680. Row driver 684 selects 104142-961225.doc • 17-1305929 to initiate row select lines in response to row address decoder 685. The array 680 is operated by a timing and control circuit 683 which controls the address decoder 68 685 to select the appropriate columns and row lines for pixel reading. The signal on the line read line usually includes a pixel reset signal (Vrst) and a pixel image signal (Vph()t.) for each pixel unit. The response line driver 684 reads the two signals into a sample and hold circuit (S/H) 686. A differential signal (Vrst - Vphc)t is generated by a differential amplifier (AMP) 687 of each pixel unit. ), and the differential signal of each pixel unit is digitized by an analog/digital converter (ADC) 688. The analog/digital converter 688 supplies the digitized pixel signals to an image processor 689 that performs appropriate image processing prior to providing a digital signal defining the image output. FIG. 8 illustrates a processor-based system 700 that includes the image sensor 600 of FIG. The processor-based system 700 is an exemplary system having digital circuitry (which may include image sensor devices). Without limitation, the system may include a computer system, a camera system, a scanner, a machine vision, a car navigation, a video phone, a surveillance system, an auto focus system, a star tracker system, a dynamic 4 test system. (motion detection system) and other systems that require image acquisition. The processor-based system 700 (e.g., camera system) typically includes a central processing unit (CPU) 795 (such as a microprocessor) that communicates with an input/output (I/O) device 791 via a bus 793. Image sensor 600 also communicates with CPU 795 via bus 793. The processor-based system 700 also includes a random access memory (RAM) 792 and may include a removable memory 794, such as a flash memory, which may also be via bus bars 793 and 104142-961225.doc -18- 1305929 CPU 795 communication. Image sensor 600 can also be combined with a processor (such as a cpu, digital signal processor or microprocessor) that is either on or off a single integrated circuit or on a different chip than the processor. The above description and the drawings are intended to be illustrative and illustrative of the preferred embodiments of the invention. The invention is not limited to the embodiments described. Any modification of the invention within the spirit and scope of the following claims should be considered as part of the invention. For example, although the described exemplary embodiments are described with reference to a CM0S 13_11_13 pixel unit, the present invention is not limited to the structure (eg, and can be applied to other configurations of pixel units, initiative and passive), the present invention Nor is it limited to the technology (eg, and can also be applied to CCD technology). BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other aspects of the present invention will be better understood from the description of the present invention, which is provided in the accompanying drawings in which: FIG. 1 is a schematic diagram of a conventional pixel unit. 2 is a cross-sectional view of a conventional pixel unit. 3 is a cross-sectional view of a conventional pixel unit in accordance with an illustrative embodiment of the present invention. Figure 4A depicts the pixel cell of Figure 3 at the beginning of the process. Figures 4B-4L depict the pixel cells of Figure 3 during the intermediate stages of processing. Figure 5 is a cross-sectional view of a conventional pixel unit in accordance with another exemplary embodiment of the present invention. Figure 6 is a cross-sectional view of a conventional pixel unit in accordance with still another exemplary embodiment of the present invention. 104142.96l225.do, 1305929 FIG. 7 is a block diagram of a CMOS image sensor according to an exemplary embodiment of the present invention; and FIG. 8 is a schematic diagram of a computer processor system incorporating the CMOS image sensor of FIG. 3 or 5. . [Main component symbol description]

2 源極/ >及極區 3 淺渠溝隔離（STI)區 5 浮動擴散區 10 習知CMOS像素單元 11 p型活性層 16 重設電晶體 17 轉移電晶體 18 列選擇電晶體 19 源極隨耦器電晶體 21 η型光電二極體區 22 ρ型表層 23 光電二極體 301 導電隔離層 302 源極/ >及極區 303 光電二極體 305 浮動擴散區 307 介電層/氧化物層 311 基板/矽層 316 重設電晶體 104142-961225.doc -20- 13059292 source / > and polar region 3 shallow trench isolation (STI) region 5 floating diffusion region 10 conventional CMOS pixel unit 11 p-type active layer 16 reset transistor 17 transfer transistor 18 column select transistor 19 source Dependent transistor 21 η-type photodiode region 22 p-type surface layer 23 photodiode 301 conductive isolation layer 302 source / > and polar region 303 photodiode 305 floating diffusion region 307 dielectric layer / oxidation Object layer 311 substrate / layer 316 reset transistor 104142-961225.doc -20- 1305929

317 轉移電晶體 321 摻雜之n型區 322 摻雜表層/ρ型表層 323 光電二極體 333 隔離區 334 第一 Ρ型阱 335 第二Ρ型阱 337 介電材料 338 絕緣層 339 障壁薄膜 401a 第一絕緣層 401b 導電層/電晶體閘極 401c 第二絕緣層 406 重設電晶體閘極堆疊 407 轉移電晶體閘極堆疊 430 渠溝 441 襯墊氧化物層 442 犧牲層 500 像素單元 501 像素單元 507 導電隔離層 517 導電隔離層 600 影像感測器 680 像素單元陣列 104142-961225.doc -21 - 6811305929 682 683 684 685 686 687 688 689 700 791 792 793 794 795 列位址解碼器 列驅動器 控制電路 行驅動器 行位址解碼器 電路（S/H) 差分放大器（AMP) 類比/數位轉換器 影像處理器 基於處理器之系統 輸入/輸出（I/O)裝置 隨機存儲記憶體（RAM) 匯流排 記憶體 中央處理單元（CPU) 104142-961225.doc -22·317 Transfer transistor 321 doped n-type region 322 doped surface layer / p-type surface layer 323 photodiode 333 isolation region 334 first germanium well 335 second germanium well 337 dielectric material 338 insulating layer 339 barrier film 401a First insulating layer 401b conductive layer/transistor gate 401c second insulating layer 406 reset transistor gate stack 407 transfer transistor gate stack 430 trench 441 pad oxide layer 442 sacrificial layer 500 pixel unit 501 pixel unit 507 conductive isolation layer 517 conductive isolation layer 600 image sensor 680 pixel unit array 104142-961225.doc -21 - 6811305929 682 683 684 685 686 687 688 689 700 791 792 793 794 795 column address decoder column driver control circuit row Driver Row Address Decoder Circuit (S/H) Differential Amplifier (AMP) Analog/Digital Converter Image Processor Processor-Based System Input/Output (I/O) Device Random Access Memory (RAM) Bus Memory Central Processing Unit (CPU) 104142-961225.doc -22·

Claims (1)

1305多^127945號專利申請案 中文申請專利範圍替換本(97年8月） 十、申請專利範圍： 1. 一種像素單元，其包含： 一基板，其具有一像素單元區域； 一光轉換裝置，其形成於該基板上於該像素單元區域 中； 一含碳導電隔離層，其置於該像素單元區域之至少 部分上；及 一電晶體閘極堆疊，其形成於該導電隔離層上。 _ 2.如請求項1之像素單元，其中該基板包含Si。 3. 如請求項1之像素單元，其中該導電隔離層包含sic。 4. 如請求項1之像素單元，其中該導電隔離層包含碳化矽。 5·如請求項1之像素單元，其中該導電隔離層係形成為約 100A至約500A之深度。 6·如請求項1之像素單元’其中該導電隔離層係形成為約 250 A之深度。 7.如請求項1之像素單元，其中該光轉換裝置為一光電二極 •體。 8. 如請求項1之像素單元’其中該光轉換裝置為一光電導 體。 9. 如請求項1之像素單元，其中該光轉換裝置為一光閘。 10. —種像素單元，其包含： 一基板’其具有一包括一電晶體區之像素單元區域及 一光轉換區； 一光轉換裝置’其形成於該光轉換區； O:\104\104142-970825.doc 1305929 數個電晶體，其形成於該電晶體區； 一含碳導電隔離層，其置於該電晶體區上；及 電晶體閘極堆疊，其形成於該導電隔離層上。 11.如請求項1 〇之像素單元，其中該基板包含Si。 如請求項U之像素單元，其中該導電隔離層包含siC。 13.如請求項η之像素單元，其進一步包含： 一第二導電隔離層，其置於該電晶體區之—源極和汲 極上。 14 ·如請求項1 3之像素單元，其進一步包含： 一第三導電隔離層，其置於該光轉換區上。 15. —種像素單元，其包含： 一基板，其具有一電晶體區及一光轉換區，其中該電 晶體區具有源極及j：及極區；及 一含碳導電隔離層，其置於該電晶體區之該源極及汲 極區上。 1 6.如請求項1 5之像素單元，其中該基板包含Si。 1 7.如請求項1 6之像素單元，其中該導電隔離層包含SiC。 1 8.如請求項1 5之像素單元，其進一步包含： 一第二導電隔離層，其置於該光轉換區上。 19.如請求項1 5之像素單元，其中該導電隔離層包含碳化矽。 2 0. —種形成一像素單元之方法，該方法包含下列步驟： 形成一基板； 在該基板上於選定位置處形成一氮化物層以形成一曝 露圖案； O:\104\104142-970825.doc 1305929 在該基板上形成一光轉換裝置； 於對應該曝露圖案之位置處在該基板上形成—導電隔 離層，該導電隔離層係至少部分位於該光轉換裝置上；及 在該基板上形成用於操作該像素之一電晶體。 21. 如請求項20之方法，其中該導電隔離層為Sic。 22. 如請求項20之方法’其中該導電隔離層為碳化石夕。 23. 如請求項20之方法’其中該導電隔離層形成為約l〇〇 a至 約500 A之深度。 24. 如請求項20之方法，其中該導電隔離層形成為約25〇 a之 深度。 25. 如請求項20之方法，其中該導電隔離層形成於該像素單 元之一電晶體區中。 26. 如請求項23之方法，其中該導電隔離層形成於該像素單 元之一光轉換區中。 27. 如請求項23之方法，其中該導電隔離層形成於該像素單 元之一外圍區中。 28. 如請求項20之方法，其中該導電隔離層形成於該像素單 元之一源極及沒極區上。 2 9.如請求項2 8之方法，其中該導電隔離層形成於遺像素單 元之該光轉換區中。 3 0. —種形成一像素單元之方法，該方法包含下列步驟： 形成一基板； 在該基板上形成一光轉換裝置； 在該基板上形成一富碳導電隔離層，該富破導電隔離 ΟΛ104\104 丨 42-970825.doc 1305929 層係至少部分位於該光轉換裝置上；及 κ基板上形成用以操作該像素之一電晶體。 31.如請求項30之方法，其進一步包含以下步驟：在形成該 導^隔離層之步驟前在該基板上形成—氮化物層。 卜求項31之方法’其中該氮化物層選擇性形成於該基 板上。1305+ 127945 Patent Application Chinese Patent Application Range Replacement (August 97) X. Patent Application Range: 1. A pixel unit comprising: a substrate having a pixel unit area; a light conversion device, Formed on the substrate in the pixel unit region; a carbon-containing conductive isolation layer disposed on at least a portion of the pixel unit region; and a transistor gate stack formed on the conductive isolation layer. 2. The pixel unit of claim 1, wherein the substrate comprises Si. 3. The pixel unit of claim 1, wherein the conductive isolation layer comprises sic. 4. The pixel unit of claim 1, wherein the conductive isolation layer comprises tantalum carbide. 5. The pixel unit of claim 1, wherein the conductive isolation layer is formed to a depth of from about 100A to about 500A. 6. The pixel unit of claim 1 wherein the conductive isolation layer is formed to a depth of about 250 Å. 7. The pixel unit of claim 1, wherein the light converting device is a photodiode body. 8. The pixel unit of claim 1 wherein the light converting device is a photoconductor. 9. The pixel unit of claim 1, wherein the light conversion device is a shutter. 10. A pixel unit comprising: a substrate having a pixel unit region including a transistor region and a light conversion region; a light conversion device 'formed in the light conversion region; O:\104\104142 - 970825.doc 1305929 A plurality of transistors formed in the transistor region; a carbon-containing conductive isolation layer disposed on the transistor region; and a transistor gate stack formed on the conductive isolation layer. 11. The pixel unit of claim 1, wherein the substrate comprises Si. A pixel unit as claimed in item U, wherein the conductive isolation layer comprises a siC. 13. The pixel unit of claim n, further comprising: a second electrically conductive isolation layer disposed on the source and the drain of the transistor region. 14. The pixel unit of claim 13, further comprising: a third conductive isolation layer disposed on the light conversion region. 15. A pixel unit comprising: a substrate having a transistor region and a light conversion region, wherein the transistor region has a source and a j: and a polar region; and a carbon-containing conductive isolation layer is disposed On the source and drain regions of the transistor region. 1 6. The pixel unit of claim 15 wherein the substrate comprises Si. 1 7. The pixel unit of claim 16, wherein the conductive isolation layer comprises SiC. 1 8. The pixel unit of claim 15, further comprising: a second conductive isolation layer disposed on the light conversion region. 19. The pixel unit of claim 15, wherein the conductive isolation layer comprises tantalum carbide. A method of forming a pixel unit, the method comprising the steps of: forming a substrate; forming a nitride layer on the substrate at a selected location to form an exposed pattern; O:\104\104142-970825. Doc 1305929, forming a light conversion device on the substrate; forming a conductive isolation layer on the substrate at a position corresponding to the exposed pattern, the conductive isolation layer being at least partially located on the light conversion device; and forming on the substrate Used to operate one of the transistors. 21. The method of claim 20, wherein the conductive isolation layer is Sic. 22. The method of claim 20 wherein the conductive isolation layer is carbon carbide. 23. The method of claim 20 wherein the electrically conductive barrier layer is formed to a depth of from about 10 Å to about 500 Å. 24. The method of claim 20, wherein the electrically conductive isolation layer is formed to a depth of about 25 〇 a. 25. The method of claim 20, wherein the electrically conductive isolation layer is formed in one of the transistor regions of the pixel unit. 26. The method of claim 23, wherein the conductive isolation layer is formed in one of the light conversion regions of the pixel unit. 27. The method of claim 23, wherein the electrically conductive isolation layer is formed in a peripheral region of the pixel unit. 28. The method of claim 20, wherein the conductive isolation layer is formed on one of the source and the non-polar regions of the pixel unit. The method of claim 28, wherein the conductive isolation layer is formed in the light conversion region of the pixel unit. A method of forming a pixel unit, the method comprising the steps of: forming a substrate; forming a light conversion device on the substrate; forming a carbon-rich conductive isolation layer on the substrate, the rich conductive isolation barrier 104 \104 丨 42-970825.doc 1305929 The layer is at least partially located on the light conversion device; and the κ substrate is formed to operate a transistor of the pixel. 31. The method of claim 30, further comprising the step of forming a nitride layer on the substrate prior to the step of forming the isolation layer. The method of claim 31 wherein the nitride layer is selectively formed on the substrate. 33. 如請求項31之方法’其中該氮化物層選擇性形成於該基 板上以曝露一電晶體區。 34. 如请求項31之方法，其中該氮化物層選擇性形成於該基 板上以曝露一光轉換區。 士叫求項3 1之方法，其巾錢化物層選擇性形成於該基 板上以曝露一外圍區。 36.如明求項3 i之方法，其中該形成該富碳導電隔離層之步 驟經由磊晶生長完成。 37. 如请求項32之方法’其巾該經由m長形成該富碳導 電隔離層之步驟於低溫下執行。 3 8·如。月求項3 i之方法，其進一步包含以下步驟：在該形成 該導電隔離層之步驟後在該基板上形成該氮化物層。 3 9 ·如請求項3 8之方法，甘、办 ^ , A * 其進一步包含以下步驟：在該氮化 物層上形成一用於閘極氧化之種子層。 其中該種子層形成自矽。 其進一步包含以下步驟：在該層上 40. 如請求項38之方法， 41. 如請求項3 9之方法， 形成一閘極氧化層。 42.如請求項41之方法 其中該閘極氧化層由快速熱氧化而 O:\104\104142-970825.doc 1305929 形成。 43.如請求項42之方法，其中該閘極4 j極虱化層由臨場蒸氣產生 而形成。 44· 一種成像器，其包含： 至少一像素單元，該至少一像素單元包含： 一基板，其具有一像素單元區域； -光轉換裝置，其形成於該基板上於該像素單元區域 中； 一含碳導電隔離層，其置於該像素單元區域之至少一 部分上；及33. The method of claim 31 wherein the nitride layer is selectively formed on the substrate to expose a transistor region. 34. The method of claim 31, wherein the nitride layer is selectively formed on the substrate to expose a light conversion region. The method of claim 3, wherein the towel layer is selectively formed on the substrate to expose a peripheral region. 36. The method of claim 3, wherein the step of forming the carbon-rich conductive isolation layer is accomplished via epitaxial growth. 37. The method of claim 32, wherein the step of forming the carbon-rich conductive isolation layer via m length is performed at a low temperature. 3 8·如如. The method of claim 3, further comprising the step of forming the nitride layer on the substrate after the step of forming the conductive isolation layer. 39. The method of claim 38, wherein the method further comprises the step of forming a seed layer for gate oxidation on the nitride layer. Wherein the seed layer is formed from a crucible. It further comprises the steps of: on the layer 40. The method of claim 38, 41. The method of claim 39, forming a gate oxide layer. 42. The method of claim 41 wherein the gate oxide layer is formed by rapid thermal oxidation and O:\104\104142-970825.doc 1305929. 43. The method of claim 42, wherein the gate 4j pole deuteration layer is formed by a field vapor. 44. An imager, comprising: at least one pixel unit, the at least one pixel unit comprising: a substrate having a pixel unit region; and a light conversion device formed on the substrate in the pixel unit region; a carbon-containing conductive isolation layer disposed on at least a portion of the pixel unit region; and 一電晶體閘極堆疊， 45. 如請求項44之成像器， 46. 如請求項44之成像器， 47. 如請求項44之成像器， 48. 如請求項44之成像器， 至約500 A之深度。 49. 如請求項44之成像器， 之深度。 其形成於該導電隔離層上。 其中該基板包含Si。 其中該導電隔離層包含81(：。 其中該導電隔離層包含碳化石夕。 其中該導電_㈣成為約⑽入 其中該導電隔離層形成為約謂a 5〇·如請求項44之成像器，其中該光轉換裝置為 體。 光電二極 5 1 ·如請求項44之成像器，其中該光轉換裴置為— 52. 如請求項44之成像器，其中該光轉換裝置為— 53. —種成像器，其包含： 先電導體 光閘。 〇 至少一像素單元，該至少一像素單元包含. O:\104\104U2-970825.doc 1305929 一基板，其具有一電晶體區及一光轉換區，其中該電 - 晶體區具有源極及》及極區， — 一含碳導電隔離層，其置於該電晶體區之該源極及汲 - 極區上，及 一電晶體閘極堆疊，其形成於該導電隔離層上。 54.如請求項53之成像器，其中該基板包含Si。 5 5.如請求項54之成像器，其中該導電隔離層包含SiC。 56.如請求項53之成像器，其進一步包含： _ 一第二導電隔離層，其置於該光轉換區上。a transistor gate stack, 45. The imager of claim 44, 46. The imager of claim 44, 47. The imager of claim 44, 48. The imager of claim 44, up to about 500 The depth of A. 49. The depth of the imager as claimed in item 44. It is formed on the conductive isolation layer. Wherein the substrate comprises Si. Wherein the conductive isolation layer comprises 81 (wherein the conductive isolation layer comprises carbon carbide eve. wherein the conductive _ (four) becomes about (10) into the image forming device, wherein the conductive isolation layer is formed to be about a 5 〇 · The photo-converting device is a body. Photoelectric diode 5 1 · The imager of claim 44, wherein the optical conversion device is - 52. The imager of claim 44, wherein the optical conversion device is - 53. An imager comprising: a first electrical conductor shutter. 〇 at least one pixel unit, the at least one pixel unit comprising: O:\104\104U2-970825.doc 1305929 a substrate having a transistor region and a light conversion a region, wherein the electro-crystalline region has a source and a polar region, a carbon-containing conductive isolation layer disposed on the source and the drain region of the transistor region, and a transistor gate stack The imager of claim 53, wherein the substrate comprises Si. 5. The imager of claim 54, wherein the conductive isolation layer comprises SiC. The imager of 53 further comprising: _ a first A conductive isolation layer is disposed on the light conversion region. O:\104\104142-970825.docO:\104\104142-970825.doc
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