TWI305323B - Method for verification branch prediction mechanisms and readable recording medium for storing program thereof - Google Patents
Method for verification branch prediction mechanisms and readable recording medium for storing program thereof Download PDFInfo
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
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Description
I3053Q85twf.doc 九、發明說明: 【發明所屬之技術領域】
本發明f關胃於—種分支(^⑻指令_ _的驗 證方法。且特別疋有關於一種分支目標緩衝 B branch target buffer)機制之驗證方法及可讀取記錄^ , 【先前技術】 目前處理器大多採用管線(Pipeline)架構以及快取記憶 體,以增進系統效率。在此架構下,提取(fetch)指令之錯 誤率將影響祕之運作魏。t處理减行分支(b_h) 指^ ’需翻下-個指令之位址,以便於提前提取指令 至官線中進行下一步驟(例如解碼)。當預判不正確致使預 取錯誤的齡時,則管料所錢行㈣指令很可能必須 捨棄而重新提取正確指令至管線中。因此,分支預測 (branch prediction)將成為影響系統效能重要機制之一。 在各種分支預測之技術中’分支目標緩衝器(Btb) 機制是常見的分支預測技術之一。分支目標緩衝器是一種 用硬體方式來記錄曾發生過的分支指令狀態及資料,以提 供下一次分支指令再發生時’可以直接從此緩衝器中獲得 所需之分支目標指令。因此,可以減少分支損失(branch penalty) ’達到減少程式的執行延遲以獲得較佳的系統效 能0 對於中央處理單元(CPU)、數位訊號處理器(DSP)等處 理盗而言’由於分支目標緩衝器機制在系統效能與處理量 上有相當大的影響,因此必須驗證所設計之分支目標缓衝 器機制是否有效。一般驗證方法係依照所設計之分支目標 I3〇53?385twf,oc
緩衝减狀_而料不_迴_證程式 本(Pattern)來達到一個可接受的涵蓋率_ = U 有的分支_狀況中可被驗證之比率)。但是分支目 為'的設計與驗證方法的架構相互依賴,容易造=方 ,盲=即無法涵蓋各種可能情況)。再者,使用不同=分 支目“緩肺機_,需要糾設計驗證程式叫配欲驗 證之分支目標緩衝器。因此必須等到分支目標緩衝 =後才能開始料專用的驗證方法,因此延長了產二 【發明内容】 本發明之目的就是在提供一種分支指令預測 證方法’以提供設計者驗證分支指令預測機制(例如八 標緩衝器)。此驗證方法適各齡支指令糊機: 而不,更改驗證方法之設計,並且提供參數設定以便設計 者決定驗證之涵蓋率(coverage)與驗證所需時間。认 以 本發明的之再一目的是提供一種可讀取記錄媒體 儲存具有前述諸目的之程式。 、— 本發明提出一種分支(branch)指令預測機制之驗證方 法,用以驗證一處理器中之該分支指令預測機制(例如^支 目標緩衝器BTB)。此驗證方法包括於該處理器中提供並執 行一驗證程式。此驗證程式中具有至少一個分支指二,其 中分支指令係依照條件而決定是否遞迴(recursive) ^ ^
執行此驗證程式。 W 130531· 依照本發明的較佳實躺所述分 證方法,更包括提供至少—參數。此之驗 錄式可驗證此分支指令麵卿的狀態之涵蓋^,驗 μ依照本發_較佳實施觸述分支指令預剛播。 故方法’其中前述條件係判斷所提供之參數之驗 係。驗證程式例士〇包括進行下列步驟。首先進2值之關 斷;依據判斷該條件之結果以決定是否將分^指=件之判 ^令位址與參數儲存至堆疊中;依據判斷該條下一 3是數之值;依據判斷該條件之結果‘^ 執仃刀支扣々,自堆疊取回被儲存之分支指令 々位址與參數;以及依所取回之分支指令之下-指 以返回前切叫驗難紅分支齡之下位址 本發明提出-種可讀取記錄媒體,用以儲存。 處理器的驗證程式,其中驗證喊用以驗證處理=行於 支指令預測機制。驗證程式包括分支指令,此分° :之分 g 了條件而決定是否以遞迴(r_ive)呼叫並執二= 依照本發明的較佳實施例所述之可讀取記錄 中該驗證程式更包括下列指令:設定至少一參數,、’八 =以決定驗證程式可驗證分支指令預測機制的狀 = 率。前述之條件係判斷該參數與目標值之關係。〜' /函盍 '、本發明因以遞迴(recursive)呼叫並配合參數之 以近似亂數地產生各種測試樣本(pattem)以驗證分、可 預測機制(例如BTB)。因此,本發明之驗證方法^適^ Ι3〇53?1— 任何分支指令預測機制之架構,更藉由參數之 ^ 汁者可以決定驗狀涵蓋率(e_,age)與驗證=使& 為讓本發明之上述和其他目的、特 、曰。 易懂,下文牲與一&社每#λ丨^ I*點月b更明顯 說明如下。較佳以例,並配合所_式,作詳細 【實施方式】 分支目標緩肺(刪厌-_快取記憶 衝器以作為程式流程控制的整合電路。分支目===綾 ^己錄曾經發生過的分支指令狀態及資料, ^再次發生時可直接從這緩衝器中獲得所需的 二广r=rnstmcti〇n),達到減少程式的執行: 的表現。因此分支目標緩衝器執行的正確性 的驗證程歧斜的重要。 日彳邊衝器 、有鑑於此,在此依照本發明分支指令預測機制之驗證 方=舉出—實施例。圖1是依照本發明實施例所繪示的1 種分支(branch)指令預測機制之驗證方法的流程圖。此驗證 方^係用以驗證處理器中之分支指令預測機制(例如分。支 目標緩衝器BTB)。請參照圖1,於步驟S110中,提供並 =該處理器中執行一驗證程式。其中驗證程式中具有至少 —個分支指令’而此分支指令係依照條件而決定是否遞迴 Oeeui^ve)呼叫並執行此驗證程式。 在執行驗證程式之前,本實施例更於步驟S120中提 供至少一個參數。此參數係用以決定前述驗證程式可驗證 此刀支指令預測機制的狀態之涵蓋率。因此,步驟S130 85twf.doc 存器r9、rlO。於下述實施例中暫存器r8將用以放置遞迴 程序(recursive routine )完成後的回歸位置,暫存器r7則 作為堆疊指位器(Stack pointer) ’指向堆疊的起始位置。 上述驗證程式在此例如為副程式(subroutine) RECUR,而主 程式之部分片段例如為: LDR r7, =STACK LDR r8, =DONE STMFD r7, {r8-rl0}
MOV r9, #3 MOV rlO, #0 B RECUR DONE
LTORG STACKBASE EQU 0x1000 STACK—SIZE EQU STACK _BASE H -0x1000 ALIGN STACK _BASE STACK ALIGN STACK _SIZE 其中,「LDR r7,= :STACK」 係將標記(label) STACK 所在位址存放於暫存器r7,用以指出堆疊的最上一筆資料 位址。「LDR r8, =DONE」則將標記DONE所在位址存 放於暫存器r8,用以指出稍後自副程式RECUR返回主程 式之位址。「STMFD r7,(r8-rl0)」係將暫存器r8〜rl〇之 130531- 内容存放置堆疊中(即暫存器r7指出之位址)。「MOV r9,#3」、「MOV rl0,#0」係將參數(本實施例中譬如為3 與〇)分別存放在暫存器r9、rlO。然後執行「B RECUR」 開始呼叫(跳至)驗證程式(即副程式RECUR)。依照本發明 之精神’本實施例中副程式RECUR之程式碼例如為: RECUR CMP r9,#2 LDRGE r8-RETURN3 STMGEFD r7!,{r8-rl0} SUBGE r9,r9,#2 ADDGE rl0,rl0,#l BGE RECUR RETURN3 CMP r9,#l LDRGE r8,二 RETURN2 STMGEFD r7!,{r8-rl0} SUBGE r9,r9,#l BGE RECUR RETURN2 CMP rl0,#l LDRGE r8,二 RETURN1 STMGEFD r7!,{r8-rl0} SUBGE rl0,rl0,#l BGE RECUR RETURN 1 CMP rl0,#l LDRGE r8 ,=RETURN0 STMGEFD r7!,{r8-rl0} SUBGE rlO, rl0,#l I3053^85tw,〇c BGE RECUR RETURNO NOP LDMFD r7!,{r8-rl0} MOV PC,r8 其中,「CMP r9,#2」係判斷(比較)參數(暫存器r9 之值)與目標值(在此為2)之關係。r ldRGE Γ8 =RETURN3」與「STMGEFD Γ7!肿γ10)」分別依據判斷 結果(在此為判斷暫存器r9之值是否大於等於2)決定是否 分別將分支指令「BGE RECUR」之下一指令位址(即斤 記RETURN3之位址)與參數(暫存器r9、rl〇之值)儲存^ 堆疊中。「SUBGE r9,r9,#2」與「ADDGE rl〇,rl〇,#1」 相當於前述步驟S150 ’用以當參數大於等於目標值時調整 參數之值(在此例如將r9之值減2、rl〇之值加丨)。然後於 步驟S160中執行分支指令「BGE RECUR」以依據判斷 條件(參數是否大於等於目標值)之結果以決定是否遞迴呼 叫並執行此驗證程式(跳至標記RECUR)。也就是說,若某 一條件判斷成立,則將分支指令之下一位址儲存至堆疊後 跳躍至此驗證程式而重複進行(例如重複進行步驟, 直到該條件判斷不成立時才自堆疊取回前次跳躍之分支指 令之下一位址並返回該位址,此即所謂遞迴。 於本實施例中’驗證程式(即副程式RECUR)係應用上 述之驗證方法四次(實作為四個程式段,分別為標記 RECUR〜標記RETURN3、標記RETURN3〜標記 RETURN2、標記RETURN2〜標記RETURN1以及標記 RETURN1〜標記RETURN0)。其中差別在於判斷(比較) 12 Ι3053ι· 判斷值各不相同(例如標記RETURN2之程式段係 判斷暫存器rl0之值是 心枉式#又係 亦各不相_如料 等於υ,以及瓣參數之值 之值減1後存回_。孰朵Ν2之程式段係將暫存器r10 並類推其餘未說明之指;:述說明瞭解 後及讀㈣斷^進行遞迴程序
r7! Γγ8- lm 田N〇之程式段。亦即,執行rLDMFD ϋ r )」自堆《取回先前被儲存分支指令下一位盘 i^S1:〇^^«^MOV PC,r8j^;:; 7下位址存放在處理器之程式計數器(PC, program _ter)中以返回前次呼叫驗證程式分支指令之 下--位址(步驟S180)。 +& ίΓ更加以朗本實施例,以下將以® 2說明當設 疋參數為3與G時驗證程式之程式執行過程。圖2是依昭 本發明較佳實關巾以邏輯觀點崎_ —種驗證程式之 程式„程之樹狀圖。請參關2,其中每—方塊表示 於邏輯觀點上被遞财叫/執狀驗證料(即前述之副程 式RECUR)。每-方塊中上部括弧(例如方塊2〇1之括弧 201a)表示當時遞迴呼叫並執行驗證程式時之參數狀態。每 一方塊中下部括弧(例如方塊201之括弧2〇1的表示遞迴執 行該驗證程式期間其中各個程式段之條件判斷狀態,其中 C表示標記RECUR〜標記RETURN3之程式段、表示標 記RETURN3〜標記肅麵2之程式段、T2表示標記 RETURN2〜標記RETURN1之程式段、τι表示標記 RETURN1〜標記RETURN0之程式段以及τ〇表示標記 13 13053為85· RETURN0以下之程式段。每一方塊中c、T3、T2、T1 TO之刪除線表示當時對應之該程式段的條件判斷不成 立,亦y該程式段中的分支指令未能分支跳躍(一般稱該分 支指令’’not taken”);反之,未加上刪除線者表示當時^二 之該程式段的條件判斷成立,亦即該程式段中的分支指二 進行分支跳躍(一般稱該分支指令”taken”)。 S 7 延續前述實施例之假設,在此亦選定參數為3與〇 別存放於暫存器ήιο)。因此,當絲式呼叫並執行ς 式日才,圖2中係以方塊2〇1表示此驗證程式之邏輯狀 態。由於此時暫存器r9之值為3 (大於等於2),因此進行 標記RECUR〜標記RETURN3之程式段。亦即將分支指令 「BGE RECUR」之下一指令位址(即標記RETURN3之 位址)與參數3與〇 (暫存器γ9、γ10之值)儲存至堆疊中。 然後調整參數之值(在此例如將r9之值減2、rl〇之值加 並且進行分支跳躍(該分支指令”taken”)以遞迴呼叫並執行 此驗證程式(跳至標記RECUR),於邏輯觀點上,以圖2之 方塊202表示此時遞迴程序中所呼叫之驗證程式(此時參 數為1、1)。 方塊202之狀態下,由於暫存器Γ9之值為1 (不大於 等於2),因此不進行標記RECUR〜標記RETURN3之程式 段中之各步驟(即此程式段之分支指令” not taken”,圖中以 方塊202之”C”加上刪除線表示之)。然後執行下一程式段 (標記RETURN3〜標記rETURN2)。因為此時暫存器r9之 值為1 (大於等於丨),因此先將分支指令「BGE RECUR」 之下一指令位址(即標記RETURN2之位址)與參數1與1 14 I3053^85tw,oc (暫存器Γ9、Γ10之值)儲存至堆疊中,然後調整參數之 此例如將r9之值減1) ’並且進行分支跳躍(該分支浐 令,’taken”)以遞迴呼叫並執行此驗證程式(跳至^ Recur)。於邏輯觀點上,以圖2之方塊2〇3表示此日7"夺遞 迴程序中所呼叫之驗證程式(此時參數為〇、υ。 方塊203之狀態下,由於暫存器r9之值為〇,因此不 進行標記RECUR〜標記RETURN2之程式段中之各步驟(即 此二個程式段之分支指令”n〇t taken”,圖中以方塊2〇3 之C’及’’T3”加上刪除線表示之)。然後執行下一程式段(標 記RETURN2〜標記RETURN1)。因為此時暫存器rl〇之值 為1 (大於等於1) ’因此先將分支指令「BGE RECUR」 之下一指令位址(即標記RETURN1之位址)與參數〇與」工 (暫存器r9、rl0之值)儲存至堆疊中,然後調整參數之值(在 此例如將rlO之值減1),並且進行分支跳躍(該分支指 令’’taken”)以遞迴呼叫並執行此驗證程式(跳至標記 RECUR)。於邏輯觀點上,以圖2之方塊2〇4表示此時遞 迴程序中所呼叫之驗證程式(此時參數為〇、〇)。 方塊204之邏輯狀態下,由於暫存器r9、rl〇之值皆 為0,因此不進行標記RECUR〜標記RETURN0之程式段 中之各步驟(即此四個程式段之分支指令”n〇t taken,,,圖中 以方塊204之”C,,、,,Τ3,,、”T2”及,,ΤΓ,加上刪除線表示之)。 然後執行下一程式段(標記RETURN0)。此程式段之主要功 能在於控制遞迴程序,因此分支指令「MOV PC,r8」必 會”taken”。在此程式段,自堆疊取回前次跳躍時之參數狀 態與分支指令之下一位址(即標記RETURN1之位址)並返 15 13053¾^ 回該位址,在邏輯上則如圖2所示自方塊2〇4返回方塊2〇3 並繼續進行標記RETURN1之程式段。 返回方塊203後,由於自堆疊取回暫存器r9、rl〇之 值(導致暫存器r9、rlO之值分別為〇、1},因此進行標記 RETURN1之程式段中之各步驟(因而此程式段之分支^ ^ 為’心]^11”)。因為此時暫存器14〇之值為1(大於等於1)了 因此先將分支指令「職RECUR」之下一指令位址(即 才示s己RETURN0之位址)與參數〇與1 (暫存器r9、rl〇之值) 儲存至堆疊中,然後調整參數之值(在此例如將Η〇之值減 1),並且進行分支跳躍以遞迴呼叫並執行此驗證程式(跳至 標記RECUR)。於邏輯觀點上,以圖2之方塊2〇5表示此 時遞迴程序中所呼叫之驗證程式(此時參數為〇、〇)。 、方塊205之邏輯狀態下,由於暫存器Γ9、rl0之值皆 為〇,其操作類似於方塊204,故不在此贅述。然後自堆疊 取回前次跳躍時之參數狀態與分支指令之下一位址(即^ 記RETURN0之位址)並返回該位址,在邏輯上則如圖^ 示自方塊205返回方塊203並繼續進行標記RETURN〇之 程式段。因此’再自堆疊取回前次跳躍時之參數狀態與分 支指令之下-健(即標記RETURN2之位址)並返回該位 ^,在邏輯上則如圖2所示自方塊2〇3返回方塊逝並繼 績進打標記RETURN2之程狀。於糖觀點上,以圖2 ^方塊2G6表示此時遞迴程序中所呼叫之驗證程式(此時 參數為1、0)。 。依據上述’熟習此藝者應可瞭解並類推本實施例遞迴 程序’於邏輯上將依照圖2中虛線之順序(方塊篇至方塊 16 1305321—c 215),最後返回方塊201。因此’其餘過程將不再贅述。 依據上述,可分析出驗證程式中各分支指令之跳躍狀況 (’’taken”或’’not taken”)。分析結果如表1所示。 表1是依照本發明實施例(驗證參數設為3、0)中各程 式段分支指令之跳躍1 史況分析表。 時序 C T3 T2 T1 TO 1 taken taken taken not taken taken 2 not taken not taken not taken taken taken 3 not taken not taken not taken not taken taken 4 not taken not taken taken not taken taken 5 not taken taken not taken not taken taken 6 not taken not taken not taken taken taken 7 not taken taken not taken not taken taken 8 not taken not taken not taken not taken taken 9 not taken taken taken not taken taken 10 taken not taken not taken taken taken 11 not taken not taken not taken not taken taken 12 not taken not taken not taken not taken taken 13 not taken taken not taken not taken taken 14 not taken taken not taken not taken taken _15 not taken not taken not taken not taken taken taken總計 2 6 3 — 3 15 not taken 總計 13 9 12 12 0 由表1可看出於驗證過程中各分支指令(c、T3、T2、 τι、το)之跳躍狀況(”taken”或,’not taken”),因以遞迴 (recursive)呼叫並配合參數之選擇,可以近似亂數地產生各 種測試樣本(Pattern)以驗證分支指令預測機制(例如 BTB)。需注意的是,本發明之驗證方法係無關於分支指令 預測機制之設計架構,因此可適用於任何分支指令預測機 制。 本發明更可藉由參數之選定使設計者可以決定驗證之 涵蓋率(coverage)與驗證所需時間。在此繼續沿用前述實施 17 I305323785twfdoc 例之驗證程式’不同在於進行驗證前將參數由前述3與〇 改為4與〇。因此,依前所述’可透過分析驗證程式而獲 得表2。 表2是依照本發明實施例(驗證參數設為4、〇)中各程 式段分支指令之跳躍狀況分析表。 時序 C T3 T2 T1 TO __ 1 taken not taken taken not taken taken 2 taken not taken taken taken taken 3 not taken not taken not taken not taken taken — 4 not taken not taken not taken taken taken 5 not taken not taken taken not taken taken 6 not taken not taken not taken taken taken 7 not taken not taken not taken not taken taken 8 not taken taken taken not taken taken 9 not taken taken not taken taken taken __ 10 not taken not taken not taken not taken taken 11 not taken not taken taken not taken taken 12 not taken not taken not taken not taken taken 13 not taken taken not taken taken taken 14 not taken not taken not taken not taken taken 15 not taken taken not taken not taken taken __ 16 not taken not taken taken not taken taken 17 —-— not taken not taken taken taken taken 18 taken not taken not taken not taken taken __ 19 not taken not taken not taken not taken taken ~~~~20- not taken taken not taken not taken taken __ 21 not taken taken not taken not taken taken 22 not taken not taken not taken taken taken 23 not taken not taken taken not taken taken 24 taken not taken not taken taken taken 25 not taken not taken not taken not taken taken __ 26 not taken taken not taken not taken taken 27 not taken taken not taken not taken taken __ 28 not taken not taken not taken not taken taken 29 not taken taken taken not taken taken 30 taken taken not taken taken taken 31 not taken not taken not taken not taken taken 18 13053¾ 785twf.doc 13053¾ 785twf.doc 32 not taken not taken taken not taken taken 33 not taken not taken not taken not taken taken 34 not taken taken not taken taken taken 35 not taken not taken not taken not taken taken 36 not taken taken not taken not taken taken 37 not taken not taken taken not taken taken 38 not taken taken not taken taken taken 39 taken not taken not taken not taken taken 40 not taken not taken not taken not taken taken 41 not taken not taken not taken not taken taken 42 not taken taken not taken not taken taken 43 not taken taken not taken not taken taken 44 not taken not taken not taken not taken taken taken總計 6 15 11 11 44 not taken 總計 38 29 33 33 0 比較表1與表2後可知,本實施例可以藉由選定參數 而獲致較佳的驗證涵蓋率。熟習此藝者應知,可在驗證程 式中選擇性地加入控制流程驗證資訊之輸出,特別是用來 除錯之指令。或者,也可以於前實施例之驗證程式中加入 迴圈,以提高驗證涵蓋率。前述各種修改結果亦不脫離本 發明之範疇。 依照本發明之精神,以下另舉一實施例。本實施例與 前述實施例相似,不同之處在於副程式RECUR中於遞^ 跳躍前加入迴圈之分支指令,其程式碼例如為: RECUR CMP r9, #2 LDRGE r8, =RETURN3 STMGEFD r7!, {r8-rl〇} ADD r8, r9, rlO SUBGE r9, r9, #2 addge rlO, rlO, #1 3 CMP r8,#0 19 13053¾^ SUBGT r8, r8, #1 BGT %b3 CMP r9, #0 BGE RECUR RETURN3 CMP r9, #1 LDRGE r8, -RETURN2 STMGEFD r7!, {r8-rl0} ADD r8, r9, rlO SUBGE r9, r9, #1 2 CMP r8, #0 SUBGT r8, r8, #1 BGT %b2 CMP r9, #0 BGE RECUR RETURN2 CMP rlO, #1 LDRGE r8, =RETURN1 STMGEFD r7!, {r8-rl0} ADD r8, r9, rlO SUBGE rlO, rlO, #1 1 CMP r8, #0 SUBGT r8, r8, #1 BGT %bl CMP rlO, #0 BGE RECUR RETURN1 CMP rlO, #1 13053¾^ LDRGE Γ8, =RETURN0 STMGEFD r7!, {r8-rl0}
ADD r8, r9, rlO SUBGE Π0, rlO, #1 0 CMP r8,#〇 SUBGT r8, r8, #1 BGT %b0 CMP rlO, #〇 BGE recur
RETURNO NOP LDMFD r7!,{r8-rl0} MOV PC,r8 其中,「ADD r8,r9,rl〇」係將暫存器⑸與^❹之值 相加並且將其加總值存放於暫存器r8。「SUBGT作,比 =」係依據前面「CMP r8,#0」指令之判斷結果,若暫存 器r8之值大於〇則使暫存器r8之值減丨。「BGT 〇/〇m 係依據前面「CMP r8, #〇」指令之判斷結果,若暫存^ β之值大於〇則分支跳躍至標記「3」之位址。也就是說°, 在每次把暫存H ι:8〜flG之内容存放置堆疊中後,隨即利 用暫存II 1*8作為迴圈之賴H(初始值㈣·所決定)。 因此,在每次判斷是否遞迴執行副程式RECUR之前即執 仃了若干次分支指令’故可產生更多樣之分支跳躍狀況與 測試樣本(Pattern)以驗證分支指令預測機制(例如 BTB)。在 此繼續沿用前述實施例之參數(3與〇)以方便比較。因此, 依前所述,可透過分析驗證程式而獲得表3。 21 I3〇53235twf_d〇c 歷程=0, Not taken 4 3 6 6 歷程=1,Not taken 5 5 6 6 歷程=2, Not taken 3 5 2 2 歷程=3, Not taken 3 2 1 1 若假設本實施例所驗證之BTB預測機制中記錄每一 個分支指令之歷程(history)為2個位元,依此本實施例中
「BGT%b3」、「BGT%b2」、「BGT%bl」以及「BGT %b0」分支指令之所能產生之測試樣本被分析統計如表3 下半部所示。若將參數設定為4與0,依前所述,可透過 分析驗證程式而獲得表4。 表4是依照本發明另一實施例(驗證參數設為4、〇)中 BGT%b3」、「BGT%b2」、「BGT %bl」以及「BGT %b0」分之跳躍狀況分析表〇 時序 BGT %b3 BGT %b2 BGT %bl BGT %b0 1 ~~ Taken Taken Taken Not taken 2 Taken Taken Taken Not taken 3 ' Taken Not taken Not taken Not taken 4 Taken Taken Taken Taken 5 Not taken Not taken Not taken Taken 6 Taken Not taken Not taken Not taken 7 Taken Not taken Not taken Not taken 8 Taken Taken Taken Taken 9 Not taken Not taken Not taken Not taken 10 Taken Not taken Not taken Not taken 11 ^ Taken Not taken Not taken Not taken 12 Not taken Taken Taken Taken 13 Taken Taken Not taken Not taken 14 ~~~ Not taken Taken Not taken Not taken 15 ~~~ Not taken Not taken Not taken Not taken 16 Not taken Taken Taken Taken 17 Taken Taken Taken Not taken 18 ~~~~~ Not taken Not taken Not taken Taken 19 Not taken Taken Not taken Taken 20 ~~~ Not taken Not taken Taken Not taken 23 Ι3053^„ 21 Taken Not taken Not taken Not taken 22 Taken Not taken Not taken Taken 23 Not taken Taken Taken Not taken 24 Taken Not taken Not taken Not taken 25 Not taken Not taken Taken Taken 26 Not taken Taken Taken Not taken 27 Not taken Not taken Taken Not taken 28 Taken Not taken Not taken Not taken 29 Not taken Taken Taken Taken 30 Not taken Not taken Not taken Not taken 31 Taken Not taken Not taken Taken 32 Not taken Not taken Not taken Taken 33 Not taken Taken Not taken Not taken 34 Taken Taken Taken Taken 35 Taken Not taken Not taken Taken 36 Not taken Taken Taken Taken 37 Taken Not taken Taken Not taken 38 Not taken Not taken Not taken Not taken 39 Not taken Taken Taken Taken 40 Not taken Not taken Not taken Not taken 41 Taken Not taken Not taken Not taken 42 Not taken Not taken Not taken Not taken 43 Not taken Taken Not taken Taken 44 Taken Taken Taken Not taken 45 Taken Not taken Not taken Taken 46 Not taken Taken Taken Taken 47 Taken Not taken Taken Not taken 48 Not taken Not taken Not taken Not taken 49 Not taken Taken Taken Taken 50 Not taken Taken Not taken Not taken 51 Taken Taken Not taken Not taken 52 Not taken Taken Not taken Not taken 53 Not taken Not taken Taken Not taken 54 Taken Taken Taken Taken 55 Taken Taken Not taken Not taken 56 Taken Not taken Not taken Taken 57 Not taken Taken Taken Taken 58 Taken Not taken Not taken Not taken 59 Taken Not taken Not taken Not taken 60 Not taken Not taken Taken Taken
24 I3053^85twfdoc 61 62 63 64 65 66 67 68 ~69 70 71 72 73 74 75 76 77
Taken
Not taken
Not taken
Not taken
Taken
Not taken
Not taken
Taken
Not taken
Not taken
Taken
Taken
Not taken
Taken
Not taken
Not taken
Not taken
Taken
Not taken
Not taken
Taken
Not taken
Not taken
Taken
Taken
Taken
Not taken
Taken
Not taken
Not taken
Not taken
Taken
Taken
Not taken
Not taken
Taken
Not taken
Not taken
Not taken
Not taken
Taken
Not taken
Taken
Taken
Not taken
Taken
Taken
Taken
Not taken
Taken
Taken
Not taken
Not taken
Taken
Not taken
Not taken
Not taken
Taken
Not taken
Taken
Taken
Not taken
Taken
Taken
Taken
Not taken
Taken
Taken 78 Taken Taken Taken 79 Not taken Not taken Taken Not taken Not taken Taken Not taken Taken Not taken
歷程=2, Not taken j 歷程=3, Not takeiT[ _ ^比較表 3 與定參數而提供設計者可以蚊龍之㈣率(c〇verJ 驗證所需時間。例如,於本實施例中, ,〇時,驗證所需時間較少。然而可以從表 (3,0)無法涵蓋所有BTB分支指令賴軸之所有狀況 25 13053¾^ 如無法涵蓋BTB中當「BGT %b2」指令之歷程=3時為 Taken之狀況。而從表4中可以明顯看出所需之驗證時間 較長,但是可以達到良好之驗證涵蓋率,同時當中: 指令跳躍與否之狀況更為無序。 刀支 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作些許之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是依照本發明實施例所繪示的一種分支指令預測 機制之驗證方法的流程圖。 圖2是依照本發明較佳實施例中以邏輯上觀點所繪示 的一種驗證程式之程式執行過程之樹狀圖。 【主要元件符號說明】 S110〜S180 :依照本發明實施例所訴一種分支指令預 測機制之驗證方法的各步驟 201〜215 :以邏輯上觀點表示於遞迴程序中被呼叫之 驗證程式 26
Claims (1)
1305323 I3785twf.doc 十、申請專利範圍: 證-之驗證方法,用以驗 列步驟·· 令_機制’該驗證方法包括下 提供並執行—驗證程式,該驗證程式中 曰令,其中該分支指令係依照-條件而決 2·如申 驗證方法;包預測機制之 支指令預測機制的狀態之涵蓋率。 驗證方法項_之分支指令預測機制之 進行該條件之判斷; *’ 依據判斷該條件之結果以決 下一指令位址與該參數至—堆疊;=子該分支指令之 以及依據判_條件之結果^定是否轉該參數之值; 迴呼據判斷該條件之結果決定是否遞 5.如申請專利範圍第4項所述之 驗證方法,其中該驗證程式更包 ^令預測機制之 自該堆疊取回被儲存之該分支指令=步驟: 該參數;以及 之下一指令位址與 27 85twf.doc 依所取回之該分支指令之下一指人 、 叫該驗證程式之該分支指令之下—p:立址以返回别次呼 / ,丄▲士 伯$位址。 6.如申請專利範圍第1項所述 驗證方法,其中該分支指令預測機制; 器(BTB,Branch Target Buffer)。 勹刀克目私緩衝 7·-種可讀取記錄媒體’用叫存可執行於 的一驗證程式,其中該驗證程式用 $- 分支一 刀支才曰々,該分支指令係依照一 —遞迴(麵rsive)呼叫並執行該驗證程^件而决疋疋否以 8.如申請專利範圍第7項所述 中該驗證程式更包括下列指令:狀%取_媒體,其 該八ίίϊ少—參數’該參數用以蚊該驗證程式可驗證 X刀支才日·T預測機制的狀態之涵蓋率。 中該記錄媒體’其 中該所述之可讀取記錄媒體,其 進行該條件之判斷; 件之結果以決定是否儲存該分支 私令位址與該參數至一堆疊; 以及依據觸該條件之結果以決定是否調整該參數之值; 依據判斷該條件之結果以決定是否進行該分支指令。 28 13053¾ 85twf.doc 11. 如申請專利範圍第10項所述之可讀取記錄媒體, 其中該驗證程式更包括下列步驟: 自該堆疊取回被儲存之該分支指令之下一指令位址與 該參數;以及 依所取回之該分支指令之下一指令位址以返回前次呼 叫該驗證程式之該分支指令之下一指令位址。 12. 如申請專利範圍第7項所述之可讀取記錄媒體,其 中該分支指令預測機制係為一分支目標緩衝器(BTB, Branch Target Buffer)。 29
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US9785442B2 (en) | 2014-12-24 | 2017-10-10 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
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US10061583B2 (en) | 2014-12-24 | 2018-08-28 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10061589B2 (en) | 2014-12-24 | 2018-08-28 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10303525B2 (en) | 2014-12-24 | 2019-05-28 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10387158B2 (en) | 2014-12-24 | 2019-08-20 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
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WO2012023185A1 (ja) * | 2010-08-18 | 2012-02-23 | 富士通株式会社 | 試験方法、演算処理装置、試験プログラム、試験プログラム生成方法、試験プログラム生成装置、及び試験プログラム生成プログラム |
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CN102156636B (zh) * | 2011-04-28 | 2013-05-01 | 北京北大众志微系统科技有限责任公司 | 一种实现值关联间接跳转预测的装置 |
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US9785442B2 (en) | 2014-12-24 | 2017-10-10 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
TWI610230B (zh) * | 2014-12-24 | 2018-01-01 | 英特爾股份有限公司 | 用於資料推測執行的系統、設備及方法 |
TWI610232B (zh) * | 2014-12-24 | 2018-01-01 | 英特爾股份有限公司 | 用於資料預測執行之系統、裝置及方法 |
US10061583B2 (en) | 2014-12-24 | 2018-08-28 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10061589B2 (en) | 2014-12-24 | 2018-08-28 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10303525B2 (en) | 2014-12-24 | 2019-05-28 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10387156B2 (en) | 2014-12-24 | 2019-08-20 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
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US10942744B2 (en) | 2014-12-24 | 2021-03-09 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
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