1305025 09335twfl.doc/006 9^-4 A9 九、發明說明： 【發明所屬技術領域】 本發明是有關於一種半導體製程，且特別是有關於一 種超薄閘極介電層(Ultra-thin Gate Dielectric Layer)之製造 方法。 【先前技術】 在積體電路蓬勃發展的今日，元件縮小化與積集化是 必然之趨勢，也是各界積極發展的重要課題。當元件尺寸 逐漸縮小，元件之閘極寬度縮小，而使得閘極介電層也隨 著金氧半導體製程技術的發展而逐漸縮小。以一般半導體 製程而言，當閘極寬度爲〇.25微米時，閘極介電層之厚度 爲4〇埃至50埃左右，當閘極寬度爲〇」微米時，閘極介 電層之厚度爲15埃至2〇埃左右。 而在降低閘極介電層厚度之同時，需要考慮製造中的 可行性及可靠度之問題’由於閘極介電層厚度的降低會使 得電子電洞的穿透機率增加，所以會產生較大的閘極漏電 流，其漏電流之大小隨著減少之阻障厚度成指數增加，以 氣化矽材質作爲閘極介電層爲例，當氧化矽厚度爲16埃， 其所產生之閘極漏電流與閘極工作時所產生之電流相當。 此外’在形成閘極介電層後，接著係製作包括摻雜多 晶石夕層與多晶砂化金屬層之閘極結構。其中，摻雜多晶砂 層在進行多晶矽之摻雜時，若閘極介電層本身之材質不夠 緻密，則閘極介電層之結構會因摻雜離子散射之緣故而受 到破壞。使得當閘極在工作時，在未達到啓始電壓之情況 1305025 96-4-19 09335twfl .doc/006 下，電流容易經由摻雜多晶矽層中之摻質滲入閘極介電層 之路徑而產生漏電流’此種情形對於超薄閘極介電層所產 生之影響更趨明顯。 在習知製程中有許多用來改善上述閘極介電層問題之 方法，例如使用其他介電常數高之介電材料或利用不同之 製作方法製作之氧化層。但是這些方法仍然需要面臨其製 程之種種問題。而且，如果閘極介電餍之材質採用氧化矽， 就必須採用厚度在100埃以下之超薄閘極氧化層，在如此 薄的厚度下，要製造高品質之氧化層，實在非常不容易。 因此’尚品質的超薄閘極介電層即成爲次微米製程技術中 最重要的課題之一。 【發明內容】 有鑑於此，本發明的一主要目的就是在提供一種超薄 閘極介電層之製造方法，可以製作品質良好、均勻性佳之 超薄閘極介電層。 本發明提供一種超薄聞極介電層之製造方法，此方法 包括下列步驟：將基底設置於一反應室中後，於反應室中 通入一第一反應氣體、一第二反應氣體與一稀釋氣體。然 後’進行一即時蒸汽產生製程，以於基底上形成一氧化層。 在上述方法中即時蒸汽產生製程之反應壓力爲6托耳 (Torr)至Μ托耳(T〇rr)左右，反應溫度爲8〇〇°C〜1200^左 右’而且於基底上形成氧化層之後，更包括進行一回火製 程。 此外，第一反應氣體爲氧氣，第二反應氣體爲氫氣或 1305025 09335twfl.doc/006 96-4-19 氘氣。其中，氫氣(H2)/氧氣（〇2)或氘氣(D2)/氧氣（〇2)之組 成比例如是0.1%〜40%左右，其總流量爲1 slm至40 slm 左右。稀釋氣體爲氮氣，其流量爲1 slm至50 slm左右。 本發明所揭露之超薄閘極介電層之形成方法係採用即 時蒸汽產生製程。其中，以氧氣、氫氣（氘氣）爲反應氣體 源，並加入一稀釋氣體。當反應氣體源（氧氣+氫氣(或氘氣)) 加入至反應室中時，氧氣與氫氣（或氘氣）先經過熱製程而 形成水蒸汽(h2o或D20)，使矽基底暴露在水蒸汽(h2o或 d2o)之環境中，然後繼續進行熱製程使水蒸汽(h2o或d2o) 與矽基底表面產生反應，而生成氧化矽。稀釋氣體則可以 稀釋反應氣體中之氧基濃度，使得氧基能夠更均勻地接觸 矽基底之表面，而形成均勻的氧化矽層。而且，在反應氣 體中加入稀釋氣體之情況下，由於稀釋氣體並不會改變氧 基的品質，因此不會影響氧化矽之沈積速率。 而且，利用氘氣取代氫氣製作超薄閘極介電層時，由 於在電應力下矽-氘鍵較矽•氫鍵穩定而不容易破壞，因此 在定電流應力下可以減少電子陷入，於是以氘氣爲反應氣 體所得到之超薄閘極介電層具有較良好的性質。此外，在 形成超薄閘極介電層後，可進行一回火製程使閘極介電層 更爲緻密。 因此，利用本發明之方法可以形成較緻密且均勻性 佳、品質量良好之超薄閘極介電層，故可以降低習知使用 超薄閘介電層時可能產生之漏電流的情形，亦可用於克服 其用於更小寬度之閘極製程時所遭遇到之困難。 1305025 09335twfl.doc/006 96-4-19 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下。 【實施方式】 本發明係採用即時蒸汽產生（In-Situ Steam Generation，ISSG)製程形成超薄閘極介電層。在本發明中 係以氧氣、氫氣（氘氣）爲反應氣體源，並加入一稀釋氣體。 當反應氣體源(氧氣+氫氣（或氣氣）)加入至反應室中時’氧 氣與氫氣（或気氣）先經過熱製程而形成水蒸汽（H2◦或 D20)，使矽基底暴露在水蒸汽(H20或D20)之環境中’然 後繼續進行熱製程使水蒸汽(H2〇或D2〇)與矽基底表面產 生反應，而生成氧化矽。稀釋氣體可以稀釋反應氣體中之 氧基(Oxygen Radical)濃度，使得氧基能夠更均勻地接觸矽 基底之表面，而形成均勻的氧化矽層。而且，在反應氣體 中加入稀釋氣體之情況下，由於稀釋氣體並不會改變氧基 的品質，因此不會影響氧化矽之沈積速率。 第1圖爲繪示依照本發明較佳實施例所揭露之用於製 造超薄閘極介電層之裝置剖面圖。 請參照第1圖，提供一半導體矽基底100，在進行形 成閘極介電層的步驟之前，會進行一道清洗的步驟。此清 洗步驟目的是在去除矽基底100表面上的雜質，以及因矽 基底100暴露在含氧環境所自然生成的原生氧化層(Native Oxide)。此清洗步驟係爲習知的製程中之清洗步驟，在此 不再贅述。進行清洗步驟以後，將矽基底1〇〇放置於可進 1305025 96-4-19 09335twfl.doc/006 行即時蒸汽產生之反應室102中。 然後’通入反應氣體(氧氣）1〇4、反應氣體(氫氣或氘氣） 106與一稀釋氣體108至反應室1〇2中，在製程反應壓力 例如是6托耳(Torr)至I4托耳（T〇rr)左右，反應溫度例如是 80(TC〜1200°C左右之狀態下，進行氧化反應以於矽基底 100上形成超薄閘極介電層。 反應氣體104例如是氧氣（〇2)，反應氣體1〇6例如是 氫氣(H2)或氘氣(D2)。在本實施例中氫氣(h2)/氧氣(〇2)或氘 氣(D2)/氧氣（02)之組成比例如是0.1%〜4〇%左右，其總流 量例如是lslm至40slm。稀釋氣體1〇4例如是氮氣，其流 量例如是lslm至50slm。 當反應氣體104與反應氣體106加入至反應室中時， 反應氣體104與反應氣體106先經過熱製程而形成水蒸汽 (H20或D20)，使矽基底100暴露在水蒸汽(h2o或d2o)之 環境中，然後繼續進行熱製程使水蒸汽(H2〇或d2o)與矽 基底100表面產生反應，而生成氧化矽。 當反應氣體爲氫氣(H2)/氧氣(〇2)時，其反應式如下：1305025 09335twfl.doc/006 9^-4 A9 IX. DESCRIPTION OF THE INVENTION: 1. Field of the Invention This invention relates to a semiconductor process, and more particularly to an ultrathin gate dielectric (Ultra-thin Gate Dielectric) Layer) manufacturing method. [Prior Art] In today's booming development of integrated circuits, component shrinkage and accumulation are inevitable trends, and they are also important topics for active development. As the component size shrinks, the gate width of the device shrinks, and the gate dielectric layer shrinks as the MOS process technology evolves. In the case of a general semiconductor process, when the gate width is 〇.25 μm, the thickness of the gate dielectric layer is about 4 〇 to 50 Å, and when the gate width is 〇 微米, the gate dielectric layer The thickness is about 15 angstroms to 2 angstroms. While reducing the thickness of the gate dielectric layer, it is necessary to consider the feasibility and reliability of the manufacturing process. 'The decrease in the thickness of the gate dielectric layer will increase the penetration probability of the electron hole, so it will be larger. The gate leakage current, the magnitude of the leakage current increases exponentially with the reduced barrier thickness. Taking the vaporized germanium material as the gate dielectric layer, for example, when the thickness of the germanium oxide is 16 angstroms, the gate is generated. The leakage current is equivalent to the current generated when the gate is operating. Further, after forming the gate dielectric layer, a gate structure including a doped polycrystalline layer and a polycrystalline sanded metal layer is formed. Wherein, when the doped polycrystalline sand layer is doped with polycrystalline germanium, if the material of the gate dielectric layer itself is not dense enough, the structure of the gate dielectric layer is destroyed by the doping ion scattering. Therefore, when the gate is in operation, under the condition that the starting voltage is not reached, 1305025 96-4-19 09335 twfl .doc/006, the current is easily generated by the path of the dopant in the doped polysilicon layer penetrating into the gate dielectric layer. Leakage current 'The effect of this situation on the ultra-thin gate dielectric layer is more pronounced. There are a number of methods for improving the above-mentioned gate dielectric layer problems in conventional processes, such as using other dielectric materials having a high dielectric constant or oxide layers formed by different fabrication methods. However, these methods still need to face various problems in their processes. Moreover, if the material of the gate dielectric is made of yttrium oxide, it is necessary to use an ultra-thin gate oxide layer having a thickness of 100 angstroms or less. At such a thin thickness, it is very difficult to manufacture a high-quality oxide layer. Therefore, the ultra-thin gate dielectric layer of the quality is one of the most important topics in the sub-micron process technology. SUMMARY OF THE INVENTION In view of the above, it is a primary object of the present invention to provide a method for fabricating an ultrathin gate dielectric layer that can produce an ultrathin gate dielectric layer of good quality and uniformity. The invention provides a method for manufacturing an ultra-thin sinter dielectric layer, the method comprising the steps of: after placing a substrate in a reaction chamber, introducing a first reaction gas, a second reaction gas and a reaction chamber into the reaction chamber; Dilution gas. An instant steam generation process is then performed to form an oxide layer on the substrate. In the above method, the reaction pressure of the instant steam generation process is from about 6 Torr to about 〇rr (T〇rr), and the reaction temperature is from about 8 ° C to about 1200 ° and the oxide layer is formed on the substrate. It also includes a tempering process. Further, the first reaction gas is oxygen, and the second reaction gas is hydrogen or 1305025 09335 twfl.doc/006 96-4-19 helium. Among them, the composition ratio of hydrogen (H2) / oxygen (? 2) or helium (D2) / oxygen (? 2) is, for example, about 0.1% to 40%, and the total flow rate is about 1 slm to 40 slm. The dilution gas is nitrogen and the flow rate is from about 1 slm to about 50 slm. The method for forming the ultrathin gate dielectric layer disclosed in the present invention employs an instant steam generation process. Among them, oxygen and hydrogen (helium) are used as a reaction gas source, and a diluent gas is added. When a source of reactive gas (oxygen + hydrogen (or helium)) is added to the reaction chamber, oxygen and hydrogen (or helium) are first subjected to a thermal process to form water vapor (h2o or D20), exposing the crucible substrate to water vapor. In the environment of (h2o or d2o), the thermal process is then continued to cause water vapor (h2o or d2o) to react with the surface of the crucible substrate to form antimony oxide. The diluent gas can dilute the concentration of the oxygen in the reaction gas so that the oxy group can more uniformly contact the surface of the ruthenium substrate to form a uniform ruthenium oxide layer. Further, in the case where a diluent gas is added to the reaction gas, since the dilution gas does not change the quality of the oxygen group, the deposition rate of the cerium oxide is not affected. Moreover, when the ultrathin gate dielectric layer is formed by using helium instead of hydrogen, since the 矽-氘 bond is less susceptible to destruction under the electrical stress than the hydrogen bond, the electron trapping can be reduced under constant current stress. The ultrathin gate dielectric layer obtained by the helium gas as the reaction gas has better properties. In addition, after the formation of the ultrathin gate dielectric layer, a tempering process can be performed to make the gate dielectric layer more dense. Therefore, the ultra-thin gate dielectric layer which is denser, more uniform, and of good quality can be formed by the method of the invention, so that the leakage current which may be generated when the ultra-thin gate dielectric layer is conventionally used can be reduced. It can be used to overcome the difficulties encountered in its gate process for smaller widths. The above and other objects, features, and advantages of the present invention will become more apparent and understood. as follows. [Embodiment] The present invention forms an ultrathin gate dielectric layer by an In-Situ Steam Generation (ISSG) process. In the present invention, oxygen, hydrogen (helium) is used as a reaction gas source, and a diluent gas is added. When a source of reactive gas (oxygen + hydrogen (or gas)) is added to the reaction chamber, 'oxygen and hydrogen (or helium) are first subjected to a thermal process to form water vapor (H2◦ or D20), exposing the crucible substrate to water. In the environment of steam (H20 or D20) 'then continue the thermal process to react water vapor (H2〇 or D2〇) with the surface of the crucible substrate to form antimony oxide. The diluent gas can dilute the Oxygen Radical concentration in the reaction gas so that the oxy group can more uniformly contact the surface of the ruthenium substrate to form a uniform ruthenium oxide layer. Further, in the case where a diluent gas is added to the reaction gas, since the dilution gas does not change the quality of the oxy group, the deposition rate of cerium oxide is not affected. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing an apparatus for fabricating an ultrathin gate dielectric layer in accordance with a preferred embodiment of the present invention. Referring to Figure 1, a semiconductor germanium substrate 100 is provided which is subjected to a cleaning step prior to the step of forming the gate dielectric layer. The cleaning step is intended to remove impurities on the surface of the ruthenium substrate 100, as well as the native Oxide naturally formed by exposure of the ruthenium substrate 100 to an oxygen-containing environment. This cleaning step is a washing step in a conventional process and will not be described herein. After the cleaning step, the crucible substrate 1 is placed in a reaction chamber 102 that can be immediately steam generated by 1305025 96-4-19 09335 twfl.doc/006. Then, a reaction gas (oxygen) 1〇4, a reaction gas (hydrogen or helium) 106 and a diluent gas 108 are introduced into the reaction chamber 1〇2, and the reaction pressure in the process is, for example, 6 torr (Torr) to I4 torr. The reaction temperature is, for example, 80 (about TC to 1200 ° C), and an oxidation reaction is performed to form an ultrathin gate dielectric layer on the ruthenium substrate 100. The reaction gas 104 is, for example, oxygen (〇). 2), the reaction gas 1〇6 is, for example, hydrogen (H2) or helium (D2). In this embodiment, the composition ratio of hydrogen (h2)/oxygen (〇2) or helium (D2)/oxygen (02) For example, about 0.1% to about 4%, the total flow rate is, for example, lslm to 40 slm. The diluent gas 1〇4 is, for example, nitrogen gas, and the flow rate thereof is, for example, lslm to 50 slm. When the reaction gas 104 and the reaction gas 106 are added to the reaction chamber, The reaction gas 104 and the reaction gas 106 are first subjected to a thermal process to form water vapor (H20 or D20), exposing the crucible substrate 100 to the environment of water vapor (h2o or d2o), and then continuing the thermal process to make the water vapor (H2 or D2o) reacts with the surface of the ruthenium substrate 100 to form ruthenium oxide. When the reaction gas is hydrogen (H2) / oxygen (〇2) Which reaction is as follows:
Η2+〇2~> 20H η2+οη—η2ο+η ο2+η-^οη+ο Η2+0—ΟΗ+ΗΗ2+〇2~> 20H η2+οη-η2ο+η ο2+η-^οη+ο Η2+0—ΟΗ+Η
當反應氣體爲氘氣(D2)/氧氣(〇2)時，其反應式如下： 20DWhen the reaction gas is helium (D2) / oxygen (〇2), the reaction formula is as follows: 20D
D2+OD—D20+D 1305025 09335twfl.doc/006 96-4-19D2+OD—D20+D 1305025 09335twfl.doc/006 96-4-19
〇2+D~^· OD+O〇2+D~^· OD+O
D2+0—OD+D 而且，在混合之反應氣體104與106中加入稀釋氣體 108，可以稀釋混合之反應氣體104與106中的氧基濃度， 使得氧基(Oxygen Radi cal)能夠更均句地接觸矽基底1〇〇之 表面，而形成均勻的氧化矽層。而且，在混合之反應氣體 104與106中加入稀釋氣體108之情況下，由於稀釋氣體 並不會改變氧基的品質，因此不會影響氧化矽之沈積速率。 依照本發明實施例所述，本發明所揭露之超薄閘極介 電層之形成方法係採用即時蒸汽產生製程。其中，以氧氣、 氫氣（氘氣）爲反應氣體源，並加入一稀釋氣體。當反應氣 體源(氧氣+氫氣(或気氣))加入至反應室中時’氧氣與氫氣 (或氘氣）先經過熱製程而形成水蒸汽(H2〇或d2o) ’使矽基 底暴露在水蒸汽(h2o或d2o)之環境中，然後繼續進行熱 製程使水蒸汽(h2o或D20)與矽基底表面產生反應’而生 成氧化矽。稀釋氣體則可以稀釋反應氣體中之氧基濃度’ 使得氧基能夠更均勻地接觸矽基底之表面，而形成均与的 氧化砍層。而且，在反應氣體中加入稀釋氣體之情況下’ 由於稀釋氣體並不會改變氧基的品質’因此不會影響氧化 矽之沈積速率。 而且，在上述實施例中，利用氘氣取代氫氣製作超薄 閘極介電層時，由於在電應力下矽-氘（Si-D Bond)鍵較砂_ 氦鍵（Si-H Bond)穩定而不容易破壞，因此在定電流應力下 可以減少電子陷入，於是以気氣爲反應氣體所得到之超薄 10 1305025 09335twfl.doc/006 %_4.19 閘極介電層具有較良好的性質。此外，在形成超薄閘極介 電層後，可進行一回火製程使閘極介電層更爲緻密。而且， 在形成超薄閘極介電層後，可進行一回火製程使閘極介電 層更爲緻密。 利用本發明之方法可以形成較緻密且均勻性佳、品質 量良好之超薄閘極介電層，故可以降低習知使用超薄閘介 電層時可能產生之漏電流的情形，亦可用於克服其用於更 小寬度之閘極製程時所遭遇到之困難。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 第1圖爲繪示依照本發明較佳實施例所揭露之用於製 迤超薄閘極介電層之裝置剖面圖。 【主要元件符號說明】 100 :基底 102 :反應室 104、106 :反應氣體 108 :稀釋氣體D2+0-OD+D Moreover, by adding a diluent gas 108 to the mixed reaction gases 104 and 106, the concentration of the oxygen in the mixed reaction gases 104 and 106 can be diluted, so that the oxy group (Oxygen Radi cal) can be more uniform. The ground is contacted with the surface of the substrate 1 to form a uniform layer of tantalum oxide. Further, in the case where the diluent gas 108 is added to the mixed reaction gases 104 and 106, since the dilution gas does not change the quality of the oxy group, the deposition rate of cerium oxide is not affected. According to an embodiment of the invention, the method for forming the ultrathin gate dielectric layer disclosed in the present invention adopts an instant steam generation process. Among them, oxygen and hydrogen (helium) are used as a reaction gas source, and a diluent gas is added. When a source of reactive gas (oxygen + hydrogen (or helium)) is added to the reaction chamber, 'oxygen and hydrogen (or helium) are first subjected to a hot process to form water vapor (H2〇 or d2o)' to expose the crucible substrate to water. In the environment of steam (h2o or d2o), the thermal process is then continued to cause water vapor (h2o or D20) to react with the surface of the crucible substrate to form cerium oxide. The diluent gas can then dilute the oxygen concentration in the reaction gas so that the oxy group can more uniformly contact the surface of the ruthenium substrate to form a uniform oxidized layer. Further, in the case where a diluent gas is added to the reaction gas, 'the dilution gas does not change the quality of the oxy group' and thus does not affect the deposition rate of ruthenium oxide. Moreover, in the above embodiment, when the ultrathin gate dielectric layer is formed by using helium instead of hydrogen, the Si-D bond is more stable than the Si-H bond under electrical stress. It is not easy to break, so it can reduce electron trapping under constant current stress, so the ultra-thin 10 1305025 09335twfl.doc/006 %_4.19 gate dielectric layer obtained by helium gas has better properties. In addition, after forming the ultrathin gate dielectric layer, a tempering process can be performed to make the gate dielectric layer more dense. Moreover, after forming the ultrathin gate dielectric layer, a tempering process can be performed to make the gate dielectric layer more dense. By using the method of the invention, an ultra-thin gate dielectric layer which is denser, more uniform and of good quality can be formed, so that the leakage current which may be generated when the ultra-thin gate dielectric layer is conventionally used can be reduced, and can also be used for Overcoming the difficulties encountered in its gate process for smaller widths. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing an apparatus for fabricating an ultrathin gate dielectric layer in accordance with a preferred embodiment of the present invention. [Description of main component symbols] 100: substrate 102: reaction chamber 104, 106: reaction gas 108: diluent gas