1304985 P950034 19579twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明s有關於m _存方法及使用該 單元’且特別是有關於-種用於記憶體單元之資料^ 法及使用該方法之記憶體單元。 子方 【先前技術】 由於現今科技日新月異，記憶體為了因應大量資 儲存’進而發展為朝向容量更大、速度更快、壽命更長、 更省電之趨勢。一般來說，容量為數百M(百萬位元 megabytes)的記憶體已逐漸不敷所求，已邁向容量為數g (十億位元組，gigabytes)或是容量為數百G之記憶體， 但南谷量之特性容易導致記憶體儲存資料之電壓分佈範圍 過大。於是，習知技術產生兩項缺失，第一，若要加大各 狀態之間（例如第一狀態為邏輯位準1與第二狀態為邏輯 位準0 )的感測窗（sensing window)以使得感測效果提升， 則必須增加各狀態之間的寫入臨界電壓差（pr〇graming threshold voltage difference)，而導致耗電及壽命減少。第 二，若要減少各狀態之間的寫入臨界電壓差來增加記憶體 使用奇命及降低耗電，則狀態之間的感測窗則會因此而減 少，而導致分辨各狀態間之感測動作不易進行。以下將使 用圖1及圖2表示並配合文字說明。 圖1描繪習知之記憶體單元資料儲存操作之臨界電壓 分佈圖。橫軸表示臨界電壓’縱軸表示位元數。臨界電壓 刀佈曲線101及㉞界電壓分佈曲線1 〇2代表1 μ記憶體來 19579twf.doc/〇〇6 1304985 P950034 使資料儲存至苐一狀態與第二狀態之分佈曲線，臨界電壓 分佈曲線103及臨界電壓曲線104代表ig記憶體使資料 儲存至第一狀態與第二狀態之分佈曲線。SW11代表兩位 元記憶體之兩狀態間的感測窗，而SW12及SW13代表1M 及1G記憶體兩狀態間的感測窗。DVtll代表寫入後兩位 元5己憶體之兩狀間之臨界電壓差值，D Vt 12及DVt 13分 別代表寫入後1M記憶體之兩狀態間之臨界電壓差值及寫 入後1G記憶體之兩狀態間之臨界電壓差值。由圖丨可知， 曲線103之分佈值D2大於曲線101之分佈值1)1，而兩位 兀記憶體則只有一臨界電壓點，故分佈值為零。圖丨繪示 ^每一位元具有相同寫入臨界電壓差值之情形。一般來 况二感測窗定義為介於低臨界電壓分佈之高界限或高臨界 電^分佈之低界限之臨界電壓差，所以兩位元記憶體、1M §己憶體、1G記憶體之寫入臨界電壓差分別為vtll、Vtl2、 Vtl3 ’可得到感測窗電壓差與寫入臨界電壓差之關係分別 為 SWll=DVtll、swi2= ( DVtl2-Dl ) 、SW13= fDVtl3_D2) ’若要維持各記憶體之寫入臨界電壓差相 則導致高容量之記憶體的感測窗SW13變小，使得高 I量之記憶體的兩狀態間之判別不易。 圖2描繪另一習知之記憶體單元資料儲存操作之臨界 電壓分佈圖。橫軸表示臨界電壓，縱軸表示位元數。臨界 電麗分佈曲線201及臨界電壓分佈曲線202代表1M記憶 體來使資料儲存至第一狀態與第二狀態之分佈曲線，臨界 電壓分佈曲線203及臨界電壓分佈曲線205代表1G記憶 1304985 P950034 19579twf.doc/006 體使負料儲存弟一狀悲與第二狀態之分佈曲線，而臨界電 壓分佈曲線204、206則代表1G記憶體之部分位元於兩狀 恶間之分佈曲線。兩位元、1M、1G記憶體之感測窗分別 為SW11、SW12及SW13，兩位元記憶體、iM記憶體、 1G §己憶體之兩狀邊間之寫入臨界電壓差分別為〇 vt21、 DVt22、DVt23。感測窗與寫入臨界電壓差之關係分別為 SW21 二DVt21、SW22二（DVt22-Dl)、SW23=(〇Vt23-D2)， 若需維持各記憶體之感測窗相同，則將導致高容量之記憶 體兩狀恶間之寫入臨界電壓差DVt23變大，使得壽命減少 及耗電。 【發明内容】 本發明的目的就是在提供一種用於記憶體單元之資 料儲存方法，可改善記憶體之週期邊際（cycling margin )、 延長記憶體使用年限、及適於應用在多重位準元件 (multilevel cell)之操作窗（〇Perating window)。 本發明的再一目的是提供一種記憶體單元，可延長記 憶體使用年限、改善記憶體之週期邊際、及適於應用在多 重位準元件之操作窗。 本發明提出一種用於記憶體單元之資料儲存方法’包 含以下步驟：首先，分割一記憶體單元為多個小記憶體群； 接著，定義多個小纪憶體君夢之臨界電麗分佈區域；其次’ 依據各個小記憶體群之臨界電壓分佈區域來定義各個小記 憶體群之多個寫入驗證臨界電壓及各個小記憶體群之多個 參考偵測值；其後，使用小§己憶體群來儲存一資料。 1304985 P950034 19579twf.doc/006 一本=再提出—觀㈣單元，其使用 群，然後，依據各個小;記憶體單元 個小年情㈣夕夕」 群界電壓區域來決定各 存H—夕"寫人驗證輕及多個參如貞測值來儲 本發明因採用將記憶體單元分 群，再以小記憶體群之臨界 ，壓及參考_值之結構，因此可改 邊際、延長記憶體使用年限 ’ 〜月 之操作窗。1更用年限、及適於應用在多重位準元件 易懂為Τ其他目的、特徵和優點能更明顯 明如下。、沾㈣例’並配合所關式，作詳細說 【實施方式】 ^ 11巾將參則頂來朗本發0狀難實施例，i中 =本項技術領域中之任何一種繼=， 皆可適用於本發明例如可抹除 (EPROM )、電子开社队 隹。貝圯U體 CEEPROM 、& 除可程式化唯讀記憶體 動恶Ik機存取記憶體（DRAM)、靜能 機存取記憶體（SRAM)等。 圖3描繪本發明實施例快閃記憶體單元3〇〇之電路方 塊圖。快閃記憶體單元300例如容量為1G (十億位元組， 1304985 P950034 19579twf.doc/006 gega byte)，分割為小記憶體群301〜304容量各為1M。 圖4描繪本發明實施例之用於快閃記憶體單元之資料儲存 方法的臨界電壓分佈圖，橫轴表示臨界電壓，縱軸表示位 元數。請同時參考圖3及圖4，小記憶體群301〜304對應 至臨界電壓分佈曲線401〜404,則快閃記憶體單元300之 原來未分割的臨界電壓分佈曲線40作為對照之用。由圖4 可知，臨界電壓分佈曲線40的臨界電壓分佈區域之分佈值 D3大於臨界電壓分佈曲線401〜404之個別的臨界電壓分 佈區域之分佈值D4，藉由改變分佈差值（D3-D4)，可用 以加大感測窗與及減少寫入臨界電壓差。定義分佈曲線 401〜404之高界限可參考點I_base，使偵測出曲線401之 高界限小於臨界電壓B1、分佈曲線402之高界限介於臨界 電壓B1〜B2間、分佈曲線403之高界限介於臨界電壓B2 〜B3間、分佈曲線404之高界限介於臨界電壓B3〜B4 間，而快閃記憶體單元300之原來未分割的高界限則位於 臨界電壓B4〜B5間作為對照之用。 本發明實施例不限於將記憶體單元分割為4個小記憶 體群，可視其需要分割為任意數量之小記憶體群，例如可 將容量為1G之記憶體單元分割為1百萬個小記憶體群， 而每個記憶體群具有1K位元組，或將容量為1G之記憶體 單元分割為16千條字元線，各條字元線具有64千位元組。 本發明藉由分割記憶體單元來得到多個小記憶體群，可儲 存多個小記憶體群之臨界電壓分佈資訊至一外部記憶體或 一緩衝記憶體，使臨界電壓分佈資訊紀錄多個小記憶體之 1304985 P950034 19579twf.doc/006 分佈區域，並可使臨界電壓分佈區域之分佈值降低來增加 儲存效果，但本發明不限於分割為具有相同容量之小記憶 體群，可視其需求分割為不同容量之小記憶體群。同時在 =存資料時，本發明並無需考慮原來記憶體單元之未分割 前的高界限，只需考慮分割後各記憶體群之高界限，可使 得，態間之寫入臨界電壓差的規劃更有彈性，而熟知技藝 者當知，本發明不限於定義高界限，可使用定義曲線之其 丨他特徵點例如低界限、或中間界限值等來取代之。 =圖5描繪本發明實施例之用於快閃記憶體單元之資料 儲存方法的另一臨界電壓分佈圖，橫轴表示臨界電壓，縱 軸^不位元數，橫軸表示臨界電壓，縱軸表示位元數。請 同=參考圖3及圖5,圖3之小記憶體群301〜3〇4在另-〜^下為^^界電壓分佈曲線41丨〜。例如分佈曲線4〇1 為貝料儲存第一狀態邏輯位準1，分佈曲線411〜414 :=料儲存第—狀態邏輯位準〇，因此，該快閃記憶體單 =兩位準圯憶體。分佈曲線401〜404之臨界電壓分佈 二1可用以定義分佈曲線411〜414之驗證臨界電壓。分佈 曲線401之古K a y 电&刀种 之驗證臨及α義小於B1，則對應之分佈曲線411 介於1堡疋義為PV1，分佈曲線402之高界限定義 B1與於間’則對應之分佈曲線412驗證臨 驗證〖品界電壓PV3、PV4可依此類推。 儲存方、、^田1會本發明實施例之用於快閃記憶體單元之資料 軸表示位的又^界電壓分佈圖，橫抽表示臨界電壓，縱 立元數。為清楚表示各曲線之差異，將臨界電壓分 101304985 P950034 19579twf.doc/006 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to the method of m_storage and the use of the unit', and particularly relates to a data method for a memory unit and A memory unit using this method. Sub-Phase [Prior Art] Due to the rapid development of today's technology, memory has evolved into a larger capacity, faster, longer life, and more power-saving trend in response to large-scale storage. In general, memory with a capacity of hundreds of M (megabytes) has gradually become insufficient, and has moved to a memory of several g (gigabytes) or a capacity of hundreds of G. Body, but the nature of the South Valley is likely to cause the voltage distribution of the memory storage data to be too large. Thus, the prior art technique produces two deficiencies. First, to increase the sensing window between states (eg, the first state is a logic level 1 and the second state is a logic level 0). In order to improve the sensing effect, it is necessary to increase the pr〇graming threshold voltage difference between the states, resulting in power consumption and life reduction. Second, if the write threshold voltage difference between states is to be reduced to increase the memory usage and reduce the power consumption, the sensing window between the states will be reduced, resulting in a sense of the state. The measurement action is not easy to perform. The following description will be made using FIG. 1 and FIG. Figure 1 depicts a threshold voltage distribution diagram for a conventional memory cell data storage operation. The horizontal axis represents the threshold voltage and the vertical axis represents the number of bits. The critical voltage knives curve 101 and 34 boundary voltage distribution curve 1 〇2 represents 1 μ memory to 19579twf.doc/〇〇6 1304985 P950034 The data is stored to the distribution of the first state and the second state, the critical voltage distribution curve 103 And the threshold voltage curve 104 represents a distribution curve in which the ig memory stores data to the first state and the second state. SW11 represents the sensing window between the two states of the two-dimensional memory, while SW12 and SW13 represent the sensing windows between the two states of the 1M and 1G memory. DVtll represents the threshold voltage difference between the two digits of the two-bit memory. D Vt 12 and DVt 13 represent the threshold voltage difference between the two states of the 1M memory after writing and 1G after writing. The threshold voltage difference between the two states of the memory. As can be seen from the figure, the distribution value D2 of the curve 103 is larger than the distribution value 1) 1 of the curve 101, and the two-dimensional memory has only one critical voltage point, so the distribution value is zero. Figure 丨 shows the case where each bit has the same write threshold voltage difference. Generally, the second sensing window is defined as the threshold voltage difference between the high limit of the low threshold voltage distribution or the low limit of the high critical voltage distribution, so the writing of the two-dimensional memory, the 1M § memory, and the 1G memory The threshold voltage difference is vtll, Vtl2, Vtl3 ' respectively. The relationship between the sensing window voltage difference and the write threshold voltage difference is SWll=DVtll, swi2=( DVtl2-Dl ), SW13= fDVtl3_D2) 'To maintain each The writing of the threshold voltage difference phase of the memory causes the sensing window SW13 of the high-capacity memory to become small, so that the discrimination between the two states of the high-I-memory memory is not easy. Figure 2 depicts a threshold voltage profile of another conventional memory cell data storage operation. The horizontal axis represents the threshold voltage and the vertical axis represents the number of bits. The critical electric distribution curve 201 and the threshold voltage distribution curve 202 represent 1M memory to store the data to the distribution curve of the first state and the second state, and the threshold voltage distribution curve 203 and the threshold voltage distribution curve 205 represent 1G memory 1304985 P950034 19579twf. The doc/006 body allows the negative material to store the distribution curve of the sorrow and the second state, while the threshold voltage distribution curves 204 and 206 represent the distribution curve of the partial bits of the 1G memory between the two morphologies. The sensing windows of the two-element, 1M, and 1G memory are SW11, SW12, and SW13, respectively. The write threshold voltage difference between the two-dimensional memory, iM memory, and 1G § memory is 〇 Vt21, DVt22, DVt23. The relationship between the sensing window and the write threshold voltage difference is SW21 two DVt21, SW22 two (DVt22-Dl), and SW23=(〇Vt23-D2). If the sensing windows of each memory are to be the same, it will lead to high. The write threshold voltage difference DVt23 between the two-shaped memory of the capacity becomes larger, resulting in a decrease in lifetime and power consumption. SUMMARY OF THE INVENTION It is an object of the present invention to provide a data storage method for a memory cell that can improve the cycle margin of the memory, extend the useful life of the memory, and be suitable for application in a multi-level component ( Multilevel cell) operation window (〇Perating window). It is still another object of the present invention to provide a memory unit which can extend the useful life of the memory, improve the periodic margin of the memory, and be adapted to be applied to the operation window of the multi-level component. The invention provides a data storage method for a memory unit', which comprises the steps of: firstly, dividing a memory unit into a plurality of small memory groups; and then, defining a plurality of small-sized memory bodies, the critical electric distribution area of the dream Secondly, according to the threshold voltage distribution area of each small memory group, a plurality of write verification threshold voltages of each small memory group and a plurality of reference detection values of each small memory group are defined; thereafter, a small § has been used. Recall the body group to store a data. 1304985 P950034 19579twf.doc/006 A copy = re-proposed - view (four) unit, which uses the group, and then, according to each small; memory unit a small year (four) Xi Xi" group boundary voltage area to determine the existence of H- Xi & quot Writer verification light and multiple parameters such as 贞 值 储 本 本 本 因 因 因 因 因 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本The operating window of the period of use ~ ~ month. 1 More useful years, and suitable for application in multiple levels of components can be understood as other purposes, features and advantages can be more clearly as follows. , Dhan (four) cases and cooperate with the closed type, for details [Implementation] ^ 11 towel will be the top of the list to the Langben hair 0 difficult embodiment, i = any of the technical fields of this field = It can be applied to the present invention, for example, erasable (EPROM), electronic publishing team. Becky U-body CEEPROM, & In addition to programmable read-only memory, Ik machine access memory (DRAM), static memory access memory (SRAM) and so on. Figure 3 depicts a circuit block diagram of a flash memory cell unit 3 in accordance with an embodiment of the present invention. The flash memory unit 300 has a capacity of, for example, 1 G (billion bytes, 1304985 P950034 19579 twf.doc/006 gega byte), and is divided into small memory groups 301 to 304 each having a capacity of 1 M. Fig. 4 is a diagram showing a critical voltage distribution diagram of a data storage method for a flash memory cell in accordance with an embodiment of the present invention, wherein the horizontal axis represents the threshold voltage and the vertical axis represents the number of bits. Referring to FIG. 3 and FIG. 4 simultaneously, the small memory groups 301 to 304 correspond to the threshold voltage distribution curves 401 to 404, and the original undivided threshold voltage distribution curve 40 of the flash memory unit 300 is used as a control. As can be seen from FIG. 4, the distribution value D3 of the threshold voltage distribution region of the threshold voltage distribution curve 40 is larger than the distribution value D4 of the individual threshold voltage distribution regions of the threshold voltage distribution curves 401 to 404, by changing the distribution difference (D3-D4). Can be used to increase the sensing window and reduce the write threshold voltage difference. The high limit of the distribution curves 401 to 404 can be referred to the reference point I_base, so that the high limit of the detected curve 401 is smaller than the threshold voltage B1, the high limit of the distribution curve 402 is between the threshold voltages B1 to B2, and the upper limit of the distribution curve 403 is Between the threshold voltages B2 and B3, the upper limit of the distribution curve 404 is between the threshold voltages B3 and B4, and the original undivided high limit of the flash memory cell 300 is used as a control between the threshold voltages B4 and B5. The embodiment of the invention is not limited to dividing the memory unit into four small memory groups, and can be divided into any number of small memory groups according to the need thereof, for example, the memory unit with a capacity of 1G can be divided into 1 million small memories. The body group, each memory group has 1K bytes, or the memory unit with a capacity of 1G is divided into 16 thousand word lines, and each word line has 64 kilobytes. The invention obtains a plurality of small memory groups by dividing the memory unit, and can store the threshold voltage distribution information of the plurality of small memory groups to an external memory or a buffer memory, so that the threshold voltage distribution information records a plurality of small Memory 1304985 P950034 19579twf.doc/006 distribution area, and the distribution value of the threshold voltage distribution area can be reduced to increase the storage effect, but the invention is not limited to being divided into small memory groups having the same capacity, and can be divided into Small memory groups of different capacities. At the same time, when the data is stored, the present invention does not need to consider the high boundary before the undivided memory unit, and only needs to consider the high limit of each memory group after the division, so that the programming of the threshold voltage difference between the states can be made. It is more flexible, and it is known to those skilled in the art that the present invention is not limited to defining high limits, and may be replaced with other characteristic points of the defined curve such as low limits, or intermediate limit values, and the like. FIG. 5 is a diagram showing another threshold voltage distribution diagram of a data storage method for a flash memory cell according to an embodiment of the present invention. The horizontal axis represents the threshold voltage, the vertical axis represents the number of bits, and the horizontal axis represents the threshold voltage, and the vertical axis. Indicates the number of bits. Please refer to FIG. 3 and FIG. 5, and the small memory groups 301 to 3〇4 of FIG. 3 are the voltage distribution curve 41丨~ under the other. For example, the distribution curve 4〇1 stores the first state logic level 1 for the bait material, and the distribution curve 411 to 414: = the material storage state-state logic level quasi-〇, therefore, the flash memory single=two quasi-remembers . The threshold voltage distributions of the distribution curves 401 to 404 can be used to define the verification threshold voltages of the distribution curves 411 to 414. The distribution curve 401 of the ancient K ay electric & knife type verification and α sense is less than B1, then the corresponding distribution curve 411 is between 1 疋 为 is PV1, the upper limit of the distribution curve 402 is defined B1 and 间 between The distribution curve 412 verifies the verification. The product boundary voltages PV3, PV4 can be deduced by analogy. The storage side, the field 1 will be the data for the flash memory unit according to the embodiment of the present invention. The axis represents the voltage distribution map of the bit, and the horizontal drawing represents the threshold voltage and the vertical element. In order to clearly show the difference between the curves, the threshold voltage is divided into 10
1304985 P950034 19579twf.doc/006 佈曲線401及臨界雷懕八饮冰仏 電壓軸。請同時參考圖5及、U置於另—相同之臨界 請〜PV4之規*彳可及二:，根據圖5之寫入驗證電 ref4，例如可決定臨界電壓B ρrefl〜 之中間點為refl。當她八二'入驗_電壓ρ\α Β卜則可將記憶體群4〇1 ^至二401 士之高界限小於 值refl作為資料讀取參考，當;參考_ 限介於财w _==4H之高界 同時使用參考偵測值ref4作為f料讀取參考，π 4 ’ 依此類推，在此參考偵測值refl〜 及電流形式。 ef4T狀界電壓形式 本實施例之寫入臨界電壓差為兩曲線之同—界限 差，基於各位元具有相同之寫入臨界電壓差例如圖6的八 感測窗為佈曲線401之最大值（高界限）與分佈曲線々η 最小值（低界限）的差值，寫入臨界電壓差值為分佈曲線 401之最小值（低界限）與分佈曲線411之最小值（低界 限）的差值。所以分佈曲線401與分佈曲線411之寫入眇 界電壓差為DVt41，分佈曲線404與分佈曲線414之寫入 臨界電壓差為DVt44 ’分佈曲線401與分佈曲線411 ^戌 測窗為SW41 ’分佈曲線404與分佈曲線414之感測窗^ SW44。感測窗SW41、寫入臨界電壓差DVt41與分佈值 D4之關係為（DVt41-SW41) =D4。在本發明中，由於將 記憶體單元分割成多個小記憶體群，使得分佈值減少，因 此可加大感測窗及降低狀態間之寫入臨界電壓差。 11 1304985 P950034 19579twf.doc/〇〇6 軸表示位元數。為㈣表示臨界電壓，縱 電壓分佈曲線4()^i 1佈值以改善寫人速度’將臨界 參考偵測點ref以作為臨界分佈曲線7〇 ’並使用 _度的不同而益=本 本分佈值m分料i t 佈曲線術〜704，使原 m的差m θ分佈值Μ。料值D3與分佈值 ，於疋使得窄化非常困難，但在分割後，分 佈值D4與分佈值D9 # s 丁丄 ^刀 當創造相同❹馆時，w f ’使得窄化料許多。於是 壓差，目卜^ 、於本毛明中具有較小之寫入臨界電 jr改善週期邊際及具有二次位元效應。 資枓二户=本發明又—實_之用於快閃記憶體單元之 j儲存綠祕界賴分佈目，橫歸雜界電壓，縱 “不位^數。為說明本發明在MLC (multi-level-ceU， 準單兀）之貫施方式’臨界電壓分佈曲線80〜83， 、I、表四種不同之㈣儲存狀態，彳壯分別為邏輯位準 >卜00、10 ’而臨界電壓分佈曲線81〜幻為窄化後之 2電壓分佈曲線。由於需處理多重邏輯位準，於是狀態 :‘、’、界電壓差DVt8增大，而感測窗sw8減少，在第 種叹计中，在切割記憶體單元後，臨界電壓分佈曲線 8〇1 813、823、833在相同感測窗SW8下，具有較低之 ，，寫人臨界電壓差DVt9。在第二種設計中 ，在切割記 I1思體單元後，臨界電壓分佈曲線8〇4、814、824、834在相 12 1304985 19579twf.doc/006 P950034 门寫入^，差DVt8具有較大之感測窗卿，孰知此 2之人士畜知，本發明之Μΐχ不限 ’:可 其需要增加邏輯位準及增加資料儲存狀能。L叮視 儲本發明實施例之用於快閃記憶體單元之資料 堵存方法的k程圖。首先，在步驟S90 ， 尸元為多個小記憶體群;接著，在步驟_中= 小5己憶體群之叫分佈區域；其次，在步驟_ 中，根據各小記憶體群之臨界_ =之界晰義多個寫入驗證位準上 多::ί;Γ證位準可為多個寫入驗證臨界電 信= 準可為多個參考臨界電壓參考 估=，在步驟S904 ’檢測該小記憶體之分佈 2區域’在步驟_5中，儲存該小記憶體之分佈之訊 诚二卜部5己憶，’該分佈資訊記錄多個臨界電壓分佈區 域，A習此技藝之人士告知，八Y士-欠 部印n T、目衫訊秘於存在在—外 %體可視4要儲存在任何可儲存分佈資訊之記情 體广可為一緩衝記憶體，在步驟讓中，根據此； =決定該小記Μ群使用哪個寫人驗證位準及哪個參考感 測位準’其後，在步驟S9G7中，寫人小記憶體群之資料。 紅上所述，在本發明之用於記憶體單元之資料儲存方 =由於採用將記憶體單元分割為多個小記憶體群，使得 u界電龍域的分佈值減少，具有可加大感測窗及減少寫 界電壓之結構’目此可改善記憶體之勒邊際、延長 記憶體使特限、及適於多重位準元件之操作窗。 13 1304985 19579twf.doc/006 P950034 雖然本發明已以較佳實施例揭露如上，然其並 限定本發明，任何熟習此技藝者，在不脫離^發明=从 和範圍内，當可作些許之更動與潤飾，因此本^日和砷 範圍當視後附之申請專利範圍所界定者為準。§明之保護 【圖式簡單說明】 圖1描繪習知之記憶體單元資料儲存握 分佈圖。 ’、之以界電Μ 圖2描繪另一習知之記憶體單元資料儲 電壓分佈圖。 ’、作之S品界 圖3描緣本發明實施例快閃記憶體嚴 塊圖。 早7^ 300之電路方 圖4描繪本發明實施例之用於快閃記 。一 儲存方法的臨界電壓分佈圖。 〜—早凡之資料 圖5描繪本發明實施例之用於快閃記惊q ^ 儲存方法的另一臨界電壓分佈圖。 —早元之育料 圖6描繪本發明實施例之用於快閃記憶體+ 儲存方法的又一臨界電壓分佈圖。 早元之貧料 圖7描緣本發明另-實施例之用於快閃記 … 貝料儲存方法的臨界電壓分佈圖。 ~體早70之 圖8描緣本發明又一實施例之用於快閃 資料儲存方法的臨界電壓分佈圖。 ％體單7L之 圖9描繪本發明實施例之用於快閃記憶體_ 一 儲存方法的流程圖。 〜早兀之資料 【主要元件符號說明】 14 1304985 P950034 19579twf.doc/006 101 〜104、201 〜206、40、401 〜404、411 〜414、70、 701 〜704、80〜83、803、804、813、814、823、824、833、 834 :臨界電壓分佈曲線 300 :記憶體單元 301〜304 :記憶體群 B1〜B5、PV1〜PV4 :臨界電壓 D1〜D4、D8、D9 :分佈值 DVtll〜DVtl3、DVt21 〜23、DVt41、DVt44、DVt8、 DVt9 :臨界電壓差 I_base :參考點 S901〜S907 :資料儲存方法之各步驟 SW11 〜SW13、SW21 〜SW23、SW41、SW44、SW8、 SW9 :感測窗 ref、refl〜ref4 :參考偵測點 151304985 P950034 19579twf.doc/006 Cloth curve 401 and critical Thunder eight drinking hail voltage axis. Please refer to FIG. 5 and U at the same time. The same threshold is applied to the same as the PV4 rule. 彳2: According to the write verification power ref4 of FIG. 5, for example, the intermediate point of the threshold voltage B ρrefl~ can be determined as refl . When she is in the 82nd test _ voltage ρ\α 则 卜, the memory group 4〇1 ^ to 401 士 high limit is less than the value refl as a reference for reading data; when; reference _ limit is between the money w _ The high boundary of ==4H uses the reference detection value ref4 as the f-material read reference, π 4 ' and so on, and refers to the detection value refl~ and the current form. ef4T boundary voltage form The write threshold voltage difference of this embodiment is the same as the difference between the two curves, and the same write voltage difference is obtained based on each bit, for example, the eight sensing window of FIG. 6 is the maximum value of the cloth curve 401 ( The difference between the high limit) and the distribution curve 々η minimum (low limit), the write threshold voltage difference is the difference between the minimum value (low limit) of the distribution curve 401 and the minimum value (low limit) of the distribution curve 411. Therefore, the write boundary voltage difference between the distribution curve 401 and the distribution curve 411 is DVt41, and the write threshold voltage difference between the distribution curve 404 and the distribution curve 414 is DVt44' distribution curve 401 and distribution curve 411. The measurement window is SW41' distribution curve. 404 and sensing window 414 of distribution curve 414. The relationship between the sensing window SW41, the write threshold voltage difference DVt41, and the distribution value D4 is (DVt41 - SW41) = D4. In the present invention, since the memory unit is divided into a plurality of small memory groups, the distribution value is reduced, so that the sensing threshold and the write threshold voltage difference between the states can be increased. 11 1304985 P950034 19579twf.doc/〇〇6 Axis represents the number of bits. For (4), the threshold voltage is expressed, and the vertical voltage distribution curve 4()^i1 is used to improve the writing speed. 'The critical reference detection point ref is taken as the critical distribution curve 7〇' and the difference is _ degrees. The value m is divided into it and the curve is ~704, so that the difference m θ distribution value of the original m is Μ. The material value D3 and the distribution value are very difficult to narrow, but after the division, the distribution value D4 and the distribution value D9 # s 丄 丄 ^ knife When creating the same ❹ ,, w f ' makes the narrowing material a lot. Therefore, the pressure difference, the object ^, in the Mao Ming has a smaller write critical power jr improved cycle margin and has a quadratic effect.枓 枓 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -level-ceU, quasi-single) The critical voltage distribution curve 80~83, I, table four different (four) storage state, strong and strong respectively logical level > 00, 10 ' and critical The voltage distribution curve 81 ~ illusion is the narrowed voltage distribution curve. Since multiple logic levels need to be processed, the state: ', ', the boundary voltage difference DVt8 increases, and the sensing window sw8 decreases, in the first kind of sigh In the second design, after the memory cell is cut, the threshold voltage distribution curves 8〇1 813, 823, and 833 are lower under the same sensing window SW8, and the write threshold voltage difference DVt9. After cutting the I1 body unit, the critical voltage distribution curves 8〇4, 814, 824, and 834 are written in the phase 12 1304985 19579twf.doc/006 P950034 gate, and the difference DVt8 has a larger sensing window, knowing this 2 people know that the invention is not limited to ': it needs to increase the logic level and increase the data The storage process can store the k-pass map of the data storage method for the flash memory unit in the embodiment of the present invention. First, in step S90, the corpse is a plurality of small memory groups; _中=小五己忆群群 is the distribution area; secondly, in step _, according to the critical _ = boundary of each small memory group, multiple write verification levels are more:: ί; The level may be a plurality of write verification critical telecommunications = quasi-a plurality of reference threshold voltage reference estimates =, in step S904 'detect the distribution 2 area of the small memory', in step_5, storing the small memory The distribution of the message of the two departments of the Ministry of Peace has recalled that 'the distribution of information recorded a number of critical voltage distribution areas, A learners of this skill told that eight Y Shi - owe part of the print n T, eyewear secrets exist in the outside -% Body Visibility 4 is stored in any bufferable information that can be stored as a buffer memory. In the step, according to this; = Determine which writer verification level and which reference sensing bit is used by the small group After that, in step S9G7, the data of the small memory group is written. The data storage side for the memory unit is defined as the division of the memory unit into a plurality of small memory groups, so that the distribution value of the u-done electric field is reduced, and the sensing window can be increased and the write-off voltage can be reduced. The structure 'is improved to the margin of the memory, to extend the memory, and to operate the window of the multi-level component. 13 1304985 19579twf.doc/006 P950034 Although the invention has been disclosed above by way of a preferred embodiment, However, it is intended to limit the invention, and any person skilled in the art can make some modifications and refinements without departing from the invention, and the scope of the application is defined by the scope of the patent application. Subject to it. § Clear protection [Simplified illustration] Figure 1 depicts a conventional memory unit data storage grip distribution map. </ RTI> </ RTI> </ RTI> Figure 2 depicts another conventional memory cell data storage voltage profile. The S product boundary is shown in Fig. 3. The flash memory block diagram of the embodiment of the present invention is depicted. Circuitry of the early 7^300 Figure 4 depicts an embodiment of the present invention for flashing. A threshold voltage distribution diagram for a storage method. ~ - Early Data Figure 5 depicts another threshold voltage profile for the flash memory q ^ storage method of an embodiment of the present invention. - Early Elemental Feed Figure 6 depicts yet another threshold voltage profile for a flash memory + storage method in accordance with an embodiment of the present invention. The poor material of the early element Fig. 7 depicts the threshold voltage distribution map for the flash memory storage method of another embodiment of the present invention. Figure 8 depicts a threshold voltage distribution diagram for a flash data storage method in accordance with yet another embodiment of the present invention. % Body Sheet 7L Figure 9 depicts a flow chart for a flash memory storage method in accordance with an embodiment of the present invention. ~ 早兀的资料 [Main component symbol description] 14 1304985 P950034 19579twf.doc/006 101~104, 201~206, 40, 401~404, 411~414, 70, 701~704, 80~83, 803, 804 813, 814, 823, 824, 833, 834: threshold voltage distribution curve 300: memory cells 301 to 304: memory groups B1 to B5, PV1 to PV4: threshold voltages D1 to D4, D8, D9: distribution value DVtll ~DVtl3, DVt21~23, DVt41, DVt44, DVt8, DVt9: Threshold voltage difference I_base: Reference point S901~S907: Steps of data storage method SW11~SW13, SW21~SW23, SW41, SW44, SW8, SW9: Sensing Window ref, refl~ref4: reference detection point 15