CN103325412B - There is integrated circuit and operational approach thereof that dynamically sensing is interval - Google Patents
There is integrated circuit and operational approach thereof that dynamically sensing is interval Download PDFInfo
- Publication number
- CN103325412B CN103325412B CN201210073973.9A CN201210073973A CN103325412B CN 103325412 B CN103325412 B CN 103325412B CN 201210073973 A CN201210073973 A CN 201210073973A CN 103325412 B CN103325412 B CN 103325412B
- Authority
- CN
- China
- Prior art keywords
- storage array
- threshold
- threshold voltage
- storage
- definitions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a kind of integrated circuit with dynamically sensing interval and operational approach thereof.This integrated circuit includes a storage array, and this storage array is characterized by a threshold definitions, and it includes that multiple threshold voltage ranges represents the data value stored by a part for this storage array, and one group of sensing interval separates the plurality of threshold voltage ranges.This threshold definitions can change and respond at least one programming operation and erasing operation.So operation variation is by a distribution of this data value of this section store of this storage array.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of integrated circuit with dynamically sensing interval and operational approach thereof.
Background technology
The threshold voltage ranges of memory element is relevant to the different pieces of information value can being stored in this memory element.And sense interval these threshold voltage ranges of separation.For example, less threshold voltage ranges can represent data value " 1 ", and bigger threshold voltage ranges can represent data value " 0 ", and sensing interval separates these less threshold voltage ranges and bigger threshold voltage ranges.One sensing wider between neighboring threshold voltage scope is interval generally corresponding with less storage mistake, because a particular threshold voltage of some memory element can be belonged to by decision mistakenly and can become ratio in the threshold voltage ranges of this mistake and be less likely to.
U.S. Patent No. 7330376 discloses the storage method of a kind of memorizer, wherein relevant to different pieces of information value in memory element threshold voltage ranges has this memory element is divided into multiple less memory element, and each less memory element has fewer number of memory element.The threshold voltage ranges of one less memory element is typically less than the threshold voltage ranges of a bigger memory element, and the process variations being for example because in the smaller area of this wafer is less.Therefore, when the area of memory element diminishes, a particular threshold voltage of some memory element can be determined that the situation belonging to erroneous data value representative in the threshold voltage ranges of this mistake can become to be less likely to mistakenly.
But, memory element can not be split in the real-time operation of a storage array, and respond the ongoing operation of memorizer and e.g. program or wipe.Additionally, be only through that each memory element is become the smaller the better sensing interval of improving also have its limit.Bigger memory element has the advantage that can reduce its related management time when accessing this storage array.
Summary of the invention
Technology described herein is to provide a storage array and is divided into the storage group of multiple e.g. page.Change this threshold definitions and be in response at least one programming operation and erasing operation, a distribution of this data value that its variation is stored by this part of this storage array.This variation can be performed by the control circuit in the test machine outside the control circuit in this integrated circuit or this integrated circuit.This part of this storage array is characterized by this threshold definitions, represent by the data value stored in this part of this storage array including (i) multiple threshold voltage ranges, and (ii) one group of sensing interval separates the plurality of threshold voltage ranges.The example of other storage group size is character, wordline, section and half page.
The example changing this threshold definitions is to change this threshold voltage ranges, such as, determine the width of this threshold voltage ranges according to the Relative distribution of this data value.One first threshold voltage range is wider compared with a Second Threshold voltage range, and respond this particular memory group and store large number of one first data value represented by this first threshold voltage range, it is relative to one second data value represented by this Second Threshold voltage range.
The example changing this threshold definitions is, changes this group sensing interval, such as, changes at least one position that at least one sensing in this threshold definitions is interval.
When the threshold definitions variation of this part of this storage array, then the access features (such as reading or programming operation) of this part of this storage array also changes.One embodiment further includes at least one access features skew of this part with reference to this storage array of memory storage, and the skew of this at least one access features is the threshold definitions variation of this part compensating this storage array.The example of access features is a reference current skew of programming checking, a wordline level skew of programming checking, a reference current skew of reading, and the wordline level skew read.This part accessing this storage array is offset according to this access features in this reference memorizer.
In one embodiment, the reading time of this reference memorizer be no longer than a wordline access this storage array this part time is set.When this wordline arranges this part that the time accesses this storage array, this reference memorizer can access the access features skew of this part reading this storage array.In this reference memorizer has the example of shorter reading time, this reference memorizer this storage array this part in relatively this storage array this part closer to this word line driver.In this reference memorizer has another example of shorter reading time, one the second storage array relatively this wordline including this reference memorizer of wordline access accesses this storage array and has the shorter access time.Second storage array includes at least one access features skew of this part of reference this storage array of memory storage, this threshold definitions variation of this part of this access features this storage array of migration.
In one embodiment, the mode with error correcting code is used to access this reference memorizer.
In one embodiment, change this threshold definitions, and respond the different relative populations between this data value in different in this part being stored in this storage array.The example of relative populations is that first quantity of one of this data value of being stored in this part of this storage array is relative to a ratio of other quantity one or more of other data values one or more in this part being stored in this storage array or percentage ratio.
Another object of the present invention is for providing a kind of method, comprise: change a threshold definitions of a part for a storage array, and respond at least one programming operation and erasing operation, one distribution of this data value that its variation is stored by this part of this storage array, wherein this part of this storage array is characterized by a threshold definitions, represent the data value stored by this part of this storage array including (i) multiple threshold voltage ranges, and (ii) one group of sensing interval separates the plurality of threshold voltage ranges.
Disclose the example changing this threshold definitions herein, such as, change at least one position that at least one sensing in this threshold definitions is interval.
Other example includes, reads this reference memorizer of at least one access features skew of this part storing this storage array, and the skew of this access features is the variation of this threshold definitions of this part compensating this storage array；And this part of this storage array is accessed according to the skew of this at least one access features.
Other example includes, read this reference memorizer of at least one access features skew of this part storing this storage array, the skew of this access features is the variation of this threshold definitions of this part compensating this storage array, within the reading time its be no longer than this storage array of access this part time is set.
A further object of the present invention is divided into the storage group of multiple e.g. page for providing storage array.Relative populations according to this data value in this part being stored in this storage array changes this threshold definitions.This part of storage array is characterized by a threshold definitions, represents the data value stored by this part of this storage array including (i) multiple threshold voltage ranges, and (ii) one group of sensing interval separates the plurality of threshold voltage ranges.The example of other storage group size is character, wordline, section and half page.
In one embodiment, the variation of this threshold definitions is in response at least one programming operation and erasing operation, a distribution of the plurality of data value that its variation is stored by this part of this storage array.
In one embodiment, first quantity of one of this data value during this relative populations is stored in this part of this storage array is relative to a ratio of other quantity one or more of other data values one or more in this part being stored in this storage array or percentage ratio.
Accompanying drawing explanation
Fig. 1 is the icon of threshold voltage and position counting, has reading reference voltage and will be stored in the voltage range separation representing different pieces of information value in this memory element.
Fig. 2 shows the threshold voltage of whole storage array and the icon of position counting, and the icon that in this array, the threshold voltage of two different pages counts with position.To in this memory page by the particular data value stored by memory element, the threshold voltage ranges that two different memory pages have different in width represents these particular data value.
Fig. 3 is that different size stores the threshold voltage of group and the icon of position counting, display threshold voltage range and the relation storing group's (such as page) size.
Fig. 4 is a threshold definitions, and display represents the threshold voltage ranges of different pieces of information value, and the sensing separating threshold voltage ranges is interval, and wherein threshold voltage ranges has variation width.
Fig. 5 to Fig. 8 is that some forms show that the storage group of the e.g. page stores a particular data value of different relative populations (relative bit number), and change following parameter: represent the threshold voltage ranges of this particular data value, and determine to represent the width variation of the threshold voltage ranges of this particular data value.
Fig. 9 is the threshold definitions of an e.g. storage group for the page, and display represents the threshold voltage ranges of different pieces of information value, and reads reference voltage and sensing interval, and it is distributed by the data crossing over whole storage array and is defined.For example, the data distribution crossing over whole storage array can be as shown in Figure 1.
Figure 10 is the threshold definitions of an e.g. storage group for the page, and display represents the threshold voltage ranges of different pieces of information value, and reads reference voltage and sensing interval, and it is distributed by the data crossing over whole storage array and is defined.
Figure 11 to Figure 12 is exemplary flowchart, shows the data programming of the stored reference group position (or access features skew bit) of the data distribution according to storage group (the e.g. page) and this storage group.
Figure 13 is exemplary flowchart, shows the digital independent of the stored reference group position (or access features skew bit) of the data distribution according to storage group (the e.g. page) and this storage group.
Figure 14 is an exemplary block diagram, its display have primary array be place the distance further away from word line driver store with reference to the array of group position or access offset memory characteristic closer to storage array.
Figure 15 is an exemplary block diagram, and to have bigger primary array be to have longer wordline in its display, and less referential array stores with reference to group position or access offset memory characteristic its storage array with shorter wordline.
Figure 16 shows primary array and stores and arrange the time with reference to the different of group position or the array of access features offset data.
Figure 17 is exemplary flowchart, shows the digital independent of the stored reference group position (or access features skew bit) of this storage group of the data distribution according to storage group (the e.g. page) and use error correcting code.
Figure 18 shows the simplification block schematic diagram of improvement storage integrated circuit according to an embodiment of the invention.
[main element symbol description]
1850: integrated circuit
1800: store with reference to the array of nonvolatile memory cells of group data and with reference to memorizer
1801: column decoder
1802: wordline
1803: line decoder
1804: bit line
1805: bus
1807: data/address bus
1806: sensing amplifier/data input structure
1809: program, wipe and read adjustment bias state mechanism change threshold definitions and access features
1808: bias adjusts supply voltage
1811: Data In-Line
1815: DOL Data Output Line
Detailed description of the invention
Example shown here is to have four data values in a memory element.Other example can be to have two data values, have eight data values or have the data value of other numbers.
Fig. 1 is the graph of a relation of threshold voltage and figure place, and it has reading reference voltage to separate being stored in the voltage range representing different pieces of information value in this memory element.
Read reference voltage-RD1, RD2, RD3-to be all positioned at the minima that in whole storage array, memory element threshold voltage is distributed.When a read operation, whether memory element determines stored particular data value higher or lower than a specific reading reference voltage according to its threshold voltage value.This reads reference voltage and is divided into several threshold voltage ranges by being stored in the threshold voltage ranges representing different pieces of information value in this memory element.The first threshold voltage range reaching as high as RD1 represents one first data value.Second Threshold voltage range between RD1 and RD2 represents one second data value.The 3rd threshold voltage ranges between RD2 and RD3 represents one the 3rd data value.4th threshold voltage ranges of minimum RD3 represents one the 4th data value.In an actual threshold voltage definition, threshold voltage ranges is separated by sensing interval as shown in Fig. 4, Fig. 9 and Figure 10.
Fig. 2 shows the threshold voltage of two different pages and the graph of a relation of figure place in the threshold voltage of whole storage array and the graph of a relation of figure place, and this array.To in this memory page by the particular data value stored by memory element, these particular data value are to be represented by the threshold voltage ranges of had different in width in two different memory pages.Memory page A has one group of threshold voltage distribution and uses long dotted line to represent, and memory page B has one group of threshold voltage distribution and uses short dash line to represent.
For by one first data value reached as high as representated by the first threshold voltage range of RD1, memory page A has bigger threshold voltage distribution and a wider threshold voltage ranges compared to memory page B.For by one second data value representated by the Second Threshold voltage range between RD1 and RD2, memory page A has less threshold voltage distribution and a narrower threshold voltage ranges compared to memory page B.For by one the 3rd data value representated by the 3rd threshold voltage ranges between RD2 and RD3, memory page A has the biggest threshold voltage distribution and a widest threshold voltage ranges compared to memory page B.For by one the 4th data value representated by the 4th threshold voltage ranges of minimum RD3, memory page A has similar threshold voltage distribution and similar threshold voltage ranges with memory page B.
Fig. 2 shows, the different memory pages in an identical storage array can have the data distribution of large-scope change, and its threshold voltage distribution with large-scope change and threshold voltage ranges represent and be stored in data values different in memory page.Although these threshold voltages distribution in the different pages changes between on a large scale, the threshold voltage of memory element between the readings reference voltage-RD1 shown in Fig. 2, RD2, RD3-are still by whole storage array is distributed and is determined.
The reference voltage that reads shown in Fig. 2 is frequently not positioned at the midpoint of a memory page neighboring threshold voltage distribution.For example, for memory page A and memory page B, reading reference voltage RD2 is not the midpoint (definition at midpoint is the maximum of lower threshold voltage range and the centre of the minima of higher threshold voltage scope) at adjacent two threshold voltage ranges, but in the right side at real midpoint of two neighboring threshold voltage scopes of memory page A and the left side at the real midpoint of two neighboring threshold voltage scopes of memory page B.Because the real midpoint of two neighboring threshold voltage scopes is different from reading reference voltage, different memory pages have nonideal reading reference voltage and nonideal sensing is interval.
Fig. 3 is that different size stores the threshold voltage of group and the graph of a relation of figure place, the relation between its display threshold voltage range and storage group's (such as page) size.
The right side graphic at this, shows three nido threshold voltage distributions together.The threshold voltage distribution of these three nido is corresponding with 512 distributions, 64 distributions and 8 distributions respectively.The threshold voltage of these three nidos is distributed circled part and shows there is the narrower dispersion of distribution (threshold voltage ranges) in less position count distribution.
Fig. 4 is a threshold definitions, and display represents the threshold voltage ranges of different pieces of information value, and the sensing separating threshold voltage ranges is interval, and wherein threshold voltage ranges has the width of variation.
Three are read reference voltage is RD1, RD2, RD3 respectively.One first data value representated by first threshold voltage range has the width determined by width W1 and extra twice dispersion of distribution DW1 (each one of the both sides of W1).The maximum of width W1 is at B2_min, and it is determined by manufaturing data.
One second data value representated by Second Threshold voltage range has the width determined by width W2 and extra twice dispersion of distribution DW2 (each one of the both sides of W2).The minima of Second Threshold voltage range is programming verifying voltage PV1.
One the 3rd data value representated by 3rd threshold voltage ranges has the width determined by width W3 and extra twice dispersion of distribution DW3 (each one of the both sides of W3).The minima of the 3rd threshold voltage ranges is programming verifying voltage PV2.
One the 4th data value representated by 4th threshold voltage ranges has the width determined by width W4 and extra twice dispersion of distribution DW4 (each one of the both sides of W4).The minima of width W4 is at B7_min, and it is determined by manufaturing data.The minima of the 4th threshold voltage ranges is programming verifying voltage PV3.
The interval SW1 of sensing separates the first and second threshold voltage ranges.Sensing interval SW2 separation second and the 3rd threshold voltage ranges.The interval SW3 of sensing separates the third and fourth threshold voltage ranges.
One example in sensing interval is defined as follows.In the definition example that sensing is interval at this, sensing interval SW1, SW2, SW3 have identical width.Additionally, in the definition example that sensing is interval at this, read reference voltage be RD1, RD2, RD3 be respectively position in interval SW1, SW2, SW3 midpoint of respective sensing.Programming verifying voltage PV1, PV2, PV3 be each sensing interval SW1, SW2, SW3 maximum at.
SW1=[(B7_min-B2_min)-DW1-(W2+2*DW2)-(W3+2*DW3)-DW4] * 1/3
SW2=[(B7_min-B2_min)-DW1-(W2+2*DW2)-(W3+2*DW3)-DW4] * 1/3
SW3=[(B7_min-B2_min)-DW1-(W2+2*DW2)-(W3+2*DW3)-DW4] * 1/3
RD1=(B2_min)+DW1+0.5*SW1
PV1=RD1+0.5*SW1
RD2=[PV1+ (W2+2*DW2)+0.5*SW2]
PV2=RD2+0.5*SW2
RD3=[PV2+ (W3+2*DW3)+0.5*SW3]
PV3=RD3+0.5*SW3
Another example in sensing interval is defined as follows.In the definition example that sensing is interval at this, sensing interval SW1, SW2, SW3 have according to respective ratio ratio1, the relative width of ratio2, ratio3, wherein 0 ＜ ratio1 ≠ ＜ 1, ratio1+ratio2+ratio3=1.In addition, in the definition example that sensing is interval at this, read reference voltage be RD1, RD2, RD3 be the relative position at respective sensing interval SW1, SW2, SW3, its be according to respective value r1, r2, r3 depending on, and 0 ＜ r# ≠ ＜ 1.Programming verifying voltage PV1, PV2, PV3 are at the maximum of respective sensing interval SW1, SW2, SW3.
SW1=[(B7_min-B2_min)-DW1-(W2+2*DW2)-(W3+2*DW3)-DW4] * ratio1
SW2=[(B7_min-B2_min)-DW1-(W2+2*DW2)-(W3+2*DW3)-DW4] * ratio2
SW3=[(B7_min-B2_min)-DW1-(W2+2*DW2)-(W3+2*DW3)-DW4] * ratio3
RD1=(B2_min)+DW1+r1*SW1
PV1=RD1+ (1-r1) * SW1
RD2=[PV1+ (W2+2*DW2)+r2*SW2]
PV2=RD2+ (1-r2) * SW2
RD3=[PV2+ (W3+2*DW3)+r3*SW3]
PV3=RD3+ (1-r3) * SW3
Fig. 5 to Fig. 8 is that some show that the storage group of the e.g. page stores the form of a particular data value of different relative populations (relative bit number), and following parameter can change: represent the threshold voltage ranges of this particular data value, and determine to represent the width variation of the threshold voltage ranges of this particular data value.
In the example of Fig. 5 to Fig. 8, a particular memory location position can store four data values.These four data values are respectively by four threshold voltage distributions: distribution 1, distribution 2, distribution 3, distribution 4 represent.The size of each distribution is to determine according to by the data value representated by the distribution of respective threshold voltage.Fig. 5, Fig. 6, Fig. 7, Fig. 8 show distribution 1, distribution 2, distribution 3, the details of distribution 4 respectively.
In an example, a storage group has 100 positions.Its absolute profile is that distribution 1 has 25 positions, distribution 2 has 25 positions, distribution 3 has 25 positions, distribution 4 has 25 positions.Its Relative distribution is then that distribution 1 has 25%, distribution 2 has 25%, distribution 3 has 25%, distribution 4 has 25%.Shown in respective figure according to Fig. 5 to Fig. 8, the Relative distribution of 25% is the 2nd hurdle in each distribution of this form (distribution 1, distribution 2, distribution 3, distribution 4).Distribution 1 according to Fig. 5, distribution 11 is selected has variation width D W11.Distribution 2 according to Fig. 6, distribution 21 is selected has variation width D W21.Distribution 3 according to Fig. 7, distribution 31 is selected has variation width D W31.
Fig. 9 is the threshold definitions of an e.g. storage group for the page, and display represents the threshold voltage ranges of different pieces of information value, and reads reference voltage and sensing interval, and it is distributed by the data crossing over whole storage array and is defined.For example, the data distribution crossing over whole storage array can be as shown in Figure 1.Being explained as in Fig. 2, the incremental data distribution of different memory pages is to be caused by nonideal reading reference voltage and sensing interval.Therefore, the interval SW3A of sensing is about the twice of the interval SW1A of sensing.Sense interval SW2A and then there is a medium-width between the width of interval SW1A and SW3A of sensing.
Figure 10 is the threshold definitions of an e.g. storage group for the page, and display represents the threshold voltage ranges of different pieces of information value, and reads reference voltage and sensing interval, and it is distributed by the data crossing over whole storage array and is defined.
After four threshold voltage distributions of definition, the definition of remaining threshold voltage is split in sensing interval SW1A, SW2A and SW3A by impartial.Three are read reference voltage RD1, RD2, RD3 is the midpoint at each sensing interval SW1A, SW2A, SW3A respectively.Width in this threshold definitions of one or more in sensing interval SW1A, SW2A, SW3A and position change.
Figure 11 to Figure 12 is for showing the exemplary flowchart of the data program operation of the stored reference group position (or access features skew bit) of the data distribution according to storage group (the e.g. page) and this storage group.
In fig. 11, this flow process is from input will be programmed into the data in a particular memory group.First produce " with reference to group position (RGB) " to determine that its access features skew (such as programming characteristic or reading characteristic) accesses this particular memory group.The example of access features skew can be reference current or the array word line level of programming checking, and it is to produce according to the threshold definitions that thus distribution of storage group data is determined.Afterwards, new data is programmed.Newly it is programmed that data are programmed checking in this, is that the access features skew by describing with reference to group position (RGB) adjusts.If being verified by programming, then complete this programming.Otherwise, if program fail, then the programming of these data is re-started.
Figure 12 is analogous to Figure 11.But, the current data distribution of this particular memory group has been determined, and creates with reference to group position.Relatively, in fig. 11, this reference group position is that the data according to the data in this storage group stored before programming are distributed and produce, and this new data will program.
The exemplary flowchart of the data read operation of the data distribution of group's (e.g. page) and the stored reference group position (or access features skew bit) of this storage group is stored according to Figure 13.
Respond a reading order, read reference group position (RGB) array to obtain " access features skew " (the such as programming characteristic or reading characteristic) of " with reference to group position (RGB) " its display sensing data to access this particular memory group.According to " with reference to group position (RGB) " data, offseting its access features (such as programming reference current or the array word line level of checking), it is that the threshold definitions determined according to data distribution in thus storage group produces.This sensing amplifier senses data according to this offset memory characteristic, and this sensing amplifier exports its sensing data.
Figure 14 is the exemplary block diagram of a storage array, shows that having primary array in this storage array is disposed at further away from word line driver for storing with reference to the array of group position or the array of access offset memory characteristic.
Wordline extends to reference to group's position (RGB) array (with reference to array or the storage array of access features, also referred to as referential array of group position) then to primary array from XDRV (word line driver).Because referential array is accessed by a part of wordline of closer word line driver, a part of wordline charging of access referential array is very fast and completes to arrange comparatively fast.Relative, because primary array is to be accessed by a part of wordline away from word line driver, a part of wordline charging of access primary array relatively slowly and completes to arrange slower.
Figure 15 is the exemplary block diagram of a storage array, shows that having bigger primary array in this storage array is to have longer wordline, and less referential array stores with reference to group position or access offset memory characteristic, and it has shorter wordline.
In a bigger storage array, wordline extends to primary array from XDRV (word line driver).In a less storage array, wordline extends to reference to group's position (RGB) array (with reference to array or the storage array of access features, also referred to as referential array of group position) from XDRV (word line driver).Because referential array is accessed by a part of wordline of close word line driver, a part of wordline charging of access referential array is very fast and completes to arrange comparatively fast.Relative, because primary array is accessed by a part of wordline away from word line driver, a part of wordline charging of access primary array is relatively slow and completes to arrange slower.
Figure 16 shows primary array and stores and arrange the time with reference to the different of group position or the array of access features offset data.
According to the embodiment shown in Figure 14 or Figure 15, the time that arranges of referential array, and self-reference array received be to complete in the time that arranges of the wordline of this primary array is carried out with reference to sensing time of group position.In the case of Ru Ci, storage operation will not because of etc. the data with reference to group position to be accessed and be delayed by.
Figure 17 is for showing the exemplary flowchart of the data read operation of the stored reference group position (or access features skew bit) of this storage group of the data distribution according to storage group (the e.g. page) and use error correcting code.
This reads the reading flow process that is analogous in Figure 13 of flow process, but many error correcting codes.In response to a reading order, read reference group position (RGB) array to obtain " access features skew " (the such as programming characteristic or reading characteristic) of " with reference to group position (RGB) " its display sensing data to access this particular memory group.Error correcting code is used to correct the mistake from " with reference to group position (RGB) " of referential array.The feature of this error correcting code can be the hardware characteristics in this memorizer, or the software features with extra delay as cost.According to " with reference to group position (RGB) " data, offseting its access features (reference current such as read or the level reading array word line), it is that the threshold definitions determined according to data distribution in thus storage group produces.This sensing amplifier senses data according to this offset memory characteristic, and this sensing amplifier exports its sensing data.
Figure 18 shows the simplification block schematic diagram of improvement storage integrated circuit according to an embodiment of the invention.Wherein integrated circuit 1850 includes storage array 1800.One wordline (arranging) decoder and block select decoder 1801 with along storage array 1800 column direction arrangement a plurality of wordline 1802 and serial selection line couples and electrical communication.One bit line (OK) decoder and driver 1803 with along storage array 1800 line direction arrangement multiple bit lines 1804 and serial selection line couples and electrical communication, to read data and write data from the memory element of this storage array 1800.Address is to be supplied to word-line decoder by bus 1805 to select decoder 1801 and bit line decoder and driver 1803 with block.Sensing amplifier in square 1806 and data input structure, including reading, programming and the current source of erasing mode, couple with bit line decoder via bus 1807.Data are supplied to Data In-Line 1818 by the input/output end port on integrated circuit 1850 and input the data input structure to square 1806.Data are by the sensing amplifier in square 1806, via DOL Data Output Line 1815, it is provided that the input/output terminal to integrated circuit, or the data source to other inner/outer of integrated circuit 1850.Programming, wipe and read and adjust the definition of bias state mechanism 1809 movement threshold and there is threshold voltage ranges and sensing interval is suitable for the data definition of the e.g. different storage groups of memory page, and control bias and adjust the application of supply voltage 1808.
Presently preferred embodiments of the present invention is the most disclosed above with example, it will be appreciated that be only used as example for above-mentioned example, is not used to limit the scope of patent.For knowing the people of this skill, from correlation technique being modified according to appended claims and combine easily.
Claims (23)
1. an integrated circuit, comprises:
One storage array has a threshold definitions, and including (i) multiple threshold voltage ranges, it represents by the data value stored by a part for this storage array, and (ii) one group of sensing interval separates the plurality of threshold voltage ranges；Wherein
Response programming operation and at least one of which of erasing operation, it is the distribution that variation is stored in the data value in this part of this storage array, and change a threshold definitions of this part of this storage array, depending on thereby the threshold definitions of the particular memory location in this part of this storage array is based on the data value being stored in other memory element of this part of this storage array.
Integrated circuit the most according to claim 1, wherein this storage array is divided into multiple storage group, storage group in the plurality of storage group is characterized by this specific threshold definitions of institute of storage group, response programming operation and at least one of which of erasing operation, it is a distribution of this data value that the storage group that variation is stored in the plurality of storage group stores, and changes a threshold definitions of this storage group in the plurality of storage group.
Integrated circuit the most according to claim 1, further includes:
Control circuit, it changes this threshold definitions.
Integrated circuit the most according to claim 1, wherein a test machine changes this threshold definitions.
Integrated circuit the most according to claim 1, wherein this threshold definitions changes by changing this threshold voltage ranges.
Integrated circuit the most according to claim 1, wherein the width of this threshold voltage ranges that this threshold definitions is determined by the Relative distribution according to this data value changes.
Integrated circuit the most according to claim 1, wherein this threshold definitions is by determining that the width of the plurality of threshold voltage ranges changes, make in this part of this storage array, one first threshold voltage range is wider compared with a Second Threshold voltage range, and large number of one first data value represented by this first threshold voltage range of this section store one responding this storage array, it is relative to one second data value represented by this Second Threshold voltage range.
Integrated circuit the most according to claim 1, wherein this threshold definitions changes by changing this group sensing interval.
Integrated circuit the most according to claim 1, wherein this threshold definitions is changed by least one position changing at least one sensing in this threshold definitions interval.
Integrated circuit the most according to claim 1, further includes:
With reference to memorizer, at least one access features skew that this threshold definitions of this part that this part storing this storage array compensates this storage array changes,
Wherein the skew of this at least one access features includes one or more:
One reference current skew of this part programming checking of this storage array, one wordline level skew of this part programming checking of this storage array, the reference current skew that this part of this storage array reads, the wordline level skew that this part of this storage array reads；And
This part accessing this storage array is wherein offset according to this at least one access features in this reference memorizer.
11. integrated circuits according to claim 1, further include:
With reference to memorizer, at least one access features of this part storing this storage array offsets the access of its this part revising this storage array；
Wherein the reading time of this reference memorizer be no longer than a wordline access this storage array this part time is set.
12. integrated circuits according to claim 1, further include:
Word line driver couples with this storage array；
Wherein this storage array includes at least one access features skew that this threshold definitions of this part compensating this storage array with reference to this part of this storage array of memory storage changes, and this part of this reference memorizer relatively this storage array of this part of this storage array is closer to this word line driver.
13. integrated circuits according to claim 1, further include:
First a plurality of wordline has the first length and accesses this storage array；
Second storage array includes at least one access features skew that this threshold definitions of this part compensating this storage array with reference to this part of this storage array of memory storage changes；
Second a plurality of wordline has the second length and accesses this second storage array, and this second length is shorter compared with this first length.
14. integrated circuits according to claim 1, further include:
With reference to memorizer, at least one access features skew that this threshold definitions of this part that this part storing this storage array compensates this storage array changes；
Wherein this reference memorizer uses the mode with error correcting code to access.
15. integrated circuits according to claim 1, wherein this threshold definitions can change, and responds this data value of the different relative populations in this part being stored in this storage array.
16. integrated circuits according to claim 15, wherein one first quantity of one of this relative populations multiple data values of this part being stored in this storage array is relative to a ratio of other quantity one or more of other data values one or more of this part being stored in this storage array or percentage ratio.
17. 1 kinds of memory operating methods, comprise:
Response programming operation and at least one of which of erasing operation, it is the distribution that variation is stored in the data value in a part for a storage array, and change a threshold definitions of this part of this storage array, depending on thereby the threshold definitions of the particular memory location in this part of this storage array is based on the data value being stored in other memory element of this part of this storage array
Wherein this part of this storage array is characterized by this threshold definitions, represent by the data value stored by this part of this storage array including (i) multiple threshold voltage ranges, and (ii) one group of sensing interval separates the plurality of threshold voltage ranges.
18. memory operating methods according to claim 17, wherein change this threshold definitions, including at least one position that at least one sensing changed in this threshold definitions is interval.
19. memory operating methods according to claim 17, further include:
Reading the reference memorizer of at least one access features skew of this part storing this storage array, the skew of this access features is the variation of this threshold definitions of this part compensating this storage array；And
This part of this storage array is accessed according to the skew of this at least one access features.
20. memory operating methods according to claim 17, further include:
Within the reading time its be no longer than access this storage array this part arrange in the time, reading the reference memorizer of at least one access features skew of this part storing this storage array, the skew of this access features is the variation of this threshold definitions of this part compensating this storage array.
21. 1 kinds of integrated circuits, comprise:
One storage array has a threshold definitions, represents the data value stored by a part for this storage array including (i) multiple threshold voltage ranges, and (ii) one group of sensing interval separates the plurality of threshold voltage ranges；And
This threshold definitions is to change according to the relative populations of multiple data values being stored in this part of this storage array, depending on thereby the threshold definitions of the particular memory location in this part of this storage array is based on the relative populations of data value being stored in other memory element of this part of this storage array.
22. integrated circuits according to claim 21, wherein the variation of this threshold definitions is in response at least one programming operation and erasing operation of changing a distribution of the multiple data values by this section store of this storage array.
23. integrated circuits according to claim 21, first quantity of one of multiple data values during wherein this relative populations is stored in this part of this storage array is relative to a ratio of other quantity one or more of other data values one or more in this part being stored in this storage array or percentage ratio.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210073973.9A CN103325412B (en) | 2012-03-20 | 2012-03-20 | There is integrated circuit and operational approach thereof that dynamically sensing is interval |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210073973.9A CN103325412B (en) | 2012-03-20 | 2012-03-20 | There is integrated circuit and operational approach thereof that dynamically sensing is interval |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103325412A CN103325412A (en) | 2013-09-25 |
| CN103325412B true CN103325412B (en) | 2016-08-03 |
Family
ID=49194106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210073973.9A Active CN103325412B (en) | 2012-03-20 | 2012-03-20 | There is integrated circuit and operational approach thereof that dynamically sensing is interval |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103325412B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9734912B2 (en) * | 2015-11-25 | 2017-08-15 | Macronix International Co., Ltd. | Reprogramming single bit memory cells without intervening erasure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI304985B (en) * | 2006-08-16 | 2009-01-01 | Macronix Int Co Ltd | Method for data storage of memory unit and memory unit using the same |
| CN101958150A (en) * | 2009-07-14 | 2011-01-26 | 旺宏电子股份有限公司 | Memory apparatus and operation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7558109B2 (en) * | 2006-11-03 | 2009-07-07 | Sandisk Corporation | Nonvolatile memory with variable read threshold |
-
2012
- 2012-03-20 CN CN201210073973.9A patent/CN103325412B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI304985B (en) * | 2006-08-16 | 2009-01-01 | Macronix Int Co Ltd | Method for data storage of memory unit and memory unit using the same |
| CN101958150A (en) * | 2009-07-14 | 2011-01-26 | 旺宏电子股份有限公司 | Memory apparatus and operation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103325412A (en) | 2013-09-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7352627B2 (en) | Method, system, and circuit for operating a non-volatile memory array | |
| US7996736B2 (en) | Bad page marking strategy for fast readout in memory | |
| US6963505B2 (en) | Method circuit and system for determining a reference voltage | |
| US7965553B2 (en) | Method of verifying a program operation in a non-volatile memory device | |
| US8345487B2 (en) | Method of setting read voltage minimizing read data errors | |
| US8286055B2 (en) | Nonvolatile memory device and method of operating the same | |
| KR100784867B1 (en) | Nonvolatile memory device having flag cells for storing msb program state | |
| CN100437827C (en) | Using multiple status bits per cell for handling power failures during write operations | |
| US8649216B2 (en) | Data writing method and data storage device for adjusting programming voltage values | |
| AU2013209362A1 (en) | Memory device, memory system, and method of controlling read voltage of the memory device | |
| US9299459B2 (en) | Method and apparatus of measuring error correction data for memory | |
| CN1902710A (en) | Method, circuit and system for read error detection in a non-volatile memory array | |
| CN102760493B (en) | Nonvolatile memory devices and verification method thereof | |
| CN101335047A (en) | Flash memory device and method for adjusting read voltage of flash memory device | |
| CN106340324A (en) | Semiconductor memory device, method for repairing bad column and method for setting redundant information thereof | |
| US8780641B2 (en) | Method and apparatus for dynamic sensing window in memory | |
| US8351263B2 (en) | Method circuit and system for operating an array of non-volatile memory (“NVM”) cells and a corresponding NVM device | |
| CN101276645B (en) | Memory device employing three-level cells and related methods of managing | |
| US7394698B1 (en) | Method and apparatus for adjusting a read reference level under dynamic power conditions | |
| CN103325412B (en) | There is integrated circuit and operational approach thereof that dynamically sensing is interval | |
| US9875811B2 (en) | Method and device for reading a memory | |
| CN107025937B (en) | Reading method of memory and memory device | |
| US7894258B2 (en) | Flash memory device for determining most significant bit program | |
| CN103106920B (en) | The flash memory of access method of storage and application the method | |
| TWI497497B (en) | Method and apparatus for dynamic sensing window in memory circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |