CN105278875B - A kind of mixing isomery NAND solid state hard disk - Google Patents
A kind of mixing isomery NAND solid state hard disk Download PDFInfo
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Abstract
The present invention relates to technical field of integrated circuits, more particularly to a kind of mixing isomery NAND solid state hard disk, the mixing isomery NAND solid state hard disk is made of stored logic controller and NAND chip group, it is based on the characteristics of SLC Flash erase-write cycles are higher than MLC flash and 3D flash memory, the mapping table of all NAND chips in isomery solid state hard disk is stored using SLC Flash and is connected to stored logic controller, to improve the endurance life of mixing isomery NAND solid state hard disk on the whole, improve the reading speed to mapping table, renewal speed and reconstruction speed, the reading to mapping table is reduced to a certain extent and updates loss.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of mixing isomery NAND solid state hard disks.
Background technique
NAND type solid state hard disk has become the non-volatile storage technologies of current mainstream, is widely used in data center, a
The every field such as people's computer, mobile phone, intelligent terminal, consumer electronics, and the ever-increasing situation of demand is still presented.NAND's
Manufacturing process has also had evolved to 16nm, and converts from two-dimensional manufacturing process to three-dimensional manufacturing process.General NAND
Memory can be divided into single layer cell NAND (SLC, Single-level cell) and multilevel-cell NAND (MLC, Multi-
level cell).SLC is exactly storage unit storage 1bit data, its main feature is that it is at high cost, capacity is small, speed is fast, erasable
It writes number (Endurance) to be up to 100,000 times, 10 times higher than MLC solid state hard disk, data holding ability (Retention) is
10 years.MLC is exactly that a storage unit can store multiple bit data, and every unit storage 2bit and 3bit may be implemented at present
Data, maximum feature is exactly that capacity is at low cost greatly, but speed is slow, and endurance life is relatively low, and data holding ability is also under meeting
Drop.The performance comparison of SLC and MLC NAND solid state hard disk is as shown in table 1.According to the difference of performance between the two, SLC and MLC
Also difference is very big in the application for NAND solid state hard disk.
Table 1 (√ represents advantage)
The advantages of in order to integrate SLC and MLC nand flash memory, proposes a kind of mixing isomery NAND solid state hard disk, such as Fig. 1
It is shown, it include N grades of NAND memory chips in the nand memory, as series increases, the data holding ability of NAND chip
With it is resistance to write the service life all can worse and worse, operate power consumption it is also increasing.For example, the first order is single layer cell (SLC) NAND chip,
The second level can be every unit 2bit multilevel-cell NAND chip, and the third level can be every unit 3bit multilevel-cell NAND core
Piece, and so on, and N grades can stack NAND storage chip for state-of-the-art 3D at present.This mixing isomery NAND type is solid
State hard disc structure combines that SLC NAND access speed is fast, resistance to writes that the service life is long, low in energy consumption and MLC NAND and 3D stack NAND
Advantage at low cost, capacity is big, application range will more extensively.
I/O characteristic and the disk of nand flash memory are very different, firstly, flash memory, other than read-write, there are also additional wipings
Except operation, and reading and writing is unit with page (Page, typical page size are 2KB or 4KB), and wiping must be with a physical block
(Block, typical sizes are 64 pages) is unit.Therefore the erasing operation on flash memory is much slower than read-write operation, and required time exists
Millisecond rank.In addition, the characteristic that flash memory cannot be rewritten in situ to take transposition to update currently based on the solid state hard disk of flash memory
Data renewal mechanism.In order to flash memory be abstracted into the block device of look-alike disk, is needed to the physical characteristic of upper layer shielding flash memory
Specific flash memory storage management.Academic circles at present mainly uses flash translation layer (FTL) (FTL) to carry out storage management NAND flash memory equipment.It dodges
Depositing conversion layer can be directly fixed in control chip in a manner of firmware, be mostly integrated in SSD equipment on the market at present
The FTL algorithm of each manufacturer oneself, can not change.Functionally, flash translation layer (FTL) needs to realize logical address to physical address
Mapping, space distribution, garbage reclamation and abrasion equilibrium etc..Power down in order to prevent, the mapping from logical address to physical address
Table (Mapping Table) needs to store into non-volatile media, and most simple most practical method is just stored in flash memory
In each memory block, but mapping block itself updates the erasing times of block where very frequently will cause mapping table much higher than it
His memory block, wear-leveling algorithm will be periodically by mapping table data copy into the less memory block of other erasing times, this
Kind copy procedure further results in the reduction in flash memory storage service life.
Therefore it provides a kind of novel mixing isomery NAND solid state hard disk is become with solving the defects such as above-mentioned endurance life is low
Those skilled in the art are dedicated to the direction of research.
Summary of the invention
In view of the above problems, it the invention discloses a kind of mixing isomery NAND solid state hard disk, is mainly based upon
SLC Flash erase-write cycles are higher than the characteristics of MLC flash and 3D flash memory, are stored in isomery solid state hard disk and are owned using SLC Flash
The mapping table of NAND chip, to improve the endurance life of mixing isomery NAND solid state hard disk, specific technical side on the whole
Case are as follows:
A kind of mixing isomery NAND solid state hard disk, wherein include:
Stored logic controller；
Several NAND memory chip groups, several NAND memory chip groups are divided into N number of rank, and M grades of NAND
The data that the data storage access speed of memory chip group is greater than M+1 grades of NAND memory chip groups store access speed,
The data holding ability of M grades of NAND memory chip groups and resistance to write the number that the service life is better than M+1 grades of NAND memory chip groups
According to holding capacity and resistance to write the service life；
Address storaging unit, the first order NAND memory chip group being set in several NAND memory chip groups
In, and connect with the stored logic controller；
Wherein, each NAND in several NAND memory chip groups is stored in the address storaging unit to deposit
Logical address corresponding to memory chip group is to the mapping table of physical address, and N, M are positive integer, and 0 < M < N.
Preferably, above-mentioned mixing isomery NAND solid state hard disk, wherein the stored logic controller is used for described the
The logical address stored in level-one NAND memory chip group to physical address mapping table carry out read operation, update operation or
Reconstruction operation.
Preferably, above-mentioned mixing isomery NAND solid state hard disk, wherein the mixing isomery NAND solid state hard disk is also integrated
There is a buffer, the stored logic controller is by the buffer to being stored in the first order NAND memory chip group
The mapping table of logical address to physical address carry out the reconstruction operation.
Preferably, above-mentioned mixing isomery NAND solid state hard disk, wherein the reconstruction operation step includes:
The mixing isomery NAND solid state hard disk power on after by the stored logic controller start firmware program；
The stored logic controller reads the logical address to physics from the first order NAND memory chip group
The map information of address completes the reconstruction operation into the buffer.
Preferably, above-mentioned mixing isomery NAND solid state hard disk, wherein the first order where the address storaging unit
NAND memory chip group and the stored logic controller are integrated on the system-level control chip of SoC.
Preferably, above-mentioned mixing isomery NAND solid state hard disk, wherein the first order where the address storaging unit
Each memory cell structure is all made of Gate Last two dimension NAND metal gate process in NAND memory chip group.
Preferably, above-mentioned mixing isomery NAND solid state hard disk, wherein the first order where the address storaging unit
NAND memory chip group and the stored logic controller are integrated in described by Gate Last two dimension NAND metal gate process
On the system-level control chip of SoC.
Preferably, above-mentioned mixing isomery NAND solid state hard disk, wherein in several NAND memory chip groups
Level-one NAND memory chip group is a single layer cell NAND chip group, and K grades of NAND memory chip groups are every unit
Lbit multilevel-cell NAND chip group, N grades of NAND memory chip groups are that 3D stacks NAND chip group；
Wherein, K, L are positive integer, and 1 < K < N, 1 < L.
Preferably, above-mentioned mixing isomery NAND solid state hard disk, wherein be stored in the address storaging unit described mixed
Close firmware program, algorithm in conversion layer, garbage collection algorithms and the loss equalizing algorithm of isomery NAND solid state hard disk.
Above-mentioned technical proposal have the following advantages that or the utility model has the advantages that
The invention discloses a kind of mixing isomery NAND solid hard disks, by stored logic controller and multiple NAND chip groups
The characteristics of constituting, being higher than MLC flash and 3D flash memory based on SLC Flash erase-write cycles, isomery solid-state is stored using SLC Flash
The mapping table of all NAND chips on hard disk, to improve the endurance life of mixing isomery NAND solid state hard disk on the whole, improve
To the reading speed of mapping table, renewal speed and speed is rebuild, reduces the reading and update to mapping table to a certain extent
Loss.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in all the attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the gist of the present invention.
Fig. 1 is the structural schematic diagram of conventional hybrid isomery NAND solid hard disk；
Fig. 2 is N grades of NAND groups of memory chips mapping table storage schematic diagrames of tradition；
Fig. 3 is the structural schematic diagram that isomery NAND solid hard disk is mixed in the present invention；
Fig. 4 is that mapping table rebuilds flow diagram in the present invention；
Fig. 5 is the structural schematic diagram that mapping table is stored in conventional hybrid isomery NAND solid hard disk；
Fig. 6 is the structural schematic diagram of the mixing isomery NAND solid hard disk in the embodiment of the present invention one；
Fig. 7 is the structural schematic diagram of the mixing isomery NAND solid hard disk in the embodiment of the present invention two.
Specific embodiment
The present invention is further illustrated with specific embodiment with reference to the accompanying drawing, but not as limit of the invention
It is fixed.
Embodiment one:
Mapping table in traditional nand flash memory conversion layer is stored in the memory block in each NAND chip, with N grades
(N grades of NAND memory chip groups are by NAND chip 0, NAND chip 1 ... NAND chip n group for NAND memory chip group
At), as shown in Fig. 2, logical address can be stored in the chip in each NAND chip to the mapping table of physical address.The present invention
It proposes a kind of mixing isomery NAND solid state hard disk, the mapping table of logical address in all NAND chips to physical address is all deposited
It stores up in the memory block in first order NAND memory chip group.
Specifically, mixing isomery NAND solid state hard disk of the invention mainly includes stored logic controller, patrols with storage
Collect several NAND memory chip groups and address storaging unit of controller connection, wherein address storaging unit is set to first
In grade NAND memory chip group, which is broadly divided into N number of grade.
It the data holding ability of NAND chip in M grades of memory chip groups and resistance to write the service life and is better than M+1 grades
The data holding ability of NAND chip in NAND memory chip group and it is resistance to write the service life, and in M grades of memory chip groups
NAND chip is less than the NAND chip in M+1 grades of NAND memory chip groups to the operation power consumption of same size unit, and
NAND chip in M grades of NAND memory chip groups will be faster than M+ to the read-write of same size unit or storage access speed
Read-write or storage access speed of the NAND chip to same size unit in 1 grade of NAND memory chip group, wherein N and M are equal
For positive integer, and 0 < M < N.
Preferably, first order NAND memory chip group is a single layer cell NAND chip group, second level NAND storage
Device chipset is that every unit 2bit multilevel-cell NAND chip K grades of NAND memory chip groups of group ... are every unit Lbit multilayer
Unit NAND chip group, N grades of NAND memory chip groups are that 3D stacks NAND chip group, wherein K, L are positive integer and 1 < K
< N, 1 < L.
Wherein, each NAND memory chip group institute in several NAND memory chip groups is stored in address storaging unit
Mapping table of the corresponding logical address to physical address.
In an alternative embodiment, address storaging unit is arranged in first in several NAND memory chip groups
Such as scheme using first order NAND memory chip group as the address storaging unit in other words in grade NAND memory chip group
Shown in 3.Therefore, first order NAND memory chip group is stored with mapping table corresponding to each NAND memory chip group.
Wherein, stored logic controller is used for the logical address stored in first order NAND memory chip group to object
The mapping table for managing address carries out read operation, updates operation or reconstruction operation, and by the logical address of all NAND chips to object
The mapping table of reason address is stored in the highest first order NAND memory chip group of erasing and writing life, there is following advantage:
1, the bulk life time of entire NAND solid state hard disk is improved.Mapping table update it is very frequent, especially for often writing
Nand memory, therefore for the higher NAND memory chip group of series, be frequently necessary under loss equalizing algorithm by
The place block copy of memory map assignments into the lower memory block of erasable number, and the higher NAND memory chip group of series compared with
For the lower chipset of series, erasing and writing life is lower, thus this frequent renewal process of mapping table can further decrease this
The service life of NAND chip in grade.Thus the mapping table of all NAND chips is stored in first order NAND chip group by the present invention
In, due to the erasable service life highest of first order NAND chip group, the longevity of entire nand memory solid state hard disk is improved on the whole
Life.
2, improve to mapping table read operation and update the speed of operation.Logical address arrives in traditional all NAND chips
The mapping table of physical address is all stored in respective chip, to being in for the higher NAND chip of series, mapping table
Reading and update also can be relatively slow.The mapping table of all NAND chip groups is stored in first order NAND memory chip by the present invention
In group, since first order NAND memory chip group will be faster than the NAND memory chip group of other grades in read or write speed,
Thus stored logic controller reads mapping table and update is rapider, and system performance is also improved.
3, the power consumption for reading and updating to mapping table is reduced.In tradition, the higher NAND memory chip group of series is read
It takes and to update its mapping table power consumption also higher.And the mapping table of all NAND chip groups is stored in the first order by the present invention
In NAND memory chip group, thus the power consumption that stored logic controller reads mapping table and updates on the whole also obtains maximum
Limit reduces.
4, the time for accelerating mapping table reconstruction, the data reliability of mapping table is enhanced.When NAND solid state hard disk powers on
When starting or restarting after a power failure, need to extract map information from each physical block with reconstructed mapped table.Institute of the present invention
There is the mapping table of NAND chip group to be all stored in first order NAND memory chip group, for first order NAND memory chip
For group, reading speed is most fast, thus stored logic controller of the present invention can quickly reconstructed mapped table, raising be systemic
Energy.Further, since the NAND chip in first order NAND memory chip group will be better than other grades in terms of data reliability
The data reliability of NAND chip in not, mapping table is also further strengthened.
It is as shown in Figure 4 by the mapping table reconstruction process of logical address to physical address in the present invention；Isomery is mixed first
Stored logic controller starts firmware program after NAND solid state hard disk powers on；Later, stored logic controller is from the first order
Logical address is read in NAND memory chip group (address storaging unit), and to the mapping table of physical address, (hereinafter referred to as address is reflected
Firing table) information to mixing isomery NAND solid state hard disk in buffer in, complete the reconstruction operation of address mapping table.
In stored logic controller start firmware program；Later, stored logic controller is from first order nand memory
It is read in the buffer that map information is integrated into stored logic controller in chipset (address storaging unit), it is slow by this
It rushes device and carries out reconstructed mapped table.
The structure of traditional mixing isomery NAND solid state hard disk as shown in Figure 5, Fig. 6 is that the mixing in the embodiment of the present invention is different
The structural schematic diagram of structure NAND solid hard disk, Fig. 6 are to be based on being changed on the basis of Fig. 5, mainly include the first order
NAND memory chip group, second level NAND memory chip group, third level NAND memory chip group and fourth stage NAND are deposited
(traditional mixing isomery NAND solid state hard disk NAND memory chip group correspondences at different levels are stored with address mapping table to memory chip group
1, address mapping table 2, address mapping table 3 and address mapping table 4).
Wherein, first order NAND memory chip group is that (i.e. equivalent above-mentioned address stores single SLC NAND chip group
Member), second level NAND memory chip group is every unit 2bit MLC NAND chip group, third level NAND memory chip group
For every unit 3bit MLC NAND chip group, fourth stage NAND memory chip group is that 3D stacks NAND chip group.
As shown in figure 5, the durable erasing and writing life of NAND chip group constantly reduces as series increases, reading speed is not yet
Disconnected to reduce, reading power consumption is increasing, and the mapping table of every level-one logical address to physical address is all stored in respective chipset
Interior, controller reads map information by interface (1), (2), (3), (4), reading for respective mapping table and update by
In series difference, speed, power consumption are different, have an impact to the performance of entire NAND chip group.The present invention is used institute
There is the mapping table (including mapping table 1, mapping table 2, mapping table 3 and mapping table 4) of NAND chip group to be maintained in first order SLC
In NAND chip, as shown in Figure 6.Obviously, the mapping table in SLC NAND chip group is carried out read operation and updated to operate, compare
MLC NAND chip group and 3D stack NAND chip group, and power consumption is lower, and faster, the durable erasing and writing life of memory block is also more for speed
Long, the performance of entire NAND solid state hard disk is improved, and service life also will increase.
Embodiment two:
Based on embodiment one, the manufacturing process of traditional flash chip is different from logic control technique, and the two can not integrate
Onto chip piece, if utilizing metal gate process using a kind of two-dimentional NAND technique based on Gate Last metal gate process
It realizes the metal control gate of each NAND cell, i.e., is each deposited in the first order NAND memory chip group where address storaging unit
Storage unit structure is all made of Gate Last two dimension NAND metal gate process, rather than traditional polysilicon surround control gate, thus
The integrated of NAND technique and high-dielectric constant metal grid CMOS technology may be implemented, then stored logic controller and address store
Single layer cell NAND chip group where unit can be integrated in a SoC by Gate Last two dimension NAND metal gate process
On system-level controller chip, one structurally variable of above-described embodiment is at structure as shown in Figure 7 as a result,.
As shown in fig. 7, structure of the invention mainly includes several grades of NAND memory chip groups, such as first order nand memory
Chipset, second level NAND memory chip group ... fourth stage NAND memory chip group.
SoC system-level controller chip, the ground for being integrated with stored logic controller and being connect with stored logic controller
Single layer cell NAND chip group where the storage unit of location is identical as first order NAND memory chip set type.
Logical address is stored in several grades of NAND memory chip groups in single layer cell NAND chip group to physical address
Mapping table, stored logic controller be used for mapping table carry out read operation, update operation or reconstruction operation.
Preferably, first order NAND memory chip group is SLC NAND chip group, second level NAND memory chip group
For every unit 2bit MLC NAND chip group, third level NAND memory chip group is every unit 3bit MLC NAND chip
Group, fourth stage NAND memory chip group are that 3D stacks NAND chip group.
SLC NAND memory chip group is integrated in the system-level control chip of SOC, stored logic controller passes through interior
Portion's interface (1) can access the content of nand memory, and speed is faster.The present invention will be further by all NAND memory chip groups
Address mapping table storage to SOC it is system-level control chip in single layer cell NAND chip group on, to further speed up
The speed that mapping table is read and is updated.If SLC NAND chip pool-size is sufficiently large, this solid state hard disk can also be stored
Firmware program and algorithm, such as flash translation layer (FTL) (FTL) algorithm, garbage collection algorithms, loss equalizing algorithm etc., further speed up
The time of NAND solid state hard disk starting improves the property of flash memory without reading these data in the NAND memory block gone outside piece again
Energy.
In conclusion the invention discloses a kind of mixing isomery NAND solid hard disk, by stored logic controller and multiple
The characteristics of NAND chip group is constituted, and is higher than MLC flash and 3D flash memory based on SLC Flash erase-write cycles, is deposited using SLC Flash
It stores up the mapping table of all NAND chips in isomery solid state hard disk and is connected to stored logic controller, to improve mixing on the whole
The endurance life of isomery NAND solid state hard disk improves the reading speed to mapping table, renewal speed and rebuilds speed, certain journey
The reading to mapping table is reduced on degree and updates loss.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize the change case, this will not be repeated here.Such change case does not affect the essence of the present invention, not superfluous herein
It states.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (6)
1. a kind of mixing isomery NAND solid state hard disk characterized by comprising
Stored logic controller；
Several NAND memory chip groups, several NAND memory chip groups are divided into N number of rank, and M grades of NAND storages
The data storage access speed of device chipset is greater than the data storage access speed of M+1 grade NAND memory chip groups, and M grades
The data holding ability of NAND memory chip group and resistance to write data holding of the service life better than M+1 grade NAND memory chip groups
Ability and resistance to write the service life；
Address storaging unit is set in the first order NAND memory chip group in several NAND memory chip groups,
And connect with the stored logic controller, the first order NAND memory chip group where the address storaging unit with it is described
Stored logic controller is integrated on the system-level control chip of SoC；
Each memory cell structure is all made of GateLast two dimension NAND metal gate in the first order NAND memory chip group
Technique, and be integrated on the system-level control chip of the SoC by the Gate Last two dimension NAND metal gate process；
Wherein, each nand memory in several NAND memory chip groups is stored in the address storaging unit
Logical address corresponding to chipset is to the mapping table of physical address, and N, M are positive integer, and 0 < M < N.
2. mixing isomery NAND solid state hard disk as described in claim 1, which is characterized in that
The stored logic controller is used for the logical address stored in the first order NAND memory chip group to object
The mapping table for managing address carries out read operation, updates operation or reconstruction operation.
3. mixing isomery NAND solid state hard disk as claimed in claim 2, which is characterized in that the mixing isomery NAND solid-state is hard
Disk is also integrated with buffer, and the stored logic controller is by the buffer to the first order NAND memory chip group
The mapping table of middle stored logical address to physical address carries out the reconstruction operation.
4. mixing isomery NAND solid state hard disk as claimed in claim 3, which is characterized in that the reconstruction operation step includes:
The mixing isomery NAND solid state hard disk power on after by the stored logic controller start firmware program；
The stored logic controller reads the logical address to physical address from the first order NAND memory chip group
Map information into the buffer, complete the reconstruction operation.
5. mixing isomery NAND solid state hard disk as described in claim 1, which is characterized in that several NAND memory chips
First order NAND memory chip group in group is a single layer cell NAND chip group, and K grades of NAND memory chip groups are
Every unit Lbit multilevel-cell NAND chip group, N grades of NAND memory chip groups are that 3D stacks NAND chip group；
Wherein, K, L are positive integer, and 1 < K < N, 1 < L.
6. mixing isomery NAND solid state hard disk as described in claim 1, which is characterized in that
Firmware program, the flash translation layer (FTL) that the mixing isomery NAND solid state hard disk is stored in the address storaging unit are calculated
Method, garbage collection algorithms and loss equalizing algorithm.
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| CN105760113B (en) * | 2016-02-04 | 2019-03-22 | 西安科技大学 | High-speed processing apparatus and file management method based on nand flash memory |
| TWI606336B (en) * | 2016-04-21 | 2017-11-21 | 慧榮科技股份有限公司 | Memory device and control unit thereof, and data storage method for memory device |
| CN107765989B (en) * | 2016-08-16 | 2020-08-11 | 上海磁宇信息科技有限公司 | Storage device control chip, storage device and storage device management method |
| CN108647157B (en) * | 2018-03-14 | 2021-10-01 | 深圳忆联信息系统有限公司 | Mapping management method based on phase change memory and solid state disk |
| CN109324979B (en) * | 2018-08-20 | 2020-10-16 | 华中科技大学 | Data cache dividing method and data distribution method of 3D flash memory solid-state disk system |
| CN111104045A (en) * | 2018-10-25 | 2020-05-05 | 深圳市中兴微电子技术有限公司 | Storage control method, device, equipment and computer storage medium |
| CN110333966B (en) * | 2019-05-30 | 2022-12-13 | 河南文正电子数据处理有限公司 | Solid state disk device |
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