CN105426129A - Method for optimizing hybrid memory data storage - Google Patents
Method for optimizing hybrid memory data storage Download PDFInfo
- Publication number
- CN105426129A CN105426129A CN201510799638.0A CN201510799638A CN105426129A CN 105426129 A CN105426129 A CN 105426129A CN 201510799638 A CN201510799638 A CN 201510799638A CN 105426129 A CN105426129 A CN 105426129A
- Authority
- CN
- China
- Prior art keywords
- memory
- nand
- mixing memory
- data
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
- G06F3/0649—Lifecycle management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention relates to the field of data storage, in particular to a method for optimizing hybrid memory data storage. Data which are stored in the last one or more stages of a hybrid memory and most do not need to be frequently read and/or written are transferred into a disk or other storage devices with relatively low reading/writing speed, so that partial storage space of the hybrid memory is released for storing data most frequently read and/or written in the disk, the characteristic of high reading/writing speed of the hybrid memory is fully utilized, and the purpose of improving the performance of the hybrid memory is achieved.
Description
Technical field
The present invention relates to field of data storage, particularly relate to a kind of method optimized mixing memory data and store.
Background technology
The heart in the data, when central processing unit (CPU) needs to read data, data, from the NAND mixing memory data store organisation, import to internal memory in novel mixing memory or disk (HDD), and then pass to CPU from internal memories.Compared to traditional disk, though NAND mixing memory or novel mixing memory performance better than HDD, but the price of NAND mixing memory or novel mixing memory will far away higher than HDD.What taking cost into account the capacity of NAND mixing memory or novel mixing memory can not account for is too large, that is the capacity of NAND mixing memory or novel mixing memory will be far smaller than the density of HDD, and need the data in HDD to be transported in NAND mixing memory or novel mixing memory in order to higher performance can be obtained, therefore NAND mixing memory or novel mixing memory are easy to be filled up by data.Because in the data in the heart, no matter it is all limited for being the capacity of NAND mixing memory or novel mixing memory, and in HDD, store a large amount of data.If deposit some data least often read or write with NAND mixing memory or novel mixing memory, relative to NAND mixing memory or the little capacity of novel mixing memory, namely waste the resource of NAND mixing memory or novel mixing memory, again reduce the overall performance of NAND mixing memory or novel mixing memory.
Summary of the invention
In view of the above problems, the invention provides a kind of method optimized mixing memory data and store, leaving mixing memory afterbody in or what least needing the data conversion storage often reading and/or write in the slower disk of read or write speed or other memory devices in, thus the part storage space of release mixing memory, be used for depositing in disk the data the most frequently read and/or write, and then take full advantage of the fast characteristic of mixing memory read or write speed, reach the object of the performance improving mixing memory.
The present invention solves the problems of the technologies described above adopted technical scheme:
Optimize the method that mixing memory data store, it is characterized in that, be applied to data center, and described data center comprises mixing memory, some disks and detection statistics module, described method comprises:
Utilize described detection statistics module to obtain the store status of described mixing memory, and add up the frequency of utilization of the data stored in described mixing memory and described some disks;
If described store status reaches preset condition, then by the first data conversion storage of storing in described mixing memory to described some disks, to discharge the storage space of described mixing memory; And
By the described storage space that the second data conversion storage stored in described some disks discharges to described mixing memory;
Wherein, described first data are the data that in described mixing memory, frequency of utilization is minimum, and described second data are the data that in described some disks, frequency of utilization is the highest, and the frequency of utilization of described second data is greater than the frequency of utilization of described first data.
Preferably, above-mentioned method, wherein, described preset condition is the state that described mixing memory is tending towards being filled with.
Preferably, above-mentioned method, wherein, described mixing memory comprises NAND mixing memory and novel mixing memory.
Preferably, above-mentioned method, wherein, described NAND mixing memory comprises:
First order single layer cell type NAND chip, second level dual layer elements type NAND chip, third level three-layer unit type NAND chip, N level N layer unit type NAND chip, and afterbody 3D-NAND cake core;
Wherein, N be greater than 0 natural number.
Preferably, above-mentioned method, wherein, in described NAND mixing memory, from the first order to afterbody:
The read or write speed of described several types chip progressively reduces, and erasable number of times gradually reduces, and capacity progressively increases.
Preferably, above-mentioned method, wherein, described novel mixing memory comprises: phase transition storage, magnetic RAM, resistive formula storer and ferroelectric memory.
Preferably, above-mentioned method, wherein, described novel mixing memory comprises: upper level novel memory devices chip and next stage NAND memory chip.
Preferably, above-mentioned method, wherein, in described novel mixing memory, described NAND memory chip is above-mentioned any one or polytype NAND chip.
Preferably, above-mentioned method, wherein, in described novel mixing memory, the read or write speed of described novel memory devices chip is faster than described NAND memory chip, and erasable number of times is more than described NAND memory chip.
Preferably, above-mentioned method, wherein, in described NAND mixing memory and described novel mixing memory, controls the read-write operation of dissimilar chip by stored logic controller.
Technique scheme tool has the following advantages or beneficial effect: a kind of method optimized mixing memory data and store provided by the invention, leaving mixing memory afterbody in or what least needing the data conversion storage often reading and/or write in the slower disk of read or write speed or other memory devices in, thus the part storage space of release mixing memory, be used for depositing in disk the data the most frequently read and/or write, and then take full advantage of the fast characteristic of mixing memory read or write speed, reach the object of the performance improving mixing memory.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more apparent.Mark identical in whole accompanying drawing indicates identical part.Proportionally can not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is the structural representation of NAND mixing memory;
Fig. 2 is the structural representation of novel mixing memory;
Fig. 3 is the method flow diagram that the present invention optimizes the storage of mixing memory data;
Fig. 4 is the structural drawing of a data center in the embodiment of the present invention.
Embodiment
Below in conjunction with specific embodiment, a kind of method optimizing the storage of mixing memory data of the present invention is elaborated.
Mixing memory comprises NAND mixing memory and novel mixing memory.
NAND mixing memory that storage medium mixes is made as shown in Figure 1 with nand flash memory, the first order is single layer cell type NAND chip (SLC), the second level is dual layer elements type NAND chip (MLC), the third level is three-layer unit type NAND chip (TLC), the like, afterbody is 3D-NAND cake core, the chip of this several types is controlled to carry out read-write operation to it and perform some special algorithm by stored logic controller, such as data management, abrasion equilibrium etc.The chip relative merits of this several types are as shown in the table:
| Read or write speed | Erasable number of times | Capacity | Cost | |
| SLC | The fastest | At most | Minimum | The highest |
| MLC | Hurry up | Many | Little | High |
| TLC | Slowly | Few | Greatly | Low |
| 3D-NAND | The slowest | Minimum | Maximum | Minimum |
As seen from the above table, in NAND mixing memory, according to the order SLC of chip type, MLC, TLC, 3D-NAND, read or write speed is more and more slower, erasable number of times is also fewer and feweri, capacity is then increasing, cost is also more and more lower, the performance of NAND mixing memory chip formed in order to the chip making these dissimilar and life-span reach optimum, usually it is fast and in the single layer cell type NAND chip that erasable number of times is high that the data those users the most frequently read in use and/or write are kept at read or write speed, phase shaft user least often reads and/or the data write to be kept at read or write speed slow and in the chip of the rear stage that erasable number of times is low.
Another kind of mixing memory forms structure as shown in Figure 2 by novel memory devices chip and NAND memory chip, wherein novel memory devices chip can be phase transition storage (PCM), magnetic RAM (MRAM), resistive formula storer (RRAM), ferroelectric memorys (FeRAM) etc., NAND memory chip can be any one or polytype NAND chip in Fig. 1.In Fig. 2, novel memory devices chip and NAND memory chip are all controlled to carry out read-write operation to it and perform some special algorithm, such as data management, abrasion equilibrium etc. by stored logic controller.The relative merits of storage chip at different levels are as shown in the table:
| Read or write speed | Erasable number of times | Cost | |
| Novel memory devices chip | Hurry up | Many | High |
| NAND memory chip | Slowly | Few | Low |
As seen from the above table, it is fast that novel mixing memory chip compares NAND memory chip read or write speed, and often erasable, cost is also higher.In order to the performance and life-span that make novel mixing memory chip reach optimum, also it is fast and in erasable novel memory devices chip often that the data usually those users the most frequently read in use and/or write are kept at read or write speed, phase shaft user least often reads and/or the data write to be kept at read or write speed slow and in the NAND memory chip that erasable number of times is few.Such mixing memory utilizes respective advantage such as read or write speed fast, and capacity is large, and erasable number of times is high, meets storage system to Large Copacity, high performance requirement.
Also the i.e. SLC of the first order in NAND mixing memory, what deposit is that some are read or write data the most frequently, what the MLC of the second level and the third level, TLC deposited is the data more frequently read or write, and what deposit in 3D-NAND chip is the data not needing often to read or write.What in same novel mixing memory, novel memory devices chip was deposited is the data needing often access or upgrade, and what deposit in NAND memory chip is that some read and write the little data of number of times mostly, that is to say some data not needing often access or upgrade.
The method that in a kind of mixing memory of the heart in the data that the present invention proposes, optimization data stores, its step as shown in Figure 3, utilize detection statistics module to obtain the store status of mixing memory (comprising NAND mixing memory and novel mixing memory), and add up the frequency of utilization of the data stored in mixing memory and some disks; If store status reaches preset condition, then by the first data conversion storage of storing in mixing memory to some disks, to discharge the storage space of mixing memory; And by storage space that the second data conversion storage stored in some disks discharges to mixing memory; Wherein, the first data are the data that in mixing memory, frequency of utilization is minimum, and the second data are the data that in some disks, frequency of utilization is the highest, and the frequency of utilization of the second data is greater than the frequency of utilization of the first data.
Preferably, above-mentioned preset condition is the state that mixing memory is tending towards being filled with, 80% of such as mixing memory or 90% and above storage space in deposited data, then judge that this mixing memory is tending towards being filled with.
Below in conjunction with a specific embodiment and accompanying drawing, the method that optimization data in the mixing memory of the heart in the data of the present invention stores is elaborated.
As shown in Figure 4, a simple data center, suppose by a NAND mixing memory (being made up of chip SLC, MLC, TLC and the 3D-NAND shown in figure), a novel mixing memory (being made up of the novel memory devices chip shown in figure and NAND memory chip) and H (H be greater than 0 natural number) individual disk (as shown in FIG. disk 1 ~ disk H) forms.NAND mixing memory, the capacity of novel mixing memory and each disk is M (M>0), and in the capacity of the memory chip (3D-NAND) of NAND mixing memory afterbody or novel mixing memory, the capacity of NAND memory chip is N (M>N>0).When system (the detection statistics module namely mentioned in said method) detects that NAND mixing memory or novel mixing memory store data are full or will expire (also namely reaching preset condition), system is according to internal record, data (being also the first data) minimum for the access times deposited in NAND memory chip in the memory chip of NAND mixing memory afterbody or novel mixing memory are dumped in disk 1, make the memory chip of NAND mixing memory afterbody (3D-NAND) release NAND memory chip in the space of P or novel mixing memory and release the space of Q.Then system is according to recording reading in disk 2 or write data Z (the second data) to be the most frequently stored in the storage space of NAND mixing memory or the release of novel mixing memory, wherein Z≤P+Q.When system visits again data Z next time, just can access from NAND mixing memory or novel mixing memory, faster more than access from disk, thus improve the performance of whole storage system.
In sum, the invention provides a kind of method optimized mixing memory data and store, leaving mixing memory afterbody in or what least needing the data conversion storage often reading and/or write in the slower disk of read or write speed or other memory devices in, thus the part storage space of release mixing memory, be used for depositing in disk the data the most frequently read and/or write, and then take full advantage of the fast characteristic of mixing memory read or write speed, reach the object of the performance improving mixing memory.
It should be appreciated by those skilled in the art that those skilled in the art are realizing described change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. optimize the method that mixing memory data store, it is characterized in that, be applied to data center, and described data center comprises mixing memory, some disks and detection statistics module, described method comprises:
Utilize described detection statistics module to obtain the store status of described mixing memory, and add up the frequency of utilization of the data stored in described mixing memory and described some disks;
If described store status reaches preset condition, then by the first data conversion storage of storing in described mixing memory to described some disks, to discharge the storage space of described mixing memory; And
By the described storage space that the second data conversion storage stored in described some disks discharges to described mixing memory;
Wherein, described first data are the data that in described mixing memory, frequency of utilization is minimum, and described second data are the data that in described some disks, frequency of utilization is the highest, and the frequency of utilization of described second data is greater than the frequency of utilization of described first data.
2. the method for claim 1, is characterized in that, described preset condition is the state that described mixing memory is tending towards being filled with.
3. the method for claim 1, is characterized in that, described mixing memory comprises NAND mixing memory and novel mixing memory.
4. method as claimed in claim 3, it is characterized in that, described NAND mixing memory comprises:
First order single layer cell type NAND chip, second level dual layer elements type NAND chip, third level three-layer unit type NAND chip, N level N layer unit type NAND chip, and afterbody 3D-NAND cake core;
Wherein, N be greater than 0 natural number.
5. method as claimed in claim 4, is characterized in that, in described NAND mixing memory, from the first order to afterbody:
The read or write speed of described several types chip progressively reduces, and erasable number of times gradually reduces, and capacity progressively increases.
6. method as claimed in claim 3, it is characterized in that, described novel mixing memory comprises: phase transition storage, magnetic RAM, resistive formula storer and ferroelectric memory.
7. method as claimed in claim 3, it is characterized in that, described novel mixing memory comprises: upper level novel memory devices chip and next stage NAND memory chip.
8. method as claimed in claim 7, is characterized in that, in described novel mixing memory, described NAND memory chip is any one or polytype NAND chip according to claim 4.
9. method as claimed in claim 8, it is characterized in that, in described novel mixing memory, the read or write speed of described novel memory devices chip is faster than described NAND memory chip, and erasable number of times is more than described NAND memory chip.
10. method as claimed in claim 3, is characterized in that, in described NAND mixing memory and described novel mixing memory, controls the read-write operation of dissimilar chip by stored logic controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510799638.0A CN105426129A (en) | 2015-11-18 | 2015-11-18 | Method for optimizing hybrid memory data storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510799638.0A CN105426129A (en) | 2015-11-18 | 2015-11-18 | Method for optimizing hybrid memory data storage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105426129A true CN105426129A (en) | 2016-03-23 |
Family
ID=55504362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510799638.0A Pending CN105426129A (en) | 2015-11-18 | 2015-11-18 | Method for optimizing hybrid memory data storage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105426129A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108984148A (en) * | 2018-06-13 | 2018-12-11 | 浙江大华技术股份有限公司 | A kind of method and memory of the data storage based on synchronization fifo memory |
| CN109741777A (en) * | 2018-12-28 | 2019-05-10 | 上海新储集成电路有限公司 | A kind of memory for improving speed and keeping data time |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100057632A1 (en) * | 2000-01-31 | 2010-03-04 | Emiko Kamano | Questionnaire research system |
| CN103186350A (en) * | 2011-12-31 | 2013-07-03 | 北京快网科技有限公司 | Hybrid storage system and hot spot data block migration method |
| CN103701916A (en) * | 2013-12-31 | 2014-04-02 | 赛凡信息科技（厦门）有限公司 | Dynamic load balancing method of distributed storage system |
| CN104679661A (en) * | 2013-11-27 | 2015-06-03 | 阿里巴巴集团控股有限公司 | Hybrid memory control method and hybrid memory system |
| CN104866246A (en) * | 2015-06-05 | 2015-08-26 | 上海新储集成电路有限公司 | Solid state hybrid drive |
-
2015
- 2015-11-18 CN CN201510799638.0A patent/CN105426129A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100057632A1 (en) * | 2000-01-31 | 2010-03-04 | Emiko Kamano | Questionnaire research system |
| CN103186350A (en) * | 2011-12-31 | 2013-07-03 | 北京快网科技有限公司 | Hybrid storage system and hot spot data block migration method |
| CN104679661A (en) * | 2013-11-27 | 2015-06-03 | 阿里巴巴集团控股有限公司 | Hybrid memory control method and hybrid memory system |
| CN103701916A (en) * | 2013-12-31 | 2014-04-02 | 赛凡信息科技（厦门）有限公司 | Dynamic load balancing method of distributed storage system |
| CN104866246A (en) * | 2015-06-05 | 2015-08-26 | 上海新储集成电路有限公司 | Solid state hybrid drive |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108984148A (en) * | 2018-06-13 | 2018-12-11 | 浙江大华技术股份有限公司 | A kind of method and memory of the data storage based on synchronization fifo memory |
| CN108984148B (en) * | 2018-06-13 | 2020-11-06 | 浙江芯昇电子技术有限公司 | Data storage method based on synchronous FIFO memory and memory |
| CN109741777A (en) * | 2018-12-28 | 2019-05-10 | 上海新储集成电路有限公司 | A kind of memory for improving speed and keeping data time |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9846542B2 (en) | Storage controller, storage device, storage system and method of operating the storage controller | |
| CN102841851B (en) | Flash memory management method and flash memory device | |
| CN103838853B (en) | Mixed file system based on different storage media | |
| US9189389B2 (en) | Memory controller and memory system | |
| US20110010489A1 (en) | Logical block management method for a flash memory and control circuit storage system using the same | |
| CN105808156A (en) | Method for writing data into solid state drive and solid state drive | |
| CN107357534A (en) | A kind of dynamic switching method and system of flash block pattern | |
| US8892812B2 (en) | Flash memory device and data writing method for a flash memory | |
| CN105278875B (en) | A kind of mixing isomery NAND solid state hard disk | |
| CN104866246A (en) | Solid state hybrid drive | |
| CN102541458B (en) | A kind of method improving data writing speed of electronic hard disk | |
| CN101419573A (en) | Storage management method, system and storage apparatus | |
| CN103049216B (en) | Solid state hard disc and data processing method, system | |
| CN102214143A (en) | Method and device for managing multilayer unit flash memory, and storage equipment | |
| CN111158579A (en) | Solid state disk and data access method thereof | |
| CN105607862A (en) | Solid state disk capable of combining DRAM (Dynamic Random Access Memory) with MRAM (Magnetic Random Access Memory) and being provided with backup power | |
| CN105205008B (en) | Reduce the method that log blocks mapping table memory source occupies in mixed-use developments algorithm | |
| CN102520885B (en) | Data management system for hybrid hard disk | |
| CN101930407B (en) | Flash memory control circuit and memory system and data transmission method thereof | |
| CN101676872A (en) | Structure of solid state disk and method for accelerating initialization thereof | |
| CN102763070B (en) | The management method of disk buffering and device | |
| CN105426129A (en) | Method for optimizing hybrid memory data storage | |
| CN101739350B (en) | Memory storage device and control method thereof | |
| CN113778907A (en) | Storage device | |
| CN105739923A (en) | Configurable data management method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160323 |