1304714 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種測試線路佈設方&，更詳而言 係有關-種似電性連接於相連之電路板與測試電°路 板間的測試用訊號線之方法。 【先前技術】 按，-般製造電路板之廠商，例如，以常見之主機板 (―Board’MB)來說’為確保所生產之主機板具備良 好之品質特性，均會在產品出麵，於該主機板上預留一 些供檢測其產品特性之待測元件，並將主機板上之各個待 測元件對應電性連接於除錯測試（Deb叫）電路板之多個測 試接點，以使該測試電路板能針對主機板進行各種除錯測 試（如：元件參數賴、產品功能測試等），藉由除錯測試 而偵測出所有可能之錯誤，以做為進行改善之根據。 请麥閱第1圖，在習知技術中，測試電路板12係以 春共板方式聯結於待測之主機板10，該測試電路板12及主 機板10間設有分界標示u。該主機板1〇上具有複數驅 、動端l〇la、1〇2a、l〇3a及與其分別對應之接收端1()lb、 i〇2b、103b;而該測試電路板12上具有複數對應於該等 驅動端101a、l〇2a、103a及接收端1〇lb、1〇肋、1〇北 之測試接點121、122、123。 佈設測試用訊號線之方法係自主機板10上之驅動端 l〇la、102a、l〇3a分別引出並佈設測試用訊號線1〇u、 102A、103A，並電性連接至與各該驅動端1〇la、1〇2a、 19319 5 1304714 103a相對應之測試接點121、122、123上；且自上述接 收h 101 b、102b、103b上亦分別引出並佈設測試用訊號 線101B、102B、103B’並電性連接至與各該接收端iQib、 102b、103b所相對應之測試接點12卜122、，123上，使 該驅動端 101a、102a、103a 及接收端 i〇ib、102b、l〇3b 分別藉由該等測試用訊號線101A、l〇2A、103A、1〇ΐβ、 102Β、103Β相互電性連接於對應之測試接點121、122、 123上。如此，則電路板1〇上之各驅動端i〇la、1〇2a、 籲103a及接收端l〇ib、l〇2b、103b與相對應之測試電路板 12上的測试接點121、12 2、12 3 ’得以透過該等測試用訊 號線 101A、102A、103A 及 101B、102B、103B 而形成完整 之導通迴路，俾以該測試電路板12對主機板1〇進行除錯 測試，以檢驗其品質特性。 惟’上述測試用訊號線之佈設方式存在有以下缺失·· 當測試電路板12對主機板10測試完畢後，若電路板 馨係無品質瑕疵且需要使用該電路板1 〇時，便不再需要共 板聯結於該電路板1〇之測試電路板12，必需沿著設於該 ,測試電路板12及主機板10間之分界標示π予以切割（例 如採用V-cut技術），自電路板1 〇及測試電路板12之頂 層切割掉部分厚度板材後，再將該測試電路板12沿著該 分界標示11折斷以脫離該電路板1 〇。 於折斷該測試電路板12後，前述測試用訊號線 101A、102A、103A 及 101B、102B、103B 亦被從中切斷。 由於電路板1 〇上之驅動端1 Ola、102a、1 〇3a與接收端 6 19319 1304714 l〇lb、102b、103b係透過該等測試用訊號線101A、102A、 103A及1 〇 1B、102B、103B而分別電性連接至測試電路板 12上之測试接點121、12 2、12 3，因此，將使該電路板 10上的驅動端l〇la、l〇2a、l〇3a與對應之接收端i〇ib、 102b、103b間之電性連接線路形成斷路。 因此，於後續使用該電路板10前必須先對該電路板 10進行重新佈線，以修復中斷之電性連接線路，使該驅 動编101a、l〇2a、103a重新電性連接於對應之接收端 • l〇lb、102b、103b。然，重新佈線需耗費相當長的工作時 間與製程成本，故效率較低。 因此，如何克服上述習知技術之缺失，進而提供一種 測試線路佈設方法，以使佈設在電路板上之驅動端及接收 端間之訊號線具獨立性，避免因折斷測試電路板而導致電 路板上之驅動端與接收端間之電性連接線路中斷，並省去 因重新佈線製程而增加之工時及製程成本，以提高效率， 肇實已成爲亟待解決之課題。 【發明内容】 鑒於上述習知技術之缺失，本發明之主要 ==舞路佈設方法，以佈設電性連接於共板相連的 =板及賴祕㈣之測試㈣料，並使佈設於電路 板上之驅動端及接收端間之訊號線路具獨 斷測試電路板而導致電 i免口折 號線中斷。 之駆動^與接收端間之訊 本發明之另一 目的係在於提供—種測試線路佈設方 19319 7 1304714 法，俾提升電路板之電性連接品質。 本發明之又一目的在於提供一種測試線路佈設方 法’俾降低產品之製造成本。 為達上述目的及其他目白勺，本發明係提供一種測試線 路佈設方法，係用於佈設電性連接於共板相連的電路板與 --測試電路板之間的測試用訊號線，其中，該電路板上具有 ··數量相對應之複數驅動端及接收端，而該測試電路板2則 设有對應數量之複數測試接點，該測試線路佈設方法係包 _括：依據驅動端及接收端之對應關係設定起始點及終點， 並根據該起始點及終點之設定於該電路板上佈設複數訊’ 號線以電性連接相對應之各該驅動端與接收端；以及分別 ^自各㈣號線m則訊號線，且分別對應電性 連接至該測試電路板上所對應之測試接點。 上述測試線路之佈設方法復可包括預先設定該電路 =驅動端、接收端及該測試電路板之測試接點間之對應 路板與測試電路板之間係具有—分界標示，以 i、該測試電路板於測試完電路板後，可沿 測試電路板折斷以脫離電路板。 ^下將5亥 %吩极4刀界私不係為一折邊劃 、’一亚不以此為限，其亦可例如為分界畫線。 ^述測試用訊號線係佈設於該電路板及測試電路板 …其他二)置二=以切割(例如採用 )自忒電路板及測試電路板之頂 掉部分厚度板材時，不會損及佈賴用訊號線，而 19319 8 1304714 •使该測咸用訊號線保持電性連接之完整性，俾以該測試電 路板對電路板進行除錯測試（Debug)工作。 再者，本發明之測試線路佈設方法，其技術特徵係於 電路板^之驅動端與其對應之接收端之間佈設訊號線，藉 由該衹娩線電性連接該驅動端與接收端，並自該訊號線上 -引出並佈設測試用訊號線，以電性連接至驅動端與接收端 ··於測試電路板上所對應之測試接點。藉此，以使佈設在電 •路板上之線路具獨立性，避免因折斷測試電路板而導致電 修路板上之驅動端與接收端間之訊號線路中斷，並省去因重 新佈線製程而增加之工時及製程成本，以提高效率。 【實施方式】 以下藉由具體實例說明本創作之實施方式，熟悉此技 藝之人士可由本說明書所揭示之内容輕易地瞭解本創作 之其他優點與功效。 ^請參閱第2Α圖及第⑼圖，係為本發明之測試線路佈 _設方法示意圖，本發明之測試線路佈設方法係可搭載於一 佈線軟體中，藉由該佈線軟體於設計一線路時，佈設電性 連接於共板相連的電路板2〇與測試電路板22之間的測試 用訊號線。 如第2Α圖所示，該電路板2〇上具有複數驅動端 201a、202a、203a及該等驅動端分別對應之接收端2〇1卜 202b、2G3b ’而該測試電路板22係對應於該等驅動端 201a、202a、203a及接收端201b、2〇2b、2〇扑具有複數 測試接點22卜222、223。且該測試電路板22係以共板 19319 9 1304714 :::結於電路板20 ’該電路板2〇 分界標示21，以因應後續製程之需要，而= ^ ^不21 “V—cut或其他切割方式，自電路板20 及測试電路板22之頂層切割掉部分厚度板材後，再將該 f試電路22板沿著該分界標㈣折斷以脫離該電路板〆 20 〇 該電路板20係例如為主機板（M〇ther B〇ard，mb)，該 驅動端201a、202a、2〇3a及接收端2〇lb、獅、2〇3/ Φ係例如為電子元件、晶片及其他線路等，該分界標示21 係為一折邊劃痕，但並不以此為限，其亦可例如一分界書 線。 ，旦 於電路板20上佈設測試用訊號線之步驟包括··藉由 佈線軟體預先設定該電路板2〇上之驅動端2〇ia、2〇2a、 203a及接收端201b、202b、203b與該測試電路板2〇上 之測试接點2 21、2 2 2、2 2 3間之對應關係，因設定對應關 ⑩係之方式係為習知佈線軟體已有之技術，故在此不再贅 述；再將該等驅動端201a、202a、203a及對應之接收端 201 b、202b、203b分別設定為電性連接於驅動端與接收 端間之訊號線的起始點及終點’並藉由佈線軟體根據起始 點及終點之設定，於電路板20上佈設電性連接於該驅動 端 201a、202a、203a 與對應之接收端 201b、202b、203b 間之訊號線201、202、203。其中，該等訊號線2(Π、202、 203係佈設於電路板20上’詳而言之，該等訊號線2〇1、 202、203均佈設於該分界標示21臨近於該電路板20之 10 19319 1304714 一側0 ^ 如此，電路板20上之驅動端201a、202a、203a及所 對應之接收端201b、202b、203b，即可藉由上述之訊號 線201、202、203而相互電性連接，並形成完整且獨立的 訊號傳輸迴路。 請參閱第2B圖，藉由佈線軟體自上述驅動端201a、 202a、203a與對應之接收端201b、202b、203b間之訊號 線201、202、203上分別引出並佈設測試用訊號線201A、 籲202A、203A以電性連接至驅動端201a、202a、203a與接 收端201b、202b、203b於測試電路板上所對應之測試接 點221、222、223。如此，該測試電路板22上之測試接 •點221、222、223即電性連接於電路板20上之驅動端 2〇la、202a、203a 及接收端 201b、202b、203b。 於本實施例中，該測試用訊號線201A、202A、203A 係佈設於該電路板20及測試電路板22之底層或臨近底層 •之佈線層上，以供廠商採用例如V-cut或其他切割方式沿 聲該分界標示21自該該電路板20及測試電路板22之頂 、層切割掉部分厚度板材後，不會損及佈設於底層或佈線層 、 上之測試用訊號線201A、202A、203A，而使該測試用訊 %線201A、202A、203A保持電性連接之完整性，俾以該 嗍試電路板22對電路板20進行除錯測試（Debug)工作。 再者，於測試電路板22對該電路板20進行測試後， 莕經確認該電路板20係無瑕疵，且需使用該電路板20 時，則該測試電路板22已完成使命且不起作用，故只需 11 19319 1304714 沿著該分界標示21將該測試電路板22折斷以脫離該電路 板20’此時該測試用訊號線201A、202A、203A即被切斷； 而電路板20上之驅動端2〇la、202a、203a與對應之接收 端201b、202b、203b間之訊號線201、202、203依然保 持完整地電性連接關係，使該電路板2〇仍可以正常運作。 本發明可避免習知技術在折斷測試電路板後，需於電 路板上進行重新佈線之缺點，免去重新佈線所需耗費之工 作時間，而提高工作效率並同時降低製程成本。 上述實施例僅為例示性說明本創作之原理及其功 政，而非用於限制本創作。任何熟習此項技藝之人士均可 在不違背本創作之精神及範疇下，對上述實施例進行修飾 與變化。因此，本創作之權利保護範圍，應以後述之申請 專利範圍為依據。 【圖式簡單說明】 第1圖係為習知技術中佈設測試用訊號線之示 圖；以及 、第2A圖及第2B圖係用以顯示本發明之測試線路佈設 去之不思圖，其中，第2 A圖係顯示於電路板上佈設複 文電性連接於驅動端與對應之接收端間的訊號線之示意 ^第2B圖係顯示自電路板之驅動端及接收端間㈣號 、、、上引出並佈設測試用訊號線，以電性連接至賴電路板 上之測試接點之示意圖。 【主要元件符號說明】 10、2Q 電路板 19319 12 1304714 101a、102a、103a、201a、202a、203a 驅動端 101b、102b、103b、201b、202b、203b 接收端 101A、102A、103A、101B、102B、103B 測試用訊號線 11、 21 分界標示 12、 22 測試電路板 121、122、123、221、222、223 測試接點 201 > 202 > 203 訊號線 201A、202A、203A 測試用訊號線1304714 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a test circuit layout device & more specifically, a related electrical connection between a connected circuit board and a test circuit board The method of testing the signal line. [Prior Art] Manufacturers who manufacture boards in general, for example, in the case of common motherboards (Board'MB), in order to ensure that the motherboards produced have good quality characteristics, they will all come out in the product. Reserve some components to be tested for detecting the characteristics of the product on the motherboard, and electrically connect each component to be tested on the motherboard to a plurality of test contacts of the debug test board. The test board can perform various debugging tests (such as component parameter dependence, product function test, etc.) on the motherboard, and all possible errors are detected by the debug test as a basis for improvement. In the prior art, the test circuit board 12 is connected to the motherboard 10 to be tested in a spring-like manner, and a boundary mark u is disposed between the test circuit board 12 and the main board 10. The motherboard 1 has a complex drive, a mobile terminal 10a, a 1a2a, a l3a, and a corresponding receiving end 1 () lb, i 〇 2b, 103b; and the test circuit board 12 has a plurality of Corresponding to the drive terminals 101a, 102a, 103a and the test terminals 121, 122, 123 of the receiving end 1 lb, 1 rib, 1 north. The method for routing the test signal line is taken from the driving terminals l〇la, 102a, and l3a on the motherboard 10, and the test signal lines 1〇u, 102A, and 103A are respectively disposed, and electrically connected to each of the drivers. The test contacts 121, 122, 123 corresponding to the terminals 1〇1a, 1〇2a, 19319 5 1304714 103a; and the test signal lines 101B, 102B are respectively drawn and arranged from the above-mentioned receiving h 101 b, 102b, 103b And 103B' is electrically connected to the test contacts 12, 122, 123 corresponding to the receiving ends iQib, 102b, 103b, so that the driving ends 101a, 102a, 103a and the receiving ends i〇ib, 102b The test signal lines 101A, 102A, 103A, 1〇ΐβ, 102Β, 103Β are electrically connected to the corresponding test contacts 121, 122, and 123, respectively. In this way, the driving terminals i〇la, 1〇2a, 103a and the receiving ends l〇ib, l〇2b, 103b on the circuit board 1 and the corresponding test contacts 121 on the test circuit board 12, 12 2, 12 3 ' can be used to form a complete conduction loop through the test signal lines 101A, 102A, 103A and 101B, 102B, 103B, and the test board 12 is used to debug the motherboard 1〇, Test its quality characteristics. However, there are the following shortcomings in the layout of the above test signal lines. When the test circuit board 12 is tested on the motherboard 10, if the circuit board is not quality and needs to use the circuit board, then it is no longer The test circuit board 12 that needs to be commonly coupled to the circuit board 1 must be cut along the boundary labeled π between the test circuit board 12 and the motherboard 10 (for example, using V-cut technology), from the circuit board. After the top layer of the test circuit board 12 has been cut off from the partial thickness plate, the test circuit board 12 is broken along the boundary mark 11 to be detached from the circuit board 1 〇. After the test circuit board 12 is broken, the test signal lines 101A, 102A, 103A and 101B, 102B, 103B are also cut off therefrom. Since the driving terminals 1 Ola, 102a, 1 〇 3a and the receiving terminals 6 19319 1304714 l 〇 lb, 102b, 103b on the circuit board 1 pass through the test signal lines 101A, 102A, 103A and 1 〇 1B, 102B, 103B is electrically connected to the test contacts 121, 12 2, and 12 3 on the test circuit board 12, respectively, so that the drive terminals l〇la, l〇2a, l〇3a on the circuit board 10 are correspondingly The electrical connection lines between the receiving ends i〇ib, 102b, and 103b form an open circuit. Therefore, the circuit board 10 must be re-routed before the subsequent use of the circuit board 10 to repair the interrupted electrical connection line, so that the drive modules 101a, 102a, 103a are electrically connected to the corresponding receiving end. • l〇lb, 102b, 103b. However, rewiring takes a considerable amount of work time and process cost, so it is less efficient. Therefore, how to overcome the above-mentioned shortcomings of the prior art, and further provide a test circuit routing method, so that the signal line disposed between the driving end and the receiving end of the circuit board is independent, and the circuit board is prevented from being broken due to breaking the test circuit board. The electrical connection between the driver and the receiver is interrupted, and the labor and process costs increased by the rewiring process are eliminated, so as to improve efficiency, compaction has become an urgent problem to be solved. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main == dance path layout method of the present invention is to lay the test (four) material electrically connected to the common board and the board (4), and to be laid on the circuit board. The signal line between the driving end and the receiving end has an independent test circuit board, which causes the electric i-free crease line to be interrupted. The other object of the present invention is to provide a test circuit layout method 19319 7 1304714 method for improving the electrical connection quality of the circuit board. It is still another object of the present invention to provide a test line routing method which reduces the manufacturing cost of the product. In order to achieve the above and other objects, the present invention provides a test circuit routing method for laying a test signal line electrically connected between a circuit board connected to a common board and a test circuit board, wherein The circuit board has a plurality of corresponding driving ends and receiving ends, and the test circuit board 2 is provided with a corresponding number of complex test contacts, and the test circuit routing method package includes: according to the driving end and the receiving end Corresponding relationship sets a starting point and an ending point, and arranges a plurality of signal lines on the circuit board according to the setting of the starting point and the ending point to electrically connect the corresponding driving end and the receiving end; and respectively (4) The number line m is a signal line, and is respectively electrically connected to the corresponding test contact on the test circuit board. The method for laying out the test circuit may include pre-setting the circuit=the drive end, the receiving end and the test board between the test circuit board and the test circuit board to have a demarcation mark, i, the test After the board is tested, the board can be broken along the test board to get rid of the board. ^Under the 5 hai, the quotation of the 4 knives is not a fold, and the one is not limited to this. It can also be drawn as a boundary. The test signal line is laid on the circuit board and the test circuit board... The other two) set two = to cut (for example, use) the self-twisting circuit board and the test circuit board to remove a part of the thickness of the board, will not damage the cloth Depending on the signal line, and 19319 8 1304714 • to maintain the integrity of the electrical connection of the salt signal line, debug the board with the test board. Furthermore, the test circuit layout method of the present invention is characterized in that a signal line is disposed between the driving end of the circuit board and the corresponding receiving end, and the driving end and the receiving end are electrically connected by the feeding line, and From the signal line, the test signal line is led out and electrically connected to the test terminal corresponding to the drive end and the receiving end on the test circuit board. Therefore, the circuit disposed on the electric circuit board is independent, and the signal line between the driving end and the receiving end of the electric circuit board is interrupted due to breaking the test circuit board, and the rewiring process is omitted. Increase the working hours and process costs to improve efficiency. [Embodiment] Hereinafter, embodiments of the present invention will be described by way of specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present specification. ^Please refer to FIG. 2 and FIG. 9 for a schematic diagram of a test circuit layout method according to the present invention. The test circuit layout method of the present invention can be mounted in a wiring software body, and the wiring software is used to design a line. The test signal line electrically connected between the circuit board 2〇 connected to the common board and the test circuit board 22 is disposed. As shown in FIG. 2, the circuit board 2 has a plurality of driving terminals 201a, 202a, and 203a, and corresponding receiving terminals 2b, 202b, and 2G3b', and the test circuit board 22 corresponds to the The drive terminals 201a, 202a, 203a and the receivers 201b, 2〇2b, 2 have a plurality of test contacts 22, 222, 223. And the test circuit board 22 is a common board 19319 9 1304714 ::: is attached to the circuit board 20 'the circuit board 2 〇 demarcation mark 21, in order to meet the needs of subsequent processes, and ^ ^ ^ not 21 "V-cut or other After cutting a part of the thickness plate from the top layer of the circuit board 20 and the test circuit board 22, the f test circuit 22 board is broken along the demarcation mark (4) to be separated from the circuit board 〆20 〇 the circuit board 20 series For example, it is a motherboard (M〇ther B〇ard, mb), and the driving terminals 201a, 202a, 2〇3a and the receiving end 2〇lb, the lion, the 2〇3/ Φ system are, for example, electronic components, chips, and other lines. The boundary mark 21 is a hem scratch, but is not limited thereto, and may be, for example, a boundary book line. The step of laying the test signal line on the circuit board 20 includes: The software pre-sets the driving terminals 2〇ia, 2〇2a, 203a and the receiving ends 201b, 202b, 203b on the circuit board 2 and the test contacts 2 21, 2 2 2, 2 on the test circuit board 2 Correspondence between 2 and 3, because the method of setting the corresponding 10 series is the existing technology of the conventional wiring software, so it is no longer here. Said driving terminals 201a, 202a, 203a and corresponding receiving ends 201 b, 202b, 203b are respectively set to be electrically connected to the start and end points of the signal line between the driving end and the receiving end and by The wiring software is disposed on the circuit board 20 according to the setting of the starting point and the end point, and the signal lines 201, 202, and 203 electrically connected between the driving ends 201a, 202a, and 203a and the corresponding receiving ends 201b, 202b, and 203b are disposed. The signal lines 2 (Π, 202, 203 are disposed on the circuit board 20). In detail, the signal lines 2〇1, 202, and 203 are disposed on the boundary board 21 adjacent to the circuit board 20. 10 19319 1304714 One side 0 ^ Thus, the driving ends 201a, 202a, 203a on the circuit board 20 and the corresponding receiving ends 201b, 202b, 203b can be electrically connected to each other by the above-mentioned signal lines 201, 202, 203. Connecting and forming a complete and independent signal transmission circuit. Referring to FIG. 2B, the wiring software 201, 202, 203 between the driving terminals 201a, 202a, 203a and the corresponding receiving terminals 201b, 202b, 203b by the wiring software. The test signal lines 201A and 2 are respectively extracted and arranged. 02A, 203A are electrically connected to the driving ends 201a, 202a, 203a and the receiving ends 201b, 202b, 203b corresponding to the test contacts 221, 222, 223 on the test circuit board. Thus, the test on the test circuit board 22 The terminals 221, 222, and 223 are electrically connected to the driving terminals 2a, 202a, and 203a and the receiving terminals 201b, 202b, and 203b on the circuit board 20. In this embodiment, the test signal lines 201A, 202A, and 203A are disposed on the bottom layer of the circuit board 20 and the test circuit board 22 or adjacent to the wiring layer of the bottom layer for the manufacturer to adopt, for example, a V-cut or other cutting. The method along the boundary mark 21 cuts off a portion of the thickness of the board from the top and the layer of the circuit board 20 and the test circuit board 22, and does not damage the test signal lines 201A, 202A disposed on the bottom layer or the wiring layer. 203A, and the test signal % lines 201A, 202A, 203A maintain the integrity of the electrical connection, and the circuit board 20 is debugged by the test circuit board 22. Moreover, after the test circuit board 22 tests the circuit board 20, it is confirmed that the circuit board 20 is flawless, and when the circuit board 20 is used, the test circuit board 22 has completed the mission and does not function. Therefore, only 11 19319 1304714 is required to break the test circuit board 22 along the boundary mark 21 to be separated from the circuit board 20'. At this time, the test signal lines 201A, 202A, 203A are cut off; The signal lines 201, 202, and 203 between the driving terminals 2a, 202a, and 203a and the corresponding receiving terminals 201b, 202b, and 203b remain in a completely electrical connection relationship, so that the circuit board 2 can still operate normally. The invention can avoid the disadvantages of the prior art that the circuit needs to be rerouted on the circuit board after breaking the test circuit board, thereby eliminating the labor time required for rewiring, thereby improving work efficiency and reducing process cost. The above embodiments are merely illustrative of the principles of the present invention and its functions, and are not intended to limit the present invention. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this creation should be based on the scope of the patent application described later. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a signal line for testing in the prior art; and FIGS. 2A and 2B are diagrams for showing the layout of the test circuit of the present invention, wherein Figure 2A shows the schematic diagram of the signal line electrically connected between the driving end and the corresponding receiving end on the circuit board. Figure 2B shows the number (4) between the driving end and the receiving end of the circuit board. The test signal line is taken up and laid out to electrically connect to the test contact on the circuit board. [Major component symbol description] 10, 2Q circuit board 19319 12 1304714 101a, 102a, 103a, 201a, 202a, 203a drive end 101b, 102b, 103b, 201b, 202b, 203b receiving end 101A, 102A, 103A, 101B, 102B, 103B test signal line 11, 21 demarcation mark 12, 22 test circuit board 121, 122, 123, 221, 222, 223 test contact 201 > 202 > 203 signal line 201A, 202A, 203A test signal line
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