CN101145168A - Test circuit layout method - Google Patents
Test circuit layout method Download PDFInfo
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- CN101145168A CN101145168A CNA2006101538229A CN200610153822A CN101145168A CN 101145168 A CN101145168 A CN 101145168A CN A2006101538229 A CNA2006101538229 A CN A2006101538229A CN 200610153822 A CN200610153822 A CN 200610153822A CN 101145168 A CN101145168 A CN 101145168A
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- circuit board
- test
- signal wire
- testing
- layout method
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Abstract
The present invention relates to a method for the layout of a testing circuit, and the method is used for the layout of a testing signal wire electrically connected between a circuit wafer and a testing circuit wafer which are connected to a common board. The circuit wafer is provided with a plurality of drive ends and receiving ends corresponding in quantity. The testing circuit wafer is provided with a plurality of testing contact points corresponding in quantity. The layout method of the testing circuit includes that a starting point and a destination are set according to the correlation of the drive ends and the receiving ends, a plurality of signal wires are arranged on the circuit wafer and electrically connected with the corresponding drive ends and the receiving ends based on the setting of the starting point and the destination; the testing signal wire extracted from each signal wire is respectively arranged on and connected with the corresponding testing contact point on the circuit wafer respectively, thereby avoiding the fact that a signal wire interruption between the drive end and the receiving end is caused due to the breaking of the testing circuit wafer in the prior art.
Description
Technical field
The present invention relates to a kind of test circuit layout method, more specifically, be electrically connected at the method for continuous circuit board and the usefulness of the test between testing circuit board signal wire about a kind of laying.
Background technology
Usually, the general manufacturer that makes circuit board, for example, with common motherboard (MotherBoard, MB), the motherboard of producing for guaranteeing possesses good quality characteristic, all can be before product export, on this motherboard, reserve some for the element under test that detects its product performance, and each element under test correspondence on the motherboard is electrically connected at a plurality of test contacts of debug test (Debug) circuit board, so that this testing circuit board can carry out various debug test (as: component parameters tests at motherboard, product function test etc.), detect all possible mistake, with as the basis of improving by debug test.
See also Fig. 1, in the prior art, testing circuit board 12 is to be linked in motherboard to be measured 10 to be total to the plate mode, and 10 of this testing circuit board 12 and motherboards are provided with boundary and indicate 11.Have many drive ends 101a, 102a, 103a and receiving end 101b, 102b, the 103b corresponding on this motherboard 10 with its difference; And have many test contacts 121,122,123 on this testing circuit board 12 corresponding to described drive end 101a, 102a, 103a and receiving end 101b, 102b, 103b.
Laying test is that drive end 101a, 102a, 103a on motherboard 10 draws and lay test usefulness signal wire 101A, 102A, 103A respectively with the method for signal wire, and is electrically connected to and respectively on this drive end 101a, the corresponding test contacts 121,122,123 of 102a, 103a; And on above-mentioned receiving end 101b, 102b, 103b, also draw and lay test signal wire 101B, 102B, 103B respectively, and be electrically connected to and respectively on the corresponding test contacts 121,122,123 of this receiving end 101b, 102b, 103b institute, this drive end 101a, 102a, 103a and receiving end 101b, 102b, 103b be electrically connected on the test contacts 121,122,123 of correspondence mutually respectively by described test with signal wire 101A, 102A, 103A, 101B, 102B, 103B.So, the test contacts 121,122,123 on each drive end 101a, 102a, 103a and receiving end 101b, 102b, 103b and the corresponding testing circuit board 12 on the circuit board 10 then, be able to form complete conducting loop with signal wire 101A, 102A, 103A and 101B, 102B, 103B by described test, thereby carry out the debug test with 12 pairs of motherboards of this testing circuit board 10, to check its quality characteristic.
But, above-mentioned test has following disappearance with the laying mode of signal wire: after 10 tests of 12 pairs of motherboards of testing circuit board finish, when if circuit board 10 is no quality defects and this circuit board 10 of needs use, just no longer need common plate to be linked in the testing circuit board 12 of this circuit board 10, must indicate 11 along the boundary of being located at 10 of this testing circuit board 12 and motherboards and be cut (for example adopting the V-cut technology), after the top layer of circuit board 10 and testing circuit board 12 cuts away segment thickness sheet material, again this testing circuit board 12 is indicated 11 along this boundary and fracture to break away from this circuit board 10.
Behind this testing circuit board 12 that fractures, aforementioned test is also therefrom cut off with signal wire 101A, 102A, 103A and 101B, 102B, 103B.Because drive end 101a, 102a, 103a and receiving end 101b, 102b, 103b on the circuit board 10 are electrically connected to test contacts 121,122,123 on the testing circuit board 12 respectively by described test with signal wire 101A, 102A, 103A and 101B, 102B, 103B, therefore, with being formed, drive end 101a, 102a on this circuit board 10,103a and corresponding receiving end 101b, 102b, electric connection circuit between 103b open circuit.
Therefore, before this circuit board 10 of follow-up use, must carry out rewiring to this circuit board 10 earlier,, make this drive end 101a, 102a, 103a be electrically connected at corresponding receiving end 101b, 102b, 103b again to repair the electric connection circuit that interrupts.So, rewiring need expend quite long working time and manufacture method cost, so efficient is lower.
Therefore, how to overcome the shortcoming of above-mentioned prior art, and then provide a kind of test circuit layout method, so that be laid in drive end on the circuit board and the signal wire tool independence between receiving end, avoid causing drive end on the circuit board and the electric connection line interruption between receiving end because of the testing circuit board that fractures, and save man-hour and the manufacture method cost that increases because of the rewiring manufacture method, to raise the efficiency the real problem that needs solution that become.
Summary of the invention
Shortcoming in view of above-mentioned prior art, fundamental purpose of the present invention is to provide a kind of test circuit layout method, be electrically connected at continuous circuit board of common plate and the test signal wire between testing circuit board with laying, and make the drive end that is laid on the circuit board and the signal line tool independence between receiving end, avoid interrupting because of the testing circuit board that fractures causes drive end and the signal wire between receiving end on the circuit board.
Another object of the present invention is to be to provide a kind of test circuit layout method, thereby promotes the electric connection quality of circuit board.
Another purpose of the present invention is to provide a kind of test circuit layout method, thereby reduces the manufacturing cost of product.
For reaching above-mentioned purpose and other purposes, the invention provides a kind of test circuit layout method, be used to lay and be electrically connected at circuit board that common plate links to each other and the test signal wire between the testing circuit board, wherein, have corresponding many drive ends of quantity and receiving end on this circuit board, then be provided with many test contacts of respective amount on this testing circuit board, this test circuit layout method comprises: the corresponding relation according to drive end and receiving end is set starting point and terminal point, and lays many signal wires on this circuit board to electrically connect corresponding respectively this drive end and receiving end according to being set in of this starting point and terminal point; And lay the test signal wire of drawing from this signal wire respectively respectively, and correspondence is electrically connected to pairing test contacts on this testing circuit board respectively.
The distribution method of above-mentioned measurement circuit also can comprise the corresponding relation between the test contacts of the drive end, receiving end and this testing circuit board that preestablish this circuit board.
Be to have a boundary to indicate between foregoing circuit plate and the testing circuit board, after testing circuit board, can this testing circuit board be fractureed with the breaking circuit plate along this boundary sign for this testing circuit board.It is to be a flanging cut that this boundary indicates, but not as limit, it also can for example be the boundary setting-out.
Above-mentioned test signal wire is the bottom that is laid in this circuit board and testing circuit board, put the manufacture method needs and cut (for example adopting V-cut or other cutting modes) for manufacturer's cooperation, when the top layer of this circuit board and testing circuit board cuts away segment thickness sheet material, can not undermine cloth test signal wire, and make this test keep the integrality of electric connection, thereby circuit board is carried out debug test (Debug) work with this testing circuit board with signal wire.
Moreover, test circuit layout method of the present invention, its technical characterictic is a laying signal wire between the receiving end corresponding with it of the drive end on the circuit board, electrically connect this drive end and receiving end by this signal wire, and draw and lay test certainly on this signal wire and use signal wire, to be electrically connected to drive end and receiving end pairing test contacts on testing circuit board.Thus, so that be laid in circuit tool independence on the circuit board, avoid interrupting, and save man-hour and the manufacture method cost that increases because of the rewiring manufacture method, to raise the efficiency because of the testing circuit board that fractures causes drive end and the signal line between receiving end on the circuit board.
Description of drawings
Fig. 1 lays the synoptic diagram of test with signal wire in the prior art; And
Fig. 2 A and Fig. 2 B are in order to show the synoptic diagram of test circuit layout method of the present invention, wherein, Fig. 2 A is shown on the circuit board and lays the synoptic diagram that is electrically connected at the signal wire between drive end and corresponding receiving end more, Fig. 2 B shows that drawing and lay test on the drive end of circuit board and the signal wire between receiving end uses signal wire, to be electrically connected to the synoptic diagram of the test contacts on the testing circuit board.
The main element symbol description
10,20 circuit boards
101a, 102a, 103a, 201a, 202a, 203a drive end
101b, 102b, 103b, 201b, 202b, 203b receiving end
101A, 102A, 103A, 101B, 102B, 103B test signal wire
11,21 boundary indicate
12,22 testing circuit boards
121,122,123,221,222,223 test contacts
201,202,203 signal wires
201A, 202A, 203A test signal wire
Embodiment
Below by instantiation explanation embodiments of the present invention, the personage who is familiar with this skill can understand other advantages of the present invention and effect easily by the disclosed content of this instructions.
See also Fig. 2 A and Fig. 2 B, be to be test circuit layout method synoptic diagram of the present invention, test circuit layout method of the present invention is can be equipped in the wiring software,, when designing a circuit, lay and be electrically connected at continuous circuit board 20 of common plate and the test signal wire between the testing circuit board 22 by this wiring software.
Shown in Fig. 2 A, have many drive ends 201a, 202a, 203a and described drive end corresponding respectively receiving end 201b, 202b, 203b on this circuit board 20, and this testing circuit board 22 is to have many test contacts 221,222,223 corresponding to described drive end 201a, 202a, 203a and receiving end 201b, 202b, 203b.And this testing circuit board 22 is to be linked in circuit board 20 to be total to the plate mode, be provided with a boundary between this circuit board 20 and the testing circuit board 22 and indicate 21, with needs in response to follow-up manufacture method, and can indicate 21 with V-cut or other cutting modes along this boundary, after the top layer of circuit board 20 and testing circuit board 22 cuts away segment thickness sheet material, again these test circuit 22 plates are indicated 21 along this boundary and fracture to break away from this circuit board 20.
This circuit board 20 is for example to be motherboard (Mother Board, MB), this drive end 201a, 202a, 203a and receiving end 201b, 202b, 203b for example are electronic component, wafer and other circuits etc., it is to be a flanging cut that this boundary indicates 21, but not as limit, it is a for example boundary setting-out also.
Comprise in laying the step of test on the circuit board 20: the corresponding relation that preestablishes 221,222,223 of test contacts on drive end 201a, 202a, 203a and receiving end 201b, 202b, 203b and this testing circuit board 20 on this circuit board 20 by wiring software with signal wire, because of the mode of setting corresponding relation is for the existing existing technology of wiring software, so do not repeat them here; Again described drive end 201a, 202a, 203a and corresponding receiving end 201b, 202b, 203b are set at starting point and the terminal point that is electrically connected at the signal wire between drive end and receiving end respectively, and, be electrically connected at this drive end 201a, 202a, 203a and corresponding receiving end 201b, 202b, signal wire 201,202,203 between 203b in laying on the circuit board 20 by the setting of wiring software according to starting point and terminal point.Wherein, described signal wire the 201,202, the 203rd is laid on the circuit board 20, and particularly, described signal wire 201,202,203 all is laid in the side that this boundary sign 21 is close in this circuit board 20.
So, drive end 201a, the 202a on the circuit board 20,203a and pairing receiving end 201b, 202b, 203b can mutually electrically connect by above-mentioned signal wire 201,202,203, and form complete and signal transmission loop independently.
See also Fig. 2 B, by wiring software on above-mentioned drive end 201a, 202a, 203a and corresponding receiving end 201b, 202b, signal wire 201,202,203 between 203b, draw respectively and lay test with signal wire 201A, 202A, 203A to be electrically connected to drive end 201a, 202a, 203a and receiving end 201b, 202b, 203b pairing test contacts 221,222,223 on testing circuit board.So, the test contacts 221,222,223 on this testing circuit board 22 promptly is electrically connected at drive end 201a, 202a, 203a and receiving end 201b, 202b, the 203b on the circuit board 20.
In present embodiment, this test signal wire 201A, 202A, 203A is laid in the bottom of this circuit board 20 and testing circuit board 22 or closes on the wiring layer of bottom, for example adopt V-cut or other cutting modes to indicate after 21 top layers from this this circuit board 20 and testing circuit board 22 cut away segment thickness sheet material for manufacturer along this boundary, can not undermine the test that is laid on bottom or wiring layer signal wire 201A, 202A, 203A, and make this test signal wire 201A, 202A, 203A keeps the integrality of electric connection, thereby carries out debug test (Debug) work with 22 pairs of circuit boards of this testing circuit board 20.
Moreover, after 22 pairs of these circuit boards 20 of testing circuit board are tested, if through confirming that this circuit board 20 is indefectible, and when needing to use this circuit board 20, then this testing circuit board 22 has been finished mission and inoperative, so only need along this boundary sign 21 this testing circuit board 22 to be fractureed to break away from this circuit board 20, this test this moment promptly is cut off with signal wire 201A, 202A, 203A; And drive end 201a, 202a on the circuit board 20,203a and corresponding receiving end 201b, 202b, the signal wire 201,202,203 between the 203b ground electrical connection that still is kept perfectly makes this circuit board 20 still can normal operation.
The present invention can avoid prior art behind the testing circuit board that fractures, and needs the shortcoming carry out rewiring on circuit board, removes the required working time of expending of rewiring from, and increases work efficiency and reduce the manufacture method cost simultaneously.
The foregoing description only is illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention should be foundation with the claim.
Claims (10)
1. test circuit layout method, be to be used to lay be electrically connected at circuit board that common plate links to each other and the test signal wire between the testing circuit board, wherein, have corresponding many drive ends of quantity and receiving end on this circuit board, then be provided with many test contacts of respective amount on this testing circuit board, this test circuit layout method comprises:
Corresponding relation according to drive end and receiving end is set starting point and terminal point, and lays many signal wires on this circuit board to electrically connect corresponding respectively this drive end and receiving end according to being set in of this starting point and terminal point; And
Lay the test signal wire of drawing respectively, and correspondence is electrically connected to pairing test contacts on this testing circuit board respectively from this signal wire respectively.
2. test circuit layout method according to claim 1 also is included in and sets before starting point and the terminal point, preestablishes the corresponding relation between the test contacts on drive end, receiving end and the testing circuit board of this circuit board.
3. test circuit layout method according to claim 1, wherein, have a boundary between this circuit board and the testing circuit board and indicate, after testing this circuit board, this testing circuit board is fractureed to break away from this circuit board along this boundary sign for this testing circuit board.
4. test circuit layout method according to claim 3, wherein, this boundary sign is one of them for boundary setting-out and flanging cut.
5. test circuit layout method according to claim 1 wherein, has a boundary and indicates between this circuit board and the testing circuit board, and this signal wire is to be laid in this circuit board to be close in the side that this boundary indicates.
6. test circuit layout method according to claim 5 wherein, fractures this testing circuit board with after breaking away from this circuit board along this boundary sign, and this signal wire keeps the integrality of electric connection.
7. test circuit layout method according to claim 1, wherein, having a boundary between this circuit board and the testing circuit board indicates, and this test signal wire is the bottom that is laid in this circuit board and testing circuit board, with when the top layer of this circuit board and testing circuit board cuts away the sheet material of segment thickness certainly, can not undermine this test and make this test keep the integrality that electrically connects with signal wire with signal wire.
8. test circuit layout method according to claim 1, wherein, this circuit board is one of them for printed circuit board (PCB), base plate for packaging and multilayer circuit board.
9. test circuit layout method according to claim 1, wherein, this circuit board is to be motherboard.
10. test circuit layout method according to claim 1 is to be applied in the wiring software, lays many signal wires and test signal wire by this wiring software.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101538229A CN101145168A (en) | 2006-09-13 | 2006-09-13 | Test circuit layout method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101538229A CN101145168A (en) | 2006-09-13 | 2006-09-13 | Test circuit layout method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101145168A true CN101145168A (en) | 2008-03-19 |
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ID=39207694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101538229A Pending CN101145168A (en) | 2006-09-13 | 2006-09-13 | Test circuit layout method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101145168A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101630657B (en) * | 2008-07-15 | 2011-04-13 | 台湾积体电路制造股份有限公司 | Integrated circuit chip and manufacturing method for integrated circuit device |
| CN103513141A (en) * | 2012-06-21 | 2014-01-15 | 国基电子（上海）有限公司 | Circuit board convenient in V-CUT quality checking and circuit board testing method thereof |
| CN112714542A (en) * | 2020-12-15 | 2021-04-27 | 苏州浪潮智能科技有限公司 | PCB (printed circuit board) test board, electronic equipment, PCB and manufacturing method thereof |
-
2006
- 2006-09-13 CN CNA2006101538229A patent/CN101145168A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101630657B (en) * | 2008-07-15 | 2011-04-13 | 台湾积体电路制造股份有限公司 | Integrated circuit chip and manufacturing method for integrated circuit device |
| CN103513141A (en) * | 2012-06-21 | 2014-01-15 | 国基电子（上海）有限公司 | Circuit board convenient in V-CUT quality checking and circuit board testing method thereof |
| CN103513141B (en) * | 2012-06-21 | 2016-08-10 | 国基电子（上海）有限公司 | It is easy to check circuit board and the circuit board detection method thereof of V-CUT quality |
| CN112714542A (en) * | 2020-12-15 | 2021-04-27 | 苏州浪潮智能科技有限公司 | PCB (printed circuit board) test board, electronic equipment, PCB and manufacturing method thereof |
| CN112714542B (en) * | 2020-12-15 | 2022-07-08 | 苏州浪潮智能科技有限公司 | PCB (printed circuit board) test board, electronic equipment, PCB and manufacturing method thereof |
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