1304645 玖、發明說明： 【發明所屬之技術領域】 本發明是有關於一種封裝方法，特別是指一種將覆晶 晶粒銲黏於基板上的銲晶方法。 5 【先前技術】 隨著電子產品的發展走向是體積愈趨輕薄短小，功能 卻更須多樣複雜，覆晶封裝（flip-chip assembly)由於具 有大幅縮減覆晶晶粒封裝後的體積，以及可降低覆晶晶粒 與基板間的電子訊號傳輸距離的優點，已成為當前極為重 10 要的封裝技術之一。 參閱圖1、圖2,一般在進行覆晶封裝之銲晶過程（chip bonding )時，是進行步驟11，以銲晶機台之流道帶動待 銲晶的基板100移動至一定位位置，並當基板100被帶動 至定位位置時，銲晶機台之定位影像擷取裝置擷取基板 15 1〇〇的影像，並依據此影像中基板100預設之二呈斜對角 設置分布的定位點（fiducial mark ) 300、300,，計算出基 板100位於定位位置時基板1〇〇之待銲晶中心400。 接著進行步驟12,銲晶機台之取晶裝置依據步驟11 中計算所得之待銲晶中心400為基準，將覆晶晶粒200定 20 置於基板100上的待銲晶位置上，並使得覆晶晶粒200上 預先形成之複數凸塊201 (bumping)對應連結於基板100 之複數接點101 (bonding pad)上。 最後進行步驟13，將銲黏有覆晶晶粒200的基板100 移送八一回銲爐（reflow oven )中進行回銲，使覆晶晶粒 1304645 200上複數凸塊201與基板100上複數接點101電性連結， 並藉由該些凸塊201與接點101的連結使覆晶晶粒200固 定連結於基板100上。 理論上來說，依步驟11所計算出來之待銲晶中心400 5 為基準，而將覆晶晶粒200定置於基板100上的待銲晶位 置，應該是可以正確地將覆晶晶粒200相對定置於基板100 上的待鲜晶位置上。 但是一來由於目前基板100會因舖覆一鮮錫層（solder layer )而遮覆預設之定位點300、300’，因此會影響定位 10 影像擷取裝置擷取基板100的影像後判讀此影像中基板 100之二定位點300、300’的實際位置，進而使得計算出的 待銲晶中心400產生偏差；二來基於人為、機台、材料（即 覆晶晶粒200、基板100本身的尺寸容許誤差）、參數調 校設定等因素共同的影響，實際上，覆晶晶粒200未能銲 15 黏於基板100上正確的待銲晶位置的發生機率大約是千分 之三。而，由於基板100上每一接點101的邊長、每一接 點101至相鄰之另一接點101的距離，以及覆晶晶粒200 上每一凸塊201的大小、每一凸塊201至相鄰之另一凸塊 201的距離大致是自數十微米至數百微米大小，一旦覆晶 20 晶粒200未能銲黏於基板100上正確的待銲晶位置時，即 會使凸塊201與接點101產生不正確地電性連結，導致銲 晶過程良率的降低。 同時，此些覆晶晶粒200未能銲黏於基板100上正確 的待銲晶位置的瑕疵品，仍會繼續後續的製程直到完成整 1304645 個封裝製程，如此，不但浪費後續各製程的生產成本，同 時也會直接導致後續每一製程的良率降低。 因此，如何把銲晶過程中覆晶晶粒2 0 0未能正確銲黏 於基板1〇0上的瑕疵品篩檢出來進行重工修正（rework)， 5 卩更加提昇銲晶良率、降低生產成本，同時減少後續製程 浪費在此等瑕疲品的封裝，提昇整體封裝製程的良率，是 業者不斷努力研究的方向。 【發明内容】 目此，本發明之目的，即在提供_種正確定位覆晶晶 1〇 纟的封裝方法，以提高覆晶封裝件之銲晶過程的良率。 本發明一種正確定位覆晶晶粒的封裝方法包含以下 步驟。 u)對應於-銲晶機台之—流道的上方裝設一視像 檢測系統。 15 (b)卩該流道帶動一基板至一輝晶位置，並將一覆 晶晶粒之-兩相鄰邊緣交會之端角區，以及該基板之至少 -定位點為-基準，經由該視像檢測系統運算分析該覆晶 晶粒定置於該基板上的位置，並進行一鲜晶步驟將該覆晶 晶粒定置於該基板上的一對應位置，而使得該覆晶晶粒與 20 該基板對應連結成—覆晶封裝件半成品。 U)以該流道帶動該步驟⑴所完成之覆晶封裝件 半成品移動’當該覆晶封裝件半成品被帶動至一檢視位置 時’該視像檢測系統擷取該覆晶封襄件半成品之影像，並 與-内建之標準影像相比對確認，以判定該覆晶晶粒是否 1304645 定置於該基板上的對應位置，且其中該内建之標準影像是 利用以該基準所建立。 本發明之功效是可以確實地篩檢出覆晶晶粒未能正 確銲黏於基板上的瑕疵品以進行返工修正，使得銲晶良率 5 提高、降低生產成本。 【實施方式】 本發明之前述以及其他技術内容、特點與優點，在以 下配合參考圖式之一較佳實施例的詳細說明中，將可清楚 的明白。 10 在本發明被詳細描述之前，要注意的是，在以下的說 明内容中，類似的元件是以相同的編號來表示。 參閱圖3，本發明之正確定位覆晶晶粒的封裝方法， 適用於覆晶封裝-覆晶封裝件的銲晶過程，使得桿晶良率 提高、降低生產成本。 15 首先進行步驟31，對應地在銲晶機台之可帶動基板 100移動之流道的上方裝設—視像檢測系統，視像檢測系 統是以感光輕合元件（CCD，Charge coupled Device)操 取'IV像並可將擷取的影像與一預先内建的標準影像作運 算分析，以比較二者的差異。 丨〇 由於視像檢測系統主要用於檢測出經過銲晶過程 =，覆晶晶粒200未能正確地定置於基板1〇〇上的覆晶封 裝件半成品的瑕疵品，因此可裝設在對應於流道之近末端 處的上方且當流道帶動覆晶晶粒200被定置於基板j 〇〇 上的覆封裝件半成品移動至一檢視位置時，可擷取此覆 1304645 晶封裝件半成品的影像，並將此影像與内建的標準影像進 行運算以分析二者的差異。 參閱圖4，視像檢測系統内建之標準影像是以覆晶晶 粒200正確地定置於基板100上待銲晶位置的覆晶封裝件 5 半成品的影像，並以覆晶晶粒200之一兩相鄰邊緣交會之 端角區202，以及基板100之一較靠近該端角區202的定 位點300二者與彼此的相對關係為依據為比較基準；並在 流道帶動銲置有覆晶晶粒200的基板100的覆晶封裝件半 成品移動至檢視位置時，擷取覆晶封裝件半成品之影像 10 後，相同地以覆晶晶粒200之一兩相鄰邊緣交會之端角區 202,以及基板100之一較靠近該端角區202的定位點300 二者與彼此的相對關係為依據，運算分析兩者的差異，以 判定覆晶晶粒200是否定置於基板100上正確的對應待銲 晶位置。 15 參閱圖3並配合參閱圖2，接著進行步驟32，與習知 銲晶過程相似，以銲晶機台之流道帶動待銲晶的基板1〇〇 移動，並當基板100被帶動至定位位置時，以銲晶機台原 本設置的定位影像擷取裝置擷取基板100之定位影像，並 依據此定位影像中基板100預設之二呈斜對角設置分布的 20 定位點300、300’，計算出基板100位於定位位置時基板 100之待銲晶中心400。 然後進行步驟33，以銲晶機台之取晶裝置依據步驟 32中計算所得之待銲晶中心400為基準，將覆晶晶粒200 定置於基板100之待銲晶位置上，並使得覆晶晶粒200上 1304645 預先形成之複數凸塊201對應連結於基板1〇〇之複數接點 ’完成一覆晶封裝件半成品。 在此要說明的是，㈣32與步驟33是覆晶封袭的鲜 晶過程，因此在量產時’此二步驟是可以獨立而一直重複 5 ㈣進行的。此外，基板刚預設之二呈斜對角設置分布 的定位點300、300,可設計配置於基板1〇〇之一銲晶區上。 然後進行步驟34,流道帶動經過步驟33銲晶完成的 覆，封裝件半成品至檢視位置，此時，視像檢測系統摘取 覆曰曰封裝件半成品的影像，並與内建之標準影像相運算分 10 析比較。 當計算比較出覆晶封裝件半成品之影像與内建標準 影像相對應吻合時，則判定此覆晶封襄件半成品符合檢測 規格，而繼續進行後續步驟35,將此覆晶封裝件半成品傳 15 送入回輝爐進行回銲，使覆晶晶粒200上複數凸塊201與 基板100上複數接點101電性連結，並藉由該些凸塊2〇1 /、接點101的連結使覆晶晶粒200固定連結於基板 上’元成銲晶過程。 *十τττ比較出覆晶封裝件半成品之影像與内建標準 2〇 料無法對應吻合時，關定此覆日^封裝件半成品為不良 ^ ’ ^時繼續進行步·驟36，停止流道作動，使覆晶封裝件 ^ 暫寺邊置於流道上，並由銲晶機台發出警示通知生 、員將此不良品取出，並在取出不良品後，繼續重複 進行上述各步驟。 接著進行步驟37，將進行至步驟36的不良品送入一 10 1304645 可以χ射線進行檢測之設備中，以人工藉由χ射線再次進 行透視檢測，以確認由視像檢測系統判定為不良品的覆晶 封裝件半成品’其覆晶晶粒20G是否正確地定置於基板⑽ 上的對應位置上，若是’則進行步驟35，將此覆晶封裝件 5 半成品傳送入回銲爐進行回銲，完成銲晶過程。 若再次檢測確認此覆晶封裝件半成品為不良品（即覆 晶晶粒200上有任-凸塊2〇1未能正確銲黏於基板刚上 的對應接點）則進行步驟38,將此不良品進行將覆晶晶粒 200與基板100兩相分離的重工修正過程，並重行自上述 10 ㈣32開始將覆晶晶粒綱定置於基板·上的各程序。 在此要另外加以說明的是，步驟36與步驟37可以配 合機台自動化，*在崎完㈣34，並敢此覆晶封裝件 半成品為不良品後，自動地將判為不良品的覆晶封裝件半 成品集中收集後以人工再次利用又射線檢測，或是直接傳 15 #入以Χ射線檢測的設備以人工再次判讀檢測，而後再將 確定的不良品進行返工修正。當然，為了減少再次檢測的 人工j本，也可以省略步驟36與37，直接將視像檢測系 統判定為不良品的覆晶封裝件半成品進行返工修正，由於 此部份過程僅為本發明之稍加修正變化，以配合實際作業 之〇 的生產需求，故不再多加詳細贅述。 ’、 由上述說明可知，本發明正確定位覆晶晶粒的封裝方1304645 发明Invention Description: TECHNICAL FIELD The present invention relates to a packaging method, and more particularly to a method of soldering a crystal on a substrate. 5 [Prior Art] With the development of electronic products, the volume is becoming thinner and lighter, and the functions are more complicated. The flip-chip assembly has a large reduction in the volume of the flip-chip package, and The advantage of reducing the distance of electronic signal transmission between the flip chip and the substrate has become one of the most important packaging technologies. Referring to FIG. 1 and FIG. 2, when the chip bonding of the flip chip package is performed, step 11 is performed to move the substrate 100 to be soldered to a positioning position by using a channel of the solder crystal machine. When the substrate 100 is driven to the positioning position, the positioning image capturing device of the soldering machine table captures the image of the substrate 15 1 , and according to the preset position of the substrate 100 in the image, the positioning points are arranged diagonally oppositely. (fiducial mark) 300, 300, calculate the crystal center 400 to be soldered of the substrate 1 when the substrate 100 is in the positioning position. Next, in step 12, the crystal pick-up device of the solder crystal machine is placed on the substrate to be soldered on the substrate 100 according to the crystal center 400 to be soldered calculated in step 11, and The plurality of bumps 201 pre-formed on the flip chip 200 are correspondingly connected to a plurality of bonding pads 101 of the substrate 100. Finally, in step 13, the substrate 100 to which the flip chip 200 is soldered is transferred to a reflow oven for reflow, so that the plurality of bumps 201 on the flip chip 1304645 200 are connected to the substrate 100. The dot 101 is electrically connected, and the flip chip 204 is fixedly coupled to the substrate 100 by the connection of the bump 201 and the contact 101. Theoretically, according to the center of the crystal to be soldered 400 5 calculated in step 11, and the position of the crystal to be soldered on the substrate 100 is determined, the flip chip 200 can be correctly It is placed on the substrate 100 at a position to be fresh. However, since the substrate 100 will cover the preset positioning points 300, 300 ′ due to the deposition of a solder layer, the positioning image 10 captures the image of the substrate 100 and then reads the image. The actual position of the two positioning points 300, 300' of the substrate 100 in the image, thereby causing the calculated center to be soldered 400 to be biased; secondly, based on the artificial, machine, and material (ie, the flip chip 200, the substrate 100 itself) The influence of the size tolerance error, the parameter adjustment setting and the like, in fact, the probability that the flip chip 200 is not soldered 15 adhered to the correct position of the substrate to be soldered on the substrate 100 is about three thousandths. The length of each contact 101 on the substrate 100, the distance from each contact 101 to another adjacent contact 101, and the size of each bump 201 on the flip chip 200, each convex The distance from the block 201 to the adjacent other bump 201 is approximately from tens of micrometers to hundreds of micrometers. Once the flip chip 20 die 200 fails to be soldered to the correct position of the substrate to be soldered on the substrate 100, The bump 201 and the contact 101 are electrically connected incorrectly, resulting in a decrease in the yield of the solder crystal process. At the same time, if the flip chip 200 is not soldered to the correct soldering position on the substrate 100, the subsequent process will continue until the entire 1,304,645 package process is completed, thus not only wasting the production of subsequent processes. The cost will also directly lead to a reduction in the yield of each subsequent process. Therefore, how to re-rake the product of the flip-chip grain 200 in the process of soldering and failing to be soldered to the substrate 1〇0 for rework, 5卩 further improve the soldering yield and reduce the production cost. At the same time, reducing the waste of subsequent processes in the packaging of such fatigue products and improving the yield of the overall packaging process is the direction that the industry is constantly striving to study. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a packaging method for correctly locating flip chip 1 〇 , to improve the yield of a solder crystal process of a flip chip package. A method of packaging a properly positioned flip chip according to the present invention comprises the following steps. u) A visual inspection system is installed above the flow path corresponding to the welding machine. 15 (b) the flow path drives a substrate to a lithode position, and an end corner region where the two adjacent edges of the flip chip are intersected, and at least the anchor point of the substrate is a reference Performing, for example, a detection system to analyze the position of the flip chip on the substrate, and performing a fresh crystal step to position the flip chip on a corresponding position on the substrate, so that the flip chip and the The substrate is correspondingly connected into a semi-finished product of a flip chip package. U) driving the flip-chip package semi-finished product completed by the step (1) by the flow channel, when the flip-chip package semi-finished product is driven to a viewing position, the visual inspection system captures the flip-chip sealing component semi-finished product The image is compared to a built-in standard image to determine if the flip chip is positioned at a corresponding location on the substrate, and wherein the built-in standard image is created using the reference. The effect of the invention is that the defects of the flip-chip crystal grains which are not properly soldered to the substrate can be surely screened for rework correction, so that the solder crystal yield 5 is increased and the production cost is lowered. The above and other technical contents, features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments. Before the present invention is described in detail, it is to be noted that in the following description, similar elements are denoted by the same reference numerals. Referring to FIG. 3, the method for correctly positioning the flip chip of the present invention is suitable for the solder crystal process of the flip chip package-Crystal chip package, so that the rod crystal yield is improved and the production cost is reduced. 15 First, step 31 is performed, correspondingly, a video detection system is installed above the flow path of the soldering machine platform that can drive the substrate 100 to move, and the visual inspection system is operated by a CCD (Charge coupled device). Take the 'IV image and analyze the captured image with a pre-built standard image to compare the differences.丨〇Because the visual inspection system is mainly used to detect the soldered crystal process=, the flip chip 200 is not correctly placed on the substrate of the flip-chip package semi-finished product, so it can be installed in the corresponding The semi-finished product of the 1304645 crystal package can be taken over the upper end of the flow channel and when the flow-passing mold-coated semi-finished product on which the flip chip 200 is placed on the substrate j 移动 is moved to a viewing position. Image and operate this image with a built-in standard image to analyze the difference between the two. Referring to FIG. 4, the standard image built in the visual inspection system is an image of the semi-finished product of the flip-chip package 5 in which the flip chip 200 is correctly positioned on the substrate 100 to be soldered, and one of the flip-chips 200 is used. The relationship between the end corner regions 202 where the two adjacent edges meet, and the positioning point 300 of one of the substrates 100 closer to the end corner region 202 are based on the comparison; and the flip-chip is mounted on the flow channel. When the flip-chip package semi-finished product of the substrate 100 of the die 200 is moved to the inspection position, after the image 10 of the flip-chip package semi-finished product is taken, the end corner region 202 where one of the two adjacent edges of the flip chip 200 meets is identically And the relative relationship between the substrate 300 and the positioning point 300 of the substrate 100 closer to the end corner region 202, and the difference between the two is calculated to determine whether the flip chip 200 is correctly placed on the substrate 100. The position of the crystal to be soldered. Referring to FIG. 3 and referring to FIG. 2, proceeding to step 32, similar to the conventional soldering process, the substrate 1 to be soldered is driven by the flow path of the solder crystal machine, and the substrate 100 is driven to the position. In the position, the positioning image capturing device originally set by the welding crystal machine platform captures the positioning image of the substrate 100, and according to the preset position of the substrate 100 in the positioning image, the positioning points 300, 300' are distributed obliquely and diagonally. Calculate the center 400 of the substrate 100 to be soldered when the substrate 100 is in the positioned position. Then, in step 33, the flip chip 200 is placed on the substrate 100 to be soldered according to the crystal center 400 to be soldered calculated in step 32, and the flip chip is formed. The pre-formed plurality of bumps 201 on the die 200 are correspondingly connected to the plurality of contacts of the substrate 1 to complete a flip chip package semi-finished product. It is to be noted that (d) 32 and step 33 are crystal-cleared fresh crystal processes, so that in the case of mass production, the two steps can be carried out independently and repeated 5 (d). In addition, the substrate has just been disposed at an obliquely diagonally disposed positioning point 300, 300, which can be designed and disposed on one of the solder crystal regions of the substrate 1 . Then, in step 34, the flow path drives the over-finishing of the package through the soldering of step 33, and the semi-finished product of the package is in the inspection position. At this time, the visual inspection system extracts the image of the semi-finished product of the encapsulation and is compared with the built-in standard image. The operation is divided into 10 comparisons. When it is calculated that the image of the semi-finished product of the flip-chip package corresponds to the built-in standard image, it is determined that the semi-finished product of the flip-chip package meets the test specification, and the subsequent step 35 is continued, and the semi-finished product of the flip-chip package is transmitted. The reflowing furnace is sent to the regenering furnace for reflowing, so that the plurality of bumps 201 on the flip chip 200 are electrically connected to the plurality of contacts 101 on the substrate 100, and the bumps are connected by the bumps 2〇1 and the contacts 101. The flip chip 200 is fixedly bonded to the substrate to form a solder crystal process. * Ten τττ compares the image of the semi-finished product of the flip-chip package with the built-in standard 2 〇 material, which is determined to be the same. If the semi-finished product of the package is defective ^ ' ^, continue the step · 36 and stop the flow The flip-chip package is placed on the flow path, and the soldering machine station sends a warning to inform the student and the person to take out the defective product, and after the defective product is taken out, the above steps are repeated. Next, in step 37, the defective product that has been sent to the step 36 is sent to a device that can detect the ray, and the fluoroscopy is manually performed again by the ray to confirm that the visual inspection system determines that the defective product is defective. The flip chip package semi-finished product 'whether the flip chip 20G is correctly positioned at the corresponding position on the substrate (10), if 'then, proceed to step 35, the semi-finished product of the flip chip package 5 is transferred into the reflow furnace for reflow, complete Soldering process. If it is confirmed again that the flip chip package semi-finished product is defective (that is, there is a corresponding bump on the flip chip 200 where the bump 2 〇 1 is not properly soldered to the substrate), then step 38 is performed. The defective product is subjected to a rework correction process of separating the flip chip 200 from the substrate 100, and repeats the procedures for placing the flip chip on the substrate from the above 10 (four) 32. It should be additionally noted that step 36 and step 37 can be combined with the machine automation, * in the end of the (four) 34, and dare to cover the semi-finished product of the package as a defective product, automatically will be judged as a defective product flip chip package After the semi-finished products are collected intensively, they are manually reused and detected by radiation, or directly passed through the equipment of the ray-ray detection by 15#, and the defective products are reworked and corrected. Of course, in order to reduce the artificial detection of the re-detection, steps 36 and 37 may be omitted, and the flip-chip package semi-finished product determined by the visual inspection system as a defective product may be directly reworked, since this part of the process is only slightly in the present invention. Add corrections to match the production needs of the actual operation, so no more detailed description will be given. As can be seen from the above description, the present invention correctly positions the package side of the flip chip.
、、上 W 要是導入目刚發展非常成熟的視像檢測技術於覆晶 封扁製程中的銲晶過程，利用感光耦合元件具有體積小、 回旦素、向解析度等優點，可以輕易擷取已定置有覆晶 11 1304645 粒200在基板loo上之覆晶封裝件半成品的影像，再與標 準影像相分析比對，以確認覆晶晶粒2〇〇是否正確地定置 於基板100上，並可將覆晶晶粒2〇〇定置位置有所偏移的 瑕疲品篩檢出來以進行再次檢測或重工修正，以提昇鲜晶 過私的良率，與習知銲晶過程相較，本發明正確定位覆晶 晶粒的封裝方法確實可以篩檢出覆晶晶粒2〇〇未正確定置 於基板100上之千分之三不良率發生的瑕疵品，進而再提 昇銲晶過程的良率，同時可避免此些瑕疵品繼續進行後續 無謂的封裝過程、浪費後續各製程生產成本的缺點，確實 達到本發明之目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 =以此限;t本發明實施之範圍，即大凡依本發明中請專利 範圍及發明說明書内容所作之簡單的等效變化與修飾，皆 應仍屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一流程圖，說明習知之銲晶過程； 士圖2疋π思圖’說明習知銲晶過程之一定位影像擷 衣置疋位出一基板之一待銲晶中心的狀態； #圖3疋一流程圖，說明本發明正確定位覆晶晶粒的封 展方法之一較佳實施例； 說明本發明正確定位覆晶晶粒的封W, if you want to introduce the very mature video detection technology in the die-casting process, the photo-coupling component has the advantages of small size, returning, resolution, etc. An image of the flip chip 11 semi-finished product of the flip chip 11 1304645 granule 200 on the substrate loo has been fixed, and then compared with the standard image phase analysis to confirm whether the flip chip 2 正确 is correctly placed on the substrate 100, and The fatigued product with the offset position of the flip-chip 2〇〇 can be screened for re-detection or rework correction to improve the yield of fresh crystals, compared with the conventional soldering process. The encapsulation method for correctly locating the flip-chip grains can indeed screen out the flip-chips 2〇〇 which are not determined to be placed on the substrate 100, and then increase the yield of the solder crystal process. At the same time, it can avoid the disadvantages that the counterfeit products continue to carry out the subsequent unnecessary packaging process and waste the subsequent production costs of the respective processes, and indeed achieve the object of the present invention. However, the above is only the preferred embodiment of the present invention, and is not limited to this; t is the scope of implementation of the present invention, that is, the simple equivalent of the scope of the patent and the contents of the invention in the present invention. Changes and modifications are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart illustrating a conventional soldering process; FIG. 2 illustrates a conventional soldering process in which one of the positioning images is placed on one of the substrates to be soldered. The state of the crystal center; FIG. 3 is a flow chart showing a preferred embodiment of the method for properly positioning the flip chip in the present invention; illustrating the correct positioning of the flip chip in the present invention
置於覆晶晶粒上的狀態。 圖4是一示意圖， 裝 12 1304645 【圖式之主要元件代表符號說明】 100 基板 13 步驟 101 接點 31 步驟 200 覆晶晶粒 32 步驟 201 凸塊 33 步驟 202、 202’ 延長線 34 步驟 203 端角區 35 步驟 300、 300’ 定位點 36 步驟 400 待銲晶中心 37 步驟 11 步驟 38 步驟 12 步驟 13A state placed on a flip chip. Figure 4 is a schematic view, with 12 1304645 [Main components of the drawings represent symbolic descriptions] 100 substrate 13 Step 101 Contact 31 Step 200 Flip chip 32 Step 201 Bump 33 Step 202, 202' Extension line 34 Step 203 Corner area 35 Step 300, 300' Positioning point 36 Step 400 To be soldered to the center 37 Step 11 Step 38 Step 12 Step 13