JP3719900B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP3719900B2
JP3719900B2 JP2000066737A JP2000066737A JP3719900B2 JP 3719900 B2 JP3719900 B2 JP 3719900B2 JP 2000066737 A JP2000066737 A JP 2000066737A JP 2000066737 A JP2000066737 A JP 2000066737A JP 3719900 B2 JP3719900 B2 JP 3719900B2
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bump
wiring board
semiconductor device
chip
semiconductor chip
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JP2001257237A (en
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浩之 平井
裕昭 小泉
知久 本村
雅弘 吉村
修 島田
義孝 福岡
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

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Description

【０００１】
【発明の属する技術分野】
この発明は、半導体チップを配線基板上にフリップチップ実装してなる半導体装置、その製造方法、実装装置及び実装方法並びにそれに用いられるフリップチップ実装用基板に関する。
【０００２】
【従来の技術】
従来より、半導体チップを配線基板上に実装する方法として、ワイヤボンディングによらず、半導体チップ側にバンプを形成し、配線基板側にパッドを形成して半導体チップを配線基板にフェースダウン方式で直接実装すると同時にバンプとパッドとを接続するフリップチップ実装方法が知られている。
【０００３】
図１２に、従来のフリップチップ実装構造を示す。同図（ａ）に示すように、半導体チップ１００の表面には、Ａｌ等からなる複数のパッド１０１が形成されており、これらのパッド１０１上にはＡｕ等からなるボールバンプ１０２が形成されている。一方、配線基板１０３の表面にも、例えばＣｕ等からなる複数のパッド１０４が半導体チップ１００のパッド１０１に対向するように配置されている。配線基板１０３上に異方性導電膜（ＡＣＦ）等の封止樹脂を配置し、半導体チップ１００のボールバンプ１０２がパッド１０４と対向するように半導体チップ１００をフェースダウンさせて加圧及び加熱することにより、ボールバンプ１０２とパッド１０４とが接合され、半導体チップ１００のフリップチップ実装が完了する。
【０００４】
上述したボールバンプ１０２としては、パッド１０１上に、例えばＣｒ−Ｃｕ−Ａｕの中間蒸着膜を形成した後、Ｐｂ，Ｓｎ等を順次蒸着して、不活性雰囲気中で加熱反応させて得られる共晶半田バンプを用いることがなされているが、蒸着法は、製造プロセスが煩雑で製造コストがかかるという問題がある。この問題を解決するため、半導体チップ１００のパッド１０１上にＡｕワイヤによるワイヤボールボンディングを施してＡｕのボールバンプ１０２を形成する方式も用いられている。
【０００５】
また、図１２（ｂ）に示すように、配線基板１０３側のパッド１０４に、例えばＡｇペースト等をスクリーン印刷法により形成してこれをバンプ１０５とする方式も提案されている。この方式は、上述した方式よりも更に製造工程を簡略化でき、高さのバラツキなども少ないという利点がある。
【０００６】
【発明が解決しようとする課題】
近年、半導体チップの小型化、配線パターンの微細化が進み、配線基板と半導体チップとの接続の信頼性向上が益々大きな課題となってきた。これに対し、上述した従来例のうち、ワイヤボールボンディングによる方法では、バンプの高さのバラツキや配線基板のうねり等の影響で接続が不安定になったり、チップそのものへのボンディング形成が困難になるという問題がある。
【０００７】
また、Ａｇバンプをスクリーン印刷により形成する方式では、ＡｇバンプとＡｌのパッドとの接合部が高湿環境下で局部電池を形成し、電気化学的腐食を起こして接続不良を発生させるという問題がある。
【０００８】
この発明は、このような問題点に鑑みてなされたもので、フリップチップ実装が微細化されても半導体チップと配線基板との接続信頼性を損なわない半導体装置、その製造方法及びそれに用いられるフリップチップ実装用基板を提供することを第１の目的とする。
この発明は、また、フリップチップ実装の際に十分な接続信頼性を確保することができる半導体装置の実装装置及び実装方法を提供することを第２の目的とする。
【０００９】
【課題を解決するための手段】
本発明に係る第１の半導体装置は、配線基板と、この配線基板上にフリップチップ方式により実装された半導体チップとを備えた半導体装置において、前記配線基板上に形成された配線基板電極と、この配線基板電極上に形成されたＡｇバンプと、このＡｇバンプが形成された配線基板電極上に形成されたＮｉ／Ａｕメッキ層と、前記半導体チップ上に形成された前記Ｎｉ／Ａｕメッキ層を介して前記Ａｇバンプと接続されるＡｌからなるチップ電極とを備えてなることを特徴とする。
【００１１】
また、本発明に係る第１の半導体装置の製造方法は、配線基板上に配線基板電極を形成する工程と、この工程で形成された配線基板電極上にＡｇバンプを形成する工程と、この工程でＡｇバンプが形成されたＣｕの配線基板電極上にＮｉメッキを施した後、Ａｕメッキを施す工程と、前記Ｎｉ／Ａｕメッキ層が表面に形成された前記Ａｇバンプと半導体チップのＡｌからなるチップ電極とを位置合わせして熱圧着することにより前記半導体チップを前記配線基板上にフリップチップ実装する工程とを備えてなることを特徴とする。
【００１２】
この発明によれば、ＡｇバンプはＮｉ／Ａｕメッキ層を介してＡｌチップ電極と接触することになるので、電池反応を抑制することができ、経時的な信頼性を高めることができる。しかも、配線基板上にＣｕの配線基板電極を形成する工程に続けてＡｇバンプを形成し、続いてＮｉ／Ａｕメッキ層を形成するようにしているので、従来の工程を殆ど変更せずに、しかもＣｕ電極が酸化する前にＡｇバンプを形成し、表面をメッキすることができるので、電極の酸化防止にも有効である。なお、ここでＡｇバンプは、例えばＡｇペーストをスクリーン印刷することによって形成されたものである。また、Ｎｉメッキ層の厚さは、望ましくは３μｍ〜５μｍであり、Ａｕメッキ層の厚さは、望ましくは０．０３μｍ以上である。
【００２７】
【発明の実施の形態】
以下、図面を参照して、この発明の実施の形態について説明する。
図１は、本発明の第１の実施形態に係る半導体装置を製造工程順に示した断面図、図２は、この半導体装置の製造工程を示すフローチャートである。
先ず、図１（ａ）に示すように、配線基板１上に、Ｃｕからなる所定の導電パターンと共に導電パッド（配線基板電極）２を形成する（Ｓ１）。続いて図１（ｂ）に示すように、導電パッド２上にＡｇペーストをスクリーン印刷して、硬化させることにより凸形状のＡｇバンプ３を形成する（Ｓ２）。次に、図１（ｃ）に示すように、Ａｇバンプ３が形成された導電パッド２にＮｉメッキを施してＮｉメッキ層４を形成し、続いてその上にＡｕメッキを施してＡｕメッキ層５を形成する（Ｓ３）。Ｎｉメッキ層４の厚みは、好適には３μｍ〜５μｍであり、Ａｕメッキ層５の厚みは、好適には０．０３μｍ以上である。なお、これらの工程は、一連のフリップチップ実装用基板の製造工程として連続的に行われることが望ましい。これにより、Ａｇバンプ３の形成と、Ｃｕの導電パッド２に対する表面酸化防止処理とを同時に実現できるからである。
【００２８】
このようにして得られたフリップチップ実装用基板に対して、次に図１（ｄ）に示すように、異方性導電膜（ＡＣＦ：Anisotropic Conductive Film）又は異方性導電ペースト（ＡＣＰ：Anisotropic Conductive Paste）からなる封止樹脂６を貼付又は塗布する（Ｓ４）。そして、図１（ｅ）に示すように、別途工程でＡｌ製の導電パッド（チップ電極）７が形成された半導体チップ８を、Ａｇバンプ３と導電パッド７とが一致するように位置合わせして熱圧着することにより、半導体装置が完成する（Ｓ５）。
【００２９】
この第１の実施形態の半導体装置及びその製造方法によれば、導電パッド２上にＡｇバンプ３を形成したのち、Ｎｉメッキ層４を下地層としてＡｕメッキ層５を形成し、半導体チップ８側の導電パッド７とを接続するようにしているので、簡易且つ安価に腐食等を防止することができ、接続信頼性を向上させることができる。そのことを証明するために、本発明者は半導体装置の高温高湿放置試験を行い、抵抗値の変化の様子を測定した。その結果を図３に示す。
【００３０】
図３（ａ）に示すように、半導体チップ８側の導電パッド７とＡｇバンプ３を直接接続した場合の試験結果によれば、試験開始から５００時間経過時位までを目処に抵抗値は増え続け（約５０ｍΩ→約８００ｍΩ）、腐食等が急激に進行することが分かり、その後も徐々にではあるが腐食し続け、接続信頼性が著しく損なわれるということが判明した。一方、図３（ｂ）に示すように、Ａｇバンプ３にＮｉメッキ層４及びＡｕメッキ層５を形成してから接続した場合の試験結果によれば、抵抗値は試験開始から１０００時間を経過しても約１００ｍΩ以下であり、腐食等による影響を受けにくいことが判明した。また、その後も非常に緩やかにしか抵抗値が増えないため、その差は歴然としたものであり、この半導体装置及びその製造方法によれば腐食等を防止し接続信頼性を向上することが確認された。
【００３１】
図４は、参考形態に係る半導体装置を示す断面図である。図４（ａ）に示す参考形態では、配線基板１１上に形成された導電パッド１２側にＡｕワイヤからなる第１のボールバンプ１３が形成され、半導体チップ１４上に形成された導電パッド１５側にＡｕワイヤからなる第２のボールバンプ１６が形成され、配線基板１１と半導体チップ１４とが、ＡＣＦ、ＡＣＰ等の封止樹脂１７によって接着されている。第１のボールバンプ１３の硬度は、第２のボールバンプ１６の硬度よりも低く、第１のボールバンプ１３の大きさは、第２ボールバンプ１６よりも大きく設定されている。
【００３２】
この参考形態によれば、硬度の低い第１のボールバンプ１３が硬度の高い第２のボールバンプ１６に食い込まれることで、バンプの高さのバラツキや基板の反りを吸収して確実な接続が得られる。第１のボールバンプ１３としては、例えば田中電子工業（株）製ＦＡタイプ（硬さ：５４Ｈｖ，φ１００μｍ）のＡｕワイヤを使用し、第２のボールバンプ１６としては、同じくＧＢタイプ（硬さ：７３Ｈｖ，φ７０μｍ）のＡｕワイヤを使用することができる。
【００３３】
図４（ｂ）は、配線基板１１側の第１のボールバンプ１８を高い硬度で小さく形成し、半導体チップ１４側の第２のボールバンプ１９を低い硬度で大きく形成した例である。この例でも、同図（ｃ）に示すように、配線基板１１と半導体チップ１４とを熱圧着したときに、第１のボールバンプ１８が第２のボールバンプ１９側に食い込むので、バンプの高さのバラツキや基板の反りを吸収して確実な接続が得られる。
【００３４】
図５は、別の参考形態に係る半導体装置を製造工程順に示す断面図である。この参考形態では、同図（ａ）に示すように、配線基板２１に導電パッド２２を形成すると共に、半導体チップ２３の導電パッド２４にワイヤボールボンディング法によりバンプ２５を形成する。但し、バンプ２５はその形状に特徴がある。この参考形態では、ボンディング時にＡｕワイヤを引きちぎってバンプ２５を形成する。このため、先端が尖った形状となっている。次に同図（ｂ）に示すように、配線基板２１の導電パッド２２上にＡＣＦ２６を貼り付ける。そして、同図（ｃ）に示すように、配線基板２１に半導体チップ２３を熱圧着により実装してバンプ２５と導電パッド２２とを接続する。
【００３５】
図６には、実際に下記表１の条件にて形成されたバンプ２５の形状が拡大表示されている。
【００３６】
【表１】

Figure 0003719900
【００３７】
なお、このバンプ２５は、松下電器製ＳＴＢボンダを使用して、日鉄マイクロメタル製Ｔ３ ２５μｍのＡｕワイヤを使用した。バンプ２５の基端部の球状部の径は６５±５μｍ、高さは８０μｍであった。
【００３８】
この参考形態によれば、バンプ２５の形状は、本発明者の実験により得られたもので先端部と球状部とを有し、先端部は尖っておりある程度の高さもあるため、バンプ２５自体の高さや配線基板、半導体チップの製品精度に多少のバラツキがあっても接続側の電極に十分接触し導通を得ることができる。また、先端部が尖っていることで、配線基板と半導体チップとを接着する封止樹脂を突き破り確実に接続することができる。従って、通常の絶縁フィルムや絶縁ペーストを使用しても導通を得ることができるため、異方性導電フィルム等の高価な絶縁樹脂を使用する必要がなく、生産コストを抑えることができる。更に、例えば高価な異方性導電フィルム等を使用した場合でも、図７に示すパッドとバンプとの接続部分の断面図からも分かるように、バンプの先端部が潰れる際に導電粒子を抱き込んで接続されるため、より確実な導通を得ることができ接続信頼性を向上することができる。ちなみに、図８に示すように、従来のバンプ２５´の形状は先端部が潰された形状であった。これはバンプ先端が平坦である方がＡＣＦの導電粒子がより捕捉し易いと考えられたためであるが、このために製品精度のバラツキ等を吸収して接続性を得ることが困難であった。また、封止樹脂の厚さや種類等により接続安定性にかなり影響を受けていた。更に、先端部を潰して接続面の面積を拡大し接続性を向上させようとしても、例えば異方性導電フィルム等の導電粒子は接続の際に接続面から離れてしまい、却って接続性を落としてしまう傾向にあるということも分かってきた。この参考例に係るバンプ２５は、これら従来の問題点を全てコストの上昇を伴わずに解決することが可能なものである。
【００３９】
は、本発明の別の参考形態に係る半導体装置を製造工程順に示す断面図である。この参考形態では、同図（ａ）に示すように、配線基板２１に導電パッド２２を形成し、ワイヤボールボンディング法によりバンプ２７を形成すると共に、半導体チップ２３の導電パッド２４を形成する。なお、バンプ２７は図５のバンプ２５と同一構造を有し、同一方法で形成されたものである。次に同図（ｂ）に示すように、配線基板２１の導電パッド２２及びバンプ２７上にＡＣＦ２６を貼り付ける。そして、同図（ｃ）に示すように、配線基板２１に半導体チップ２３を熱圧着により実装してバンプ２７と導電パッド２２とを接続する。
【００４０】
この参考形態によれば、ワイヤボールボンディングによるバンプの形成を半導体チップ側ではなく配線基板側に対して行うため、例えば半導体チップの小型化に伴うハンドリングの困難性が増大したり、半導体チップの材質がＧａＡｓのように衝撃に弱い場合であっても半導体チップと配線基板を確実に接続することができ、製造工程が簡略化されて製品歩留まりも向上することができる。なお、この参考例では、バンプ２７は図５のバンプ２５と同一構造を有し、同一方法で形成されたものであるが、本参考形態は、配線基板２１側にバンプを形成することを主眼とするものであるから、バンプの形状は、上述した形状に限定されない。
【００４１】
図１０は、一参考例に係る半導体装置の実装装置の装置構成例を示す図である。配線基板搭載テーブル３１は、その所定の位置にパッドが形成された配線基板３２を搭載する。半導体チップ支持ヘッド３３は、先端部にＡＴＣ（Auto-ToolChange Collet）３４を有し、このＡＴＣ３４でバンプが形成されたベアＩＣチップ等の半導体チップ３５をバキュームにより支持し、配線基板搭載テーブル３１の配線基板３２位置に半導体チップ３５を移動させる。半導体チップ３５と配線基板３２との精密な位置合わせは、配線基板３２の裏面側にあるＸ線発生装置３７からのＸ線照射をチップ支持ヘッド３３上部にあるＸ線撮像装置３８により撮像して行う。即ち、Ｘ線発生装置３７からのＸ線は、配線基板３２や半導体チップ３５のバンプや各電極等を透過してこれらの透過像を生成するため、この透過像をＸ線撮像装置３８にて撮像し、撮像されたバンプや各電極等の位置をモニタ装置３９により参照しながら位置合わせ実装処理部４０の位置補正制御によりチップ支持ヘッド３３に支持された半導体チップ３５の位置を微調整して半導体チップ３５と配線基板３２との位置合わせを行い、チップ支持ヘッド３３のヒータ３６により熱圧着を実行してフリップチップ実装を行う。
【００４２】
ちなみに従来の半導体実装装置では、例えばＣＣＤカメラを複数台使用して配線基板３２と半導体チップ３５のバンプや各電極等を撮像し、その複数の映像に基づきバンプ等の真の位置を演算により割り出して位置合わせを行っていたため、精度の高い位置合わせを行うことは難しく、また、実装後の接続部の様子は、ＣＣＤカメラでは撮像できなかったため検査作業を別工程で行う必要等があり、実装作業が煩雑なものとなっていた。
【００４３】
しかし、この参考例に係る半導体実装装置は、上述したようにＸ線を使用して、図１１に示すように、配線パターン、各パッド及びバンプの状態等の透過像を確認しながらバンプや各電極等の位置合わせを行うことができるため、フリップチップ実装の精度を向上することができる。しかも、Ｘ線による配線パターンの確認や実装状態の検査も同時に行うことができるため、検査作業を簡略化し製品の信頼性を高めることが可能となる。
【００４４】
【発明の効果】
以上述べたように、この発明の第１の半導体装置及び半導体装置の製造方法によれば、ＡｇバンプはＮｉ／Ａｕメッキ層を介してＡｌチップ電極と接触することになるので、電池反応を抑制することができ、経時的な信頼性を高めることができると共に、配線基板上にＣｕの配線基板電極を形成する工程に続けてＡｇバンプを形成し続いてＮｉ／Ａｕメッキ層を形成するようにしているので、従来の工程を殆ど変更せずに、しかもＣｕ電極が酸化する前にＡｇバンプを形成し表面をメッキすることができるので、電極の酸化防止にも有効であるという効果を奏する。
【図面の簡単な説明】
【図１】 この発明の第１の実施形態に係る半導体装置を製造工程順に示した断面図である。
【図２】 同半導体装置の製造工程を示すフローチャートである。
【図３】 同半導体装置の効果を説明するための図である。
【図４】 この発明の参考形態に係る半導体装置を製造工程順に示した断面図である。
【図５】 この発明の別の参考形態に係る半導体装置を製造工程順に示した断面図である。
【図６】 同半導体装置のバンプの拡大斜視図である。
【図７】 同半導体装置のバンプによる接続部の拡大図である。
【図８】 従来のワイヤボールボンディングによるバンプの拡大斜視図である。
【図９】 この発明の別の参考形態に係る半導体装置を製造工程順に示した断面図である。
【図１０】 一参考例に係る半導体装置の実装装置の一例を示す図である。
【図１１】 同実装装置で得られる画像を示す図である。
【図１２】 従来の半導体装置の断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a semiconductor chip is flip-chip mounted on a wiring substrate, a manufacturing method thereof, a mounting device and a mounting method, and a flip chip mounting substrate used therefor.
[0002]
[Prior art]
Conventionally, as a method of mounting a semiconductor chip on a wiring board, bumps are formed on the semiconductor chip side, pads are formed on the wiring board side, and the semiconductor chip is directly mounted on the wiring board in a face-down manner without using wire bonding. A flip chip mounting method in which bumps and pads are connected simultaneously with mounting is known.
[0003]
FIG. 12 shows a conventional flip chip mounting structure. As shown in FIG. 2A, a plurality of pads 101 made of Al or the like are formed on the surface of the semiconductor chip 100, and ball bumps 102 made of Au or the like are formed on these pads 101. Yes. On the other hand, a plurality of pads 104 made of, for example, Cu are also disposed on the surface of the wiring substrate 103 so as to face the pads 101 of the semiconductor chip 100. A sealing resin such as an anisotropic conductive film (ACF) is disposed on the wiring substrate 103, and the semiconductor chip 100 is faced down and pressed and heated so that the ball bumps 102 of the semiconductor chip 100 face the pads 104. As a result, the ball bumps 102 and the pads 104 are joined, and the flip chip mounting of the semiconductor chip 100 is completed.
[0004]
As the above-described ball bump 102, for example, an intermediate vapor deposition film of, for example, Cr—Cu—Au is formed on the pad 101, and then Pb, Sn, etc. are sequentially deposited and heated and reacted in an inert atmosphere. Although crystal solder bumps are used, the vapor deposition method has a problem that the manufacturing process is complicated and the manufacturing cost is high. In order to solve this problem, a method of forming Au ball bumps 102 by performing wire ball bonding with Au wires on the pads 101 of the semiconductor chip 100 is also used.
[0005]
Further, as shown in FIG. 12B, a method is proposed in which, for example, an Ag paste or the like is formed on the pad 104 on the wiring board 103 side by a screen printing method and used as a bump 105. This method has an advantage that the manufacturing process can be further simplified and there is less variation in height than the method described above.
[0006]
[Problems to be solved by the invention]
In recent years, miniaturization of semiconductor chips and miniaturization of wiring patterns have progressed, and improvement in the reliability of connection between a wiring board and a semiconductor chip has become an increasingly important issue. On the other hand, among the conventional examples described above, in the method using wire ball bonding, the connection becomes unstable due to variations in bump height, waviness of the wiring board, etc., and it is difficult to form a bond to the chip itself. There is a problem of becoming.
[0007]
Further, in the method of forming the Ag bump by screen printing, there is a problem in that the joint between the Ag bump and the Al pad forms a local battery in a high humidity environment, causing electrochemical corrosion and causing a connection failure. is there.
[0008]
The present invention has been made in view of such problems. A semiconductor device that does not impair the connection reliability between a semiconductor chip and a wiring board even if flip chip mounting is miniaturized, a manufacturing method thereof, and a flip used in the semiconductor device A first object is to provide a chip mounting substrate.
A second object of the present invention is to provide a semiconductor device mounting apparatus and mounting method capable of ensuring sufficient connection reliability in flip chip mounting.
[0009]
[Means for Solving the Problems]
A first semiconductor device according to the present invention is a semiconductor device comprising a wiring board and a semiconductor chip mounted on the wiring board by a flip chip method, a wiring board electrode formed on the wiring board, An Ag bump formed on the wiring board electrode, a Ni / Au plating layer formed on the wiring board electrode on which the Ag bump is formed, and the Ni / Au plating layer formed on the semiconductor chip. And chip electrodes made of Al connected to the Ag bumps.
[0011]
The first method for manufacturing a semiconductor device according to the present invention includes a step of forming a wiring substrate electrode on the wiring substrate, a step of forming an Ag bump on the wiring substrate electrode formed in this step, and this step. After the Ni plating is performed on the Cu wiring substrate electrode on which the Ag bump is formed, the Au plating is performed, and the Ag bump having the Ni / Au plated layer formed on the surface and the Al of the semiconductor chip. And a step of flip-chip mounting the semiconductor chip on the wiring board by aligning the chip electrode and thermocompression bonding.
[0012]
According to the present invention, the Ag bump comes into contact with the Al chip electrode through the Ni / Au plating layer, so that the battery reaction can be suppressed and the reliability over time can be improved. Moreover, since the Ag bump is formed following the process of forming the Cu wiring board electrode on the wiring board, and the Ni / Au plating layer is subsequently formed, the conventional process is hardly changed. In addition, Ag bumps can be formed before the Cu electrode is oxidized, and the surface can be plated, which is also effective for preventing oxidation of the electrode. Here, the Ag bump is formed, for example, by screen printing an Ag paste. Further, the thickness of the Ni plating layer is desirably 3 μm to 5 μm, and the thickness of the Au plating layer is desirably 0.03 μm or more.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment of the present invention in the order of the manufacturing process, and FIG. 2 is a flowchart showing the manufacturing process of the semiconductor device.
First, as shown in FIG. 1A, a conductive pad (wiring board electrode) 2 is formed on a wiring board 1 together with a predetermined conductive pattern made of Cu (S1). Subsequently, as shown in FIG. 1B, an Ag paste 3 is screen-printed on the conductive pad 2 and cured to form convex Ag bumps 3 (S2). Next, as shown in FIG. 1 (c), the Ni plating layer 4 is formed by performing Ni plating on the conductive pad 2 on which the Ag bump 3 is formed, and then Au plating is applied thereon to form the Au plating layer. 5 is formed (S3). The thickness of the Ni plating layer 4 is preferably 3 μm to 5 μm, and the thickness of the Au plating layer 5 is preferably 0.03 μm or more. Note that these steps are desirably performed continuously as a series of flip-chip mounting substrate manufacturing steps. This is because the formation of the Ag bump 3 and the surface oxidation prevention treatment for the Cu conductive pad 2 can be realized simultaneously.
[0028]
Next, as shown in FIG. 1 (d), an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP) is applied to the flip-chip mounting substrate thus obtained. A sealing resin 6 made of Conductive Paste) is pasted or applied (S4). Then, as shown in FIG. 1E, the semiconductor chip 8 on which the Al conductive pads (chip electrodes) 7 are formed in a separate process is aligned so that the Ag bumps 3 and the conductive pads 7 coincide. The semiconductor device is completed by thermocompression bonding (S5).
[0029]
According to the semiconductor device and the manufacturing method thereof of the first embodiment, after forming the Ag bump 3 on the conductive pad 2, the Au plating layer 5 is formed using the Ni plating layer 4 as a base layer, and the semiconductor chip 8 side. Since the conductive pads 7 are connected to each other, corrosion and the like can be prevented easily and inexpensively, and connection reliability can be improved. In order to prove this, the present inventor conducted a high-temperature and high-humidity storage test of the semiconductor device, and measured the state of change in the resistance value. The result is shown in FIG.
[0030]
As shown in FIG. 3A, according to the test result when the conductive pad 7 on the semiconductor chip 8 side and the Ag bump 3 are directly connected, the resistance value increases from the start of the test until about 500 hours have passed. Continuing (about 50 mΩ → about 800 mΩ), it was found that corrosion and the like proceeded rapidly, and thereafter, it gradually continued to corrode, and it was found that connection reliability was significantly impaired. On the other hand, as shown in FIG. 3B, according to the test result when the Ni plating layer 4 and the Au plating layer 5 are formed on the Ag bump 3 and then connected, the resistance value has passed 1000 hours from the start of the test. However, it was found to be about 100 mΩ or less and hardly affected by corrosion. In addition, since the resistance value increases only very slowly thereafter, the difference is obvious, and it has been confirmed that this semiconductor device and its manufacturing method prevent corrosion and improve connection reliability. It was.
[0031]
FIG. 4 is a cross-sectional view showing a semiconductor device according to a reference embodiment. Figure 4 reference embodiment shown in (a), the wiring first ball bump 13 made of Au wire on the formed conductive pad 12 side on the substrate 11 is formed, is formed on the semiconductor chip 14 has conductive pads 15 side A second ball bump 16 made of Au wire is formed on the wiring board 11, and the wiring substrate 11 and the semiconductor chip 14 are bonded by a sealing resin 17 such as ACF or ACP. The hardness of the first ball bump 13 is lower than the hardness of the second ball bump 16, and the size of the first ball bump 13 is set larger than that of the second ball bump 16.
[0032]
According to this reference form, the first ball bump 13 having a low hardness is digged into the second ball bump 16 having a high hardness, so that a reliable connection can be achieved by absorbing variations in the height of the bump and warping of the substrate. can get. For example, an FA type (hardness: 54 Hv, φ100 μm) Au wire manufactured by Tanaka Denshi Kogyo Co., Ltd. is used as the first ball bump 13, and a GB type (hardness: 73Hv, φ70 μm) Au wire can be used.
[0033]
FIG. 4B shows an example in which the first ball bump 18 on the wiring board 11 side is formed small with high hardness, and the second ball bump 19 on the semiconductor chip 14 side is formed large with low hardness. Also in this example, as shown in FIG. 5C, when the wiring board 11 and the semiconductor chip 14 are thermocompression bonded, the first ball bumps 18 bite into the second ball bumps 19 side. Reliable connection can be obtained by absorbing variations in the thickness and warping of the substrate.
[0034]
FIG. 5 is a cross-sectional view showing a semiconductor device according to another reference embodiment in the order of manufacturing steps. In this reference embodiment, as shown in FIG. 5A, conductive pads 22 are formed on the wiring substrate 21, and bumps 25 are formed on the conductive pads 24 of the semiconductor chip 23 by a wire ball bonding method. However, the bump 25 is characterized by its shape. In this reference embodiment, the bump 25 is formed by tearing the Au wire during bonding. For this reason, the tip has a sharp shape. Next, as shown in FIG. 2B, an ACF 26 is attached on the conductive pad 22 of the wiring substrate 21. Then, as shown in FIG. 3C, the semiconductor chip 23 is mounted on the wiring substrate 21 by thermocompression bonding, and the bumps 25 and the conductive pads 22 are connected.
[0035]
In FIG. 6, the shape of the bump 25 actually formed under the conditions shown in Table 1 below is enlarged and displayed.
[0036]
[Table 1]
Figure 0003719900
[0037]
In addition, this bump 25 used the Matsushita Electric STB bonder, and used the T3 25micrometer Au wire made from Nippon Steel Micrometal. The diameter of the spherical portion at the base end of the bump 25 was 65 ± 5 μm, and the height was 80 μm.
[0038]
According to this reference form, the shape of the bump 25 was obtained by the experiment of the present inventor and has a tip portion and a spherical portion. The tip portion is sharp and has a certain height, so the bump 25 itself Even if there is some variation in the product height of the wiring board, the wiring board, and the semiconductor chip, the electrodes on the connection side can be sufficiently contacted and electrical conduction can be obtained. Further, since the tip portion is sharp, the sealing resin for bonding the wiring board and the semiconductor chip can be pierced and reliably connected. Therefore, since conduction can be obtained even if a normal insulating film or insulating paste is used, it is not necessary to use an expensive insulating resin such as an anisotropic conductive film, and the production cost can be suppressed. Furthermore, even when an expensive anisotropic conductive film or the like is used, for example, as shown in the sectional view of the connection portion between the pad and the bump shown in FIG. Therefore, more reliable conduction can be obtained and connection reliability can be improved. Incidentally, as shown in FIG. 8, the shape of the conventional bump 25 ′ is a shape in which the tip is crushed. This is because it is thought that the ACF conductive particles are more easily captured when the bump tip is flat, but for this reason, it is difficult to obtain the connectivity by absorbing variations in product accuracy. Further, the connection stability was significantly affected by the thickness and type of the sealing resin. Furthermore, even if the tip portion is crushed to increase the area of the connection surface and improve the connectivity, for example, conductive particles such as an anisotropic conductive film are separated from the connection surface during connection, and the connectivity is reduced instead. It has also been found that it tends to end up. The bump 25 according to this reference example can solve all of these conventional problems without increasing the cost.
[0039]
These are sectional drawings which show the semiconductor device which concerns on another reference form of this invention in order of a manufacturing process. In this reference embodiment, as shown in FIG. 5A, conductive pads 22 are formed on a wiring board 21, bumps 27 are formed by a wire ball bonding method, and conductive pads 24 of a semiconductor chip 23 are formed. The bump 27 has the same structure as the bump 25 in FIG. 5 and is formed by the same method. Next, as shown in FIG. 2B, the ACF 26 is attached on the conductive pads 22 and the bumps 27 of the wiring board 21. Then, as shown in FIG. 3C, the semiconductor chip 23 is mounted on the wiring substrate 21 by thermocompression bonding, and the bumps 27 and the conductive pads 22 are connected.
[0040]
According to this reference form, bump formation by wire ball bonding is performed not on the semiconductor chip side but on the wiring board side, so that, for example, handling difficulty associated with downsizing of the semiconductor chip increases, and the semiconductor chip material Even when GaAs is weak against impact, the semiconductor chip and the wiring substrate can be reliably connected, the manufacturing process is simplified, and the product yield can be improved. In this reference example, the bumps 27 have the same structure as the bump 25 of Figure 5, but those that are formed by the same method, the present reference embodiment, focus forming a bump on the wiring board 21 side Therefore, the shape of the bump is not limited to the shape described above.
[0041]
FIG. 10 is a diagram illustrating a device configuration example of a semiconductor device mounting apparatus according to a reference example. The wiring board mounting table 31 mounts a wiring board 32 on which pads are formed at predetermined positions. The semiconductor chip support head 33 has an ATC (Auto-Tool Change Collet) 34 at the tip, and supports a semiconductor chip 35 such as a bare IC chip on which bumps are formed by the ATC 34 by vacuum, and The semiconductor chip 35 is moved to the position of the wiring board 32. Precise alignment between the semiconductor chip 35 and the wiring board 32 is performed by imaging X-ray irradiation from the X-ray generator 37 on the back side of the wiring board 32 with an X-ray imaging device 38 above the chip support head 33. Do. That is, the X-rays from the X-ray generator 37 are transmitted through the bumps and electrodes of the wiring substrate 32 and the semiconductor chip 35 to generate these transmitted images. The position of the semiconductor chip 35 supported by the chip support head 33 is finely adjusted by the position correction control of the alignment mounting processing unit 40 while taking an image and referring to the position of the imaged bump and each electrode by the monitor device 39. The semiconductor chip 35 and the wiring board 32 are aligned, and flip-chip mounting is performed by performing thermocompression bonding with the heater 36 of the chip support head 33.
[0042]
Incidentally, in a conventional semiconductor mounting apparatus, for example, a plurality of CCD cameras are used to image the bumps and electrodes of the wiring board 32 and the semiconductor chip 35, and the true positions of the bumps and the like are calculated by calculation based on the plurality of images. Therefore, it is difficult to perform highly accurate alignment, and the state of the connected part after mounting cannot be imaged with a CCD camera, so inspection work must be performed in a separate process. The work was complicated.
[0043]
However, the semiconductor mounting apparatus according to this reference example uses X-rays as described above, and as shown in FIG. 11, while confirming a transmission image such as the wiring pattern, each pad, and the state of the bump, Since the electrodes and the like can be aligned, the accuracy of flip chip mounting can be improved. In addition, since it is possible to simultaneously check the wiring pattern by X-rays and inspect the mounting state, it is possible to simplify the inspection work and increase the reliability of the product.
[0044]
【The invention's effect】
As described above, according to the first semiconductor device and the method for manufacturing the semiconductor device of the present invention, the Ag bump comes into contact with the Al chip electrode through the Ni / Au plating layer, thereby suppressing the battery reaction. In addition to improving reliability over time, an Ag bump is formed following a process of forming a Cu wiring board electrode on the wiring board, and then a Ni / Au plating layer is formed. Therefore, it is possible to form an Ag bump and plate the surface before the Cu electrode is oxidized without changing the conventional process, and it is effective in preventing the oxidation of the electrode.
[Brief description of the drawings]
1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention in the order of manufacturing steps;
FIG. 2 is a flowchart showing manufacturing steps of the semiconductor device.
FIG. 3 is a diagram for explaining an effect of the semiconductor device.
4 is a cross-sectional view showing a semiconductor device according to a reference embodiment of the present invention in the order of manufacturing steps; FIG.
FIG. 5 is a cross-sectional view showing a semiconductor device according to another reference embodiment of the present invention in the order of manufacturing steps;
FIG. 6 is an enlarged perspective view of a bump of the semiconductor device.
FIG. 7 is an enlarged view of a connection portion by a bump of the semiconductor device.
FIG. 8 is an enlarged perspective view of a bump formed by conventional wire ball bonding.
FIG. 9 is a cross-sectional view showing a semiconductor device according to another reference embodiment of the present invention in the order of manufacturing steps;
FIG. 10 is a diagram illustrating an example of a semiconductor device mounting apparatus according to a reference example ;
FIG. 11 is a view showing an image obtained by the mounting apparatus.
FIG. 12 is a cross-sectional view of a conventional semiconductor device.

Claims (6)

配線基板と、この配線基板上にフリップチップ方式により実装された半導体チップとを備えた半導体装置において、
前記配線基板上に形成された配線基板電極と、
この配線基板電極上に形成されたＡｇバンプと、
このＡｇバンプが形成された配線基板電極上に形成されたＮｉ／Ａｕメッキ層と、
前記半導体チップ上に形成された前記Ｎｉ／Ａｕメッキ層を介して前記Ａｇバンプと接続されるＡｌからなるチップ電極と
を備えてなることを特徴とする半導体装置。In a semiconductor device comprising a wiring board and a semiconductor chip mounted on the wiring board by a flip chip method,
A wiring board electrode formed on the wiring board;
Ag bumps formed on the wiring board electrodes;
A Ni / Au plating layer formed on the wiring board electrode on which the Ag bump is formed;
A semiconductor device comprising: a chip electrode made of Al connected to the Ag bump through the Ni / Au plated layer formed on the semiconductor chip. Ａｇバンプは、Ａｇペーストをスクリーン印刷することによって形成されたものであることを特徴とする請求項１記載の半導体装置。  The semiconductor device according to claim 1, wherein the Ag bump is formed by screen printing of an Ag paste. 前記配線基板電極は、Ｃｕからなることを特徴とする請求項１又は２記載の半導体装置。  The semiconductor device according to claim 1, wherein the wiring board electrode is made of Cu. 前記配線基板と前記半導体チップとは、異方性導電フィルム、異方性導電ぺースト及び絶縁樹脂のうちの一つを塗布、貼付又は充填することにより接着されていることを特徴とする請求項１〜３のいずれか１項記載の半導体装置。The wiring board and the semiconductor chip are bonded by applying, pasting or filling one of an anisotropic conductive film, an anisotropic conductive paste, and an insulating resin. the semiconductor device of any one of 1-3. 配線基板上に配線基板電極を形成する工程と、この工程で形成された配線基板電極上にＡｇバンプを形成する工程と、この工程でＡｇバンプが形成されたＣｕの配線基板電極上にＮｉメッキを施した後、Ａｕメッキを施す工程と、前記Ｎｉ／Ａｕメッキ層が表面に形成された前記Ａｇバンプと半導体チップのＡｌからなるチップ電極とを位置合わせして熱圧着することにより前記半導体チップを前記配線基板上にフリップチップ実装する工程とを備えてなることを特徴とする半導体装置の製造方法。  Forming a wiring board electrode on the wiring board; forming an Ag bump on the wiring board electrode formed in this process; and plating Ni on the Cu wiring board electrode on which the Ag bump is formed in this process. The semiconductor chip by aligning the Ag bump having the Ni / Au plating layer formed on the surface thereof with the chip electrode made of Al of the semiconductor chip, and performing thermocompression bonding. And a step of flip-chip mounting on the wiring substrate. 前記配線基板上にＡｇバンプを形成する工程は、Ａｇペーストを前記配線基板電極上にスクリーン印刷して形成する工程であることを特徴とする請求項５記載の半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5 , wherein the step of forming the Ag bump on the wiring substrate is a step of forming an Ag paste by screen printing on the wiring substrate electrode.
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