TWI304632B - - Google Patents

Download PDF

Info

Publication number
TWI304632B
TWI304632B TW91124259A TW91124259A TWI304632B TW I304632 B TWI304632 B TW I304632B TW 91124259 A TW91124259 A TW 91124259A TW 91124259 A TW91124259 A TW 91124259A TW I304632 B TWI304632 B TW I304632B
Authority
TW
Taiwan
Prior art keywords
layer
trench
depth
sacrificial layer
semiconductor substrate
Prior art date
Application number
TW91124259A
Other languages
Chinese (zh)
Inventor
Yau-Ji Jang
Lu Jeff
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Priority to TW91124259A priority Critical patent/TWI304632B/zh
Application granted granted Critical
Publication of TWI304632B publication Critical patent/TWI304632B/zh

Links

Landscapes

  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)

Description

13046321304632

發明領域 修正 本發明係有關於半導體製程,特別有關於一種形成深 均一之淺溝渠隔離結構(Shan〇W trench is〇lation, S TI )的方法。 發明背景 隨著半導體積體電路(Jc)製造技術的發展,晶片中的 p 體元件數$不斷增加,元件的尺寸也因積集度的提昇 而不斷地縮小。而隨著元件尺寸的縮小化,晶片中各個元 件之間的絕緣或隔離結構也隨之縮小,其製造技術也需隨 之提升。 一在疋件隔離技術中,習知的局部矽氧化方法(L〇c〇s) 在元件尺寸微小化的情況下已不再適用,主要是因為鳥嘴 結構的侵飯問題。因此,淺溝渠隔離區(shallow trench 1 sol at ι〇η,STI )製程,由於具有隔離區域小和完成後仍 保持基底平坦性等優點,成為最常被採用的技術。 製作 成一 矽基 1C 内壁 成的 利用 將絕 學氣 a 。接著以第1A至1E圖說明習知的淺溝渠隔離結構的 流,。參見第1A圖,首先在半導體矽基底1〇上依序形 墊氧化物層12與一氮化矽層14。接著參見第1B圖,在 底1 0上以微影與蝕刻製程形成淺溝渠1 6。接著參見第 圖,將矽基底1 〇進行一熱氧化反應,以在淺溝渠1 6的 上:成内襯氧化物層1 8,藉以去除矽基底蝕刻時所造 材質損壞。接著參見第1 ])圖,於淺溝渠丨6之空間中, 化學氣相沈積法(chemical vapor dep〇siti〇n,CVD) 、緣才才/料(i s ο 1 a t ο r ) 1 9填入其中,例如以高密度電漿化FIELD OF THE INVENTION The present invention relates to semiconductor processes, and more particularly to a method of forming a deep uniform shallow trench isolation structure (S TI ). BACKGROUND OF THE INVENTION With the development of semiconductor integrated circuit (Jc) fabrication techniques, the number of p-body components in a wafer has been increasing, and the size of components has been continuously reduced due to an increase in the degree of integration. As the size of the components shrinks, the insulation or isolation structure between the components in the wafer is also reduced, and the manufacturing technology needs to be improved. In the case of the element isolation technology, the conventional partial oxidation process (L〇c〇s) is no longer applicable in the case of miniaturization of the component size, mainly due to the problem of invading the bird's beak structure. Therefore, the shallow trench 1 sol at ι〇η (STI) process has become the most commonly used technology due to its small isolation area and the flatness of the substrate after completion. The use of a sill-based 1C inner wall will result in a sufficiency of a. Next, the flow of the conventional shallow trench isolation structure will be described in Figs. 1A to 1E. Referring to Fig. 1A, an oxide layer 12 and a tantalum nitride layer 14 are sequentially formed on a semiconductor substrate 1 . Referring next to Fig. 1B, a shallow trench 16 is formed on the bottom 10 by a lithography and etching process. Referring to the figure, the ruthenium substrate 1 is subjected to a thermal oxidation reaction to form a lining oxide layer 18 on the shallow trench 16 to remove material damage during etching of the ruthenium substrate. Then refer to the figure 1)). In the space of the shallow trench, the chemical vapor dep〇siti〇n (CVD), the edge of the material (is ο 1 at ο r ) 1 9 Into it, for example, high-density plasma

第5頁 1304632 五、發明說明(2) 相沈積法(hi gh densi. + 石夕等絕緣材料填Λ、气y plasma CVD,HDP—CVD)將二氧化 (CMP)將表面平坦化义溝渠1 6中。最後則以化學機械研磨法 離結構,如第1E—圖所’_以在半導體基底10上形成淺溝渠隔 件。 ° 示’以隔離半導體基底10上的各元 在上述習知的萝 藉由乾式蝕刻,例★ ^ ’形成淺溝渠1 6的蝕刻步驟,係 烷(CFO、三敗甲烷(°c^活性離子蝕刻(ME),藉由四氣甲 去除墊氧化物12與t /3)與氬氣(Ar)混合作為反應氣體, 數千埃(A、卢士 石夕層1 4後’將石夕基底;i 〇向下银刻約 度通常以二時=力知的f程中,淺溝渠16的餘刻深 蝕刻深度的模式(tim、丑H 制。這種以蝕刻時間控制 偏# ),往往容易因為蝕刻機台的 g a $低ι $ 、、更換機台的影響,使得淺溝渠1 6的蝕刻深 ϊ Ϊ體元侔η ί溝渠結構間的蝕刻深度不一致,可能造成 不良影響。電性的問題,對於積體電路之品質控制產生 發明簡述 為了解決上述問 可控制淺溝渠結構深 度之溝渠。 本發明的另一個 構深度的方法,以製 根據本發明之— 一半導體基底上,包 的一 可穩 的係 均一 控制 下列 個目 定蝕 一種 淺 導 供一種 相同深 溝渠結 適用於 體基底 0503-8385TWF3;daphne.p t c 1304632 WJL· 五、發明說明(3) 上依序形成一終點控制層與一 成並定義具有一溝$ > 犧牲層。接著在犧牲層上形 以該能量感ί層為冓=案:;;;=;層’如光",並 形成一開口暴露該半導體美二犧t層與該终點控制層以 層,續以以一既定餘列5。之後,移除該能量感應 犧牲層至達到該終點控 之半導體基底與讀 比例約等於兹刻該半ί;;:;Λ 犧牲層之厚度二者的 率二者的比例。¥體基底之速率/韻刻該犧牲層之逮 犧牲層:i ί U ί:U優點在於藉由钕刻氣體對於 當厚度的犧牲基=的敍刻速率比例,予貝先沈積適 層時作為蝕刻終點之控制。由蝕刻至終點控制 刻速率比例相同,因并播;划氣體對不同材質的蝕 ^ ^ ^.. B„..犧牲層被蝕刻的厚度與溝渠蝕刻深 -成,比例關係’可穩定控制溝渠深度的均一性。 結構的::上更提供-種形成淺溝渠隔離 形成墊氧化物層、墊气化物# I先在半導體基底上依序 為幕罩,㈣犧牲層、終點 乂 物層以形成一開口暴露其下之半導體基底。:j 1嬸=^後、’以一既定银刻氣體#刻該暴露之半導體基底 '一 :、θ至達到終點控制層為止,以於半導體基底中形成 一溝渠,其中,該溝渠之深度/該犧牲層之厚度二者的比 例約等於蝕刻該半導體基底之速率/银刻該犧牲層之速率 _丨 FW ΐΚ 1Γ f[> ilJJLUJll UllLUJU .LJ JL UJ J.l JIJIU J. ..... … " 0503 -8385TWF3;daphne.p t c 1304632 修正 茶就^)1124259 年 月 五、發明說明(4) =者的比例。接著以熱氧化法在溝渠内側形成一内 勿層,亚沈積一絕緣材料以填滿該溝渠。最後,進 $製程以去除多餘之終點控制層而形成一淺溝渠隔離結旦 實施例 以下以第2A至2C圖詳細說明根據本發明之施 一種控制淺溝渠隔離結構蝕刻深度方法流程。 成- A第22ΑΓΐ:在一半導體石夕基底2〇上,以習知方式形 成墊層22。例如,一般在形成、淺溝隔離結構時 矽基底上通常依序形成墊氧化物層(pad 〇xide)盥墊氮化一 矽層(pad nitride)作為墊層結構22,以蝕 中提供矽基底絕緣保護。 佼只蚀刻衣私 接著仍參見第2A圖,在一般的墊層結構22上,進—舟 形成一終點控制層24與一犧牲層26。終點控制層24可藉= 常壓(atmospheric)或是低壓化學氣相沉積法(l〇w 曰Page 5 1304632 V. Description of the invention (2) Phase deposition method (hi gh densi. + Shi Xi et al., y plasma CVD, HDP-CVD) will planarize the surface of the oxidization (CMP) 6 in. Finally, the structure is removed by chemical mechanical polishing, as in the case of the first substrate, to form a shallow trench spacer on the semiconductor substrate 10. ° "Insulate the elements on the semiconductor substrate 10 in the above-mentioned conventional radish by dry etching, for example ^ ^ 'the formation of shallow trenches 16 etching step, silane (CFO, three-depleted methane (°c ^ active ions Etching (ME), by removing the pad oxide 12 with t / 3) and argon (Ar) as a reaction gas, several thousand angstroms (A, Lu Shishi layer 14 after 'will be Shi Xi base; i 〇 〇 银 银 银 通常 通常 通常 通常 通常 通常 通常 通常 通常 通常 通常 通常 通常 通常 通常 通常 通常 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银 银The etching machine's ga $low ι $, and the influence of the replacement of the machine, the etched depth of the shallow trench 16 不一致 Ϊ Ϊ ί ί ί ί 结构 结构 结构 结构 结构 结构 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻 蚀刻SUMMARY OF THE INVENTION For the quality control of the integrated circuit, a summary of the invention is provided to solve the problem of controlling the depth of the shallow trench structure. Another method of constructing the depth of the present invention is to fabricate a semiconductor substrate according to the present invention. Steady system uniform control of the following The shallow guide is used for the same deep groove junction suitable for the body base 0503-8385TWF3; daphne.ptc 1304632 WJL·5, the invention description (3) sequentially forms an end point control layer and a layer and defines a groove $ > sacrificial layer Then, the energy layer is formed on the sacrificial layer as 冓=case:;;;=; layer 'such as light", and an opening is formed to expose the semiconductor layer and the end point control layer Continued with an established remainder of 5. After that, the energy sensing sacrificial layer is removed until the semiconductor substrate and the read ratio of the endpoint are approximately equal to the ratio of the thickness of the sacrificial layer; The ratio of the two. The rate of the base of the body / the rhyme of the sacrifice layer of the sacrificial layer: i ί U ί: U advantage lies in the ratio of the rate of sacrificial rate of the thickness of the sacrificial base = When the stratified layer is deposited, it is used as the control of the etch end point. The ratio of the etch rate to the end point control is the same, because the gas is etched on different materials. ^ ^.. B„.. The thickness of the sacrificial layer is etched and the trench is etched deep. - Cheng, proportional relationship 'stable control of the uniformity of the ditch depth. The structure:: further provides a shallow trench isolation to form a pad oxide layer, a pad gas #1 first on the semiconductor substrate sequentially as a mask, (4) a sacrificial layer, an end point layer to form an opening to expose the underside After the semiconductor substrate: j 1 婶 = ^, 'with a predetermined silver engraved gas # engraved the exposed semiconductor substrate '1:, θ until reaching the end control layer to form a trench in the semiconductor substrate, wherein The ratio of the depth of the trench/the thickness of the sacrificial layer is approximately equal to the rate at which the semiconductor substrate is etched/the rate at which the sacrificial layer is engraved _丨FW ΐΚ 1Γ f[> ilJJLUJll UllLUJU .LJ JL UJ Jl JIJIU J... ... " 0503 -8385TWF3;daphne.ptc 1304632 Corrected tea on ^) 1124259, the fifth month, the invention description (4) = the proportion of the person. Then, a layer of inner layer is formed on the inner side of the trench by thermal oxidation, and an insulating material is deposited to fill the trench. Finally, the process is performed to remove the excess endpoint control layer to form a shallow trench isolation junction. Embodiments The method of controlling the etch depth of the shallow trench isolation structure according to the present invention will be described in detail below with reference to FIGS. 2A to 2C. Form - A 22nd: On a semiconductor substrate 2, a mat 22 is formed in a conventional manner. For example, generally, in the formation of a shallow trench isolation structure, a pad oxide layer (pad nitride) is generally formed on the germanium substrate as a pad structure 22 to provide a germanium substrate in the etch. Insulation protection.佼Immediately etching only the garments. Referring now to Figure 2A, on a typical bedding structure 22, the inlet boat forms an end point control layer 24 and a sacrificial layer 26. The endpoint control layer 24 can be controlled by atmospheric pressure or low pressure chemical vapor deposition (l〇w 曰

Pressure chemical vapor deposit ion,LPCVD)沉積四乙 氧基矽烷(TEOS)作為氧化物層,厚度約為3〇〇〜5〇〇埃(a) 左右。而犧牲層26可藉由低壓化學氣相沉積法(LpcvD), 以二氯矽烷(SiCl2%)與氨氣(NH3)為反應原料沉積形成氮 化矽層。而此犧牲層26的厚度(D1),乃用以決定後續欲形 成之溝渠深度(D2)。根據後續溝渠蝕刻所欲採用的蝕刻氣 體配方對於犧牲層2 6與矽基底2 0的蝕刻速率比,換算出欲 形成之犧牲層2 6的厚度(D1 )。 "在一實施例中,後續溝渠蝕刻氣體配方為氯氣(Cl2) 與氣氣(02)之混合氣體進行電漿蝕刻,其氯氣與氧氣混合 " ________ 、 0503-8385TWF3;daphne.ptc 第8頁 1304632Pressure chemical vapor deposition (LPCVD) deposits tetraethoxy decane (TEOS) as an oxide layer having a thickness of about 3 〇〇 5 5 Å (a). The sacrificial layer 26 can be deposited by a low pressure chemical vapor deposition method (LpcvD) with dichlorosilane (SiCl2%) and ammonia (NH3) as a reaction material to form a ruthenium nitride layer. The thickness (D1) of the sacrificial layer 26 is used to determine the depth of the trench (D2) to be subsequently formed. The thickness (D1) of the sacrificial layer 26 to be formed is converted according to the etching rate ratio of the sacrificial layer 26 to the germanium substrate 20 in accordance with the etching gas formulation to be used for subsequent trench etching. " In an embodiment, the subsequent trench etching gas formulation is plasma etching of a mixed gas of chlorine gas (Cl2) and gas (02), and the chlorine gas is mixed with oxygen" ________, 0503-8385TWF3; daphne.ptc 8th Page 1304632

^列約為15 :1 ’而電梁兹刻之壓力為20〜40毫托耳,電 浆源功率約為40 0瓦特’偏壓功率 案號 91124259 五、發明說明(5) 蝕刻對氮化矽犧牲層26與該半導此%電水 1 . 3。因此,虽欲形成深度3〇〇〇埃左 LPCVD形成1000埃左右之氮化石夕犧牲層26。 則以 而在犧牲層26形成後,則接著在 『盖=參見第2B圖,以一般微影製程在光阻 義「溝渠開口圖案,並以其為幕罩,韻刻其 疋 終點控制層24與塾層結構22,以形成溝渠開口“ 接著參見第2C圖,在去除光阻層28後,接著 蝕刻。如上所述,溝渠蝕刻採用氯氣隹二 ”㈣’而㈣終點則控制在犧牲層26:二:=: 露出終點控制層24為止。在一實施例φ 庋蝕亥"夕除至 籠〇及/細㈣⑼認中 =物=爾號,則表示 乱化物層已被姓刻完畢。或者,當出現⑶ 已經蝕刻到做為終點控制層24的氧化物層:心上:表: CN彳§號的彳貞測作為银刻終點的判斷。 θ 5 由於已預先根據電漿蝕刻對於氮化矽鱼 =率,以及欲形成的溝渠深度⑽3〇。。埃夕= 矽犧牲層26的厚度(D1)為ι 0 0 0埃,因此告、汁开出虱化 化矽犧牲層26均.被蝕刻氣體移除時,^ :度1 0 0 0埃之氮 步被蝕刻出深度30 0 0埃之溝渠3〇。、』代表矽基底2〇已同 ^根據上述方預定形成之深度與^ Column is about 15:1 'and the voltage of the electric beam is 20~40 mTorr, and the plasma source power is about 40 watts. 'Bias power case number 91124259 V. Invention description (5) Etching on nitriding The sacrificial layer 26 and the semiconductor are electrically conductive. Therefore, although it is desired to form a depth of 3 Å, the left LPCVD forms a nitride sacrificial layer 26 of about 1000 Å. Then, after the formation of the sacrificial layer 26, then in the cover = see Figure 2B, in the general lithography process in the photoresist "ditch opening pattern, and as a mask, rhyme engraving its end point control layer 24 The germanium layer structure 22 is formed to form a trench opening. Referring next to FIG. 2C, after the photoresist layer 28 is removed, etching is then performed. As described above, the trench is etched with chlorine gas ”"(4)" and (4) the end point is controlled at the sacrificial layer 26: two: =: the end point control layer 24 is exposed. In an embodiment φ 庋 亥 & & 夕 夕 夕 夕 夕/fine (four) (9) acknowledgment = object = er, which means that the disordered layer has been engraved by the surname. Or, when (3) has been etched into the oxide layer as the endpoint control layer 24: on the heart: Table: CN彳§ The speculation is judged as the end point of the silver engraving. θ 5 Since the plasma etching is based on the etched squid = rate, and the depth of the trench to be formed (10) 3 〇. Essence = thickness of the sacrificial layer 26 (D1) It is ι 0 0 0 angstroms, so the sputum and juice are opened and the sacrificial layer 26 is removed. When the etching gas is removed, the nitrogen step of 1 : 0 0 angstrom is etched to a depth of 30 0 0 Å. 3〇., ” represents the base of the base 2 has been the same as the depth formed by the above-mentioned party

〇5〇3-8385TlVF3;daphne.ptc 第9頁 1304632 修正 91124^0__^ 五、發明說明(6) 溝渠蝕刻時對於犧牲層與矽基底的蝕 適當厚声夕禮、M ^ t匕 可以沈積 式較::Γ= 控制溝渠钱刻的钱刻終點。上述方 itii 間控删終點,可不受钱刻機台種 深度;更此準確的控制溝渠的银刻深度,達成溝渠 ,由ίϊίϊΐ憂點’以下進一步藉由第3A至3E圖詳細說明 ^。述拴蝕刻深度方法以形成淺溝渠隔離結構之方法流 、參見第3A圖,在半導體矽基底20上,以習知 形成墊氧化物層21與墊氮化物層23以作為絕緣結構1,々提 緣保護。塾氧化層21可利用熱氧化法於矽基底 上开y成虱化矽,或是以低壓化學氣相沉積法(1 ow〇5〇3-8385TlVF3;daphne.ptc Page 9 1304632 Amendment 91124^0__^ V. Description of invention (6) Corrosion of sacrificial layer and ruthenium base during trench etching is appropriate, M ^ t匕 can be deposited Comparison::Γ= Control the end of the money engraved in the ditch. The above-mentioned party itii controls the end point, which can be used without the money to mark the depth of the machine; more precisely, the depth of the silver engraving of the ditches can be controlled to reach the ditches, which are further explained by the figures 3A to 3E below. Referring to FIG. 3A, the etch depth method is described to form a shallow trench isolation structure. Referring to FIG. 3A, a pad oxide layer 21 and a pad nitride layer 23 are conventionally formed on the semiconductor germanium substrate 20 as an insulating structure 1. Edge protection. The tantalum oxide layer 21 can be opened by a thermal oxidation method on the tantalum substrate, or by low pressure chemical vapor deposition (1 ow).

Pressure chemical vapor deposit ion,LPCVD)沉積四乙 軋基矽feXTEOS)作為墊氧化物層,厚度約為丨丨〇埃(人)左 右。而墊氮化物層23可藉由低壓化學氣相沉積法 工 (LPWD),—以二氯矽烷與氨氣(NH3)為反應原料沉 積形成墊氮化矽層,較佳厚度為丨6 2 5埃左右。 接著仍參見第3A圖,在墊氮化矽層23上,進一步形成 終點控制層24與犧牲層26。終點控制層24可藉由常壓 (atmospheric)或是低壓化學氣相沉積法(;[〇w pressure chemical vapor depositi〇n,LpcVD)沉積四乙氧基矽烷 (TEOS)作為氧化物層,厚度約為3〇〇〜5〇〇埃(a )左右。而 犧牲層26可藉由低壓化學氣相沉積法(LpcvD),以二氯矽 烧(Si(312¾)與氨氣(NHS)為反應原料沉積形成氮化矽層。 而此犧牲層26的厚度(D1),乃用以決定後續欲形成之溝渠 0503-8385TWF3;daphne. p t c 第10頁 1304632 修正 月 曰 _案號 91124259 五、發明說明(7) 沬度(D2)。根據後續溝渠蝕刻所欲採用的蝕 ^乍為犧牲層26之氮切層與⑪基㈣的㈣料比,= 异出欲形成之犧牲層2 6的厚度(d 1)。 ,一實施例中,後續溝渠蝕刻氣體配方為氯氣(Cl2) 與乳氣(〇2)之混合氣體進行電t蝕刻,其氯氣 比例約為15 :卜而電漿㈣之…20〜40毫:耳口 漿源功率約為400瓦特,偏壓功率約為3〇〇瓦特,此時 蝕刻對氮化矽犧牲層26與該半導體矽基底2〇 為 因此,當欲形成深度3_埃左右之溝渠時=為 LPCVD形成1 0 0 0埃左右之氮化梦犧牲層26。卞才則以 而在犧牲層2 6形成後,則接著在犧牲層2 6上蓋一 一8、盖ΐ著參見第36圖’以一般微影製程在光阻層28上 =義故溝朱開口圖案,並以其為幕罩,蝕刻其下的犧牲声 成溝==與塾氮化物層23與塾氧化物層21,㈣ =參見第3C圖’去除光阻層28後,接著進行溝渠钱 q j所述’溝渠㈣採用I氣與氧氣混合氣體進行電 :二控制在犧牲層 出、、、…W工制層24為止。在一實施例中,可 測CO及/或CN信號以確認電漿蝕列0 水x 、 声。例如# t、+ a 刻疋否已達到該終點控制 :二:信號,則表示作為犧牲層26的氮 化物層已被蝕刻完畢。或者 一 ,到做為終點控制層24的氧化物層=上 仏號的偵測作為蝕刻終點的判斷。 3 氮化石夕犧牲層2 6與石夕基 第11頁 0503-8385TWF3;daphne.ptc 1304632 r-t月日 倐正_; 五、發明說明(8) 一"—- 底20之餘刻速率’以及欲形成的溝渠深度(D2),言十算出氮 化矽犧牲層26之厚度(D1),因此當厚度〇1之氮化矽犧牲層 2 6均被钱刻氣體移除時,則代表矽基底2 〇同步被蝕刻出深 度D2之溝渠30。 接著參見第3D圖,當矽基底2〇上的溝渠3〇形成後,則 將矽基底2 0進仃一熱氧化製程,使溝渠3 〇的内壁形成内襯 氧化物層(liner oxide)32,以去除矽基底2〇溝渠蝕刻過 程所可能造成的材質損壞。 最後參見第3E圖,在溝渠3〇中填充絕緣材料。例如, 以高密度電漿沉積法(high density plasma deposition,HDPCVD),將絕緣氧化物填入溝渠3〇中。而 溝渠30外多餘的氧化物或氮化物層等,則續以回蝕刻或化 學機械研磨法(chemical mechanical p〇lishing,CMp)去 除,以得到平坦化的淺溝渠隔離結構34以隔離半導體基底 2 0上的元件。 根據本發明,上述方法中的犧牲層並非僅限於氮化物 材質、’僅需選擇適當之材質,與半導體基底間具有適當之 蝕刻f擇比即彳。再者,上述終點控制層亦非僅限定於氧 化物θ僅而選擇與犧牲層不同之材質,以達到終點控制 的效果即可。 根據上述說明,本發明之優 侷限於由蝕刻時間控制,而可藉 矽基底的蝕刻速率比,而計算出 藉以控制溝渠的餘刻終點。因此 左丄亡丨1 卷触;ΪΚ:7 + η士 ,》Pressure chemical vapor deposition (LPCVD) is deposited as a pad oxide layer having a thickness of about 丨丨〇 (human). The pad nitride layer 23 can be deposited by a low pressure chemical vapor deposition process (LPWD) using a mixture of dichlorosilane and ammonia (NH3) to form a pad nitride layer, preferably having a thickness of 丨6 2 5 . Around. Next, referring to Fig. 3A, on the pad nitride layer 23, an end point control layer 24 and a sacrificial layer 26 are further formed. The end point control layer 24 can deposit tetraethoxy decane (TEOS) as an oxide layer by atmospheric or low pressure chemical vapor deposition (LPCVD), and has a thickness of about It is about 3〇〇~5〇〇(a). The sacrificial layer 26 can be deposited by a low pressure chemical vapor deposition method (LpcvD) with dichlorohydrazine (Si (3123⁄4) and ammonia (NHS) as a reaction material to form a tantalum nitride layer. The thickness of the sacrificial layer 26 (D1), is used to determine the subsequent formation of the ditches 0503-8385TWF3; daphne. ptc page 10 1304632 revised month 曰 _ case number 9124259 five, invention description (7) 沬 degree (D2). According to the subsequent trench etching The etch is used as the ratio of the nitrogen cut layer of the sacrificial layer 26 to the (four) ratio of the 11 base (four), and the thickness (d 1) of the sacrificial layer 26 formed by the different formation. In one embodiment, the subsequent trench etching gas recipe For the gas mixture of chlorine gas (Cl2) and milk gas (〇2), the ratio of chlorine gas is about 15: and the plasma (4) is 20~40 millimeters: the power of the ear pulp source is about 400 watts. The voltage power is about 3 watts. At this time, the tantalum nitride sacrificial layer 26 and the semiconductor germanium substrate 2 are etched. Therefore, when a trench having a depth of about 3 angstroms is formed, it is formed by LPCVD to about 100 angstroms. The nitrided sacrificial layer 26 is formed so that after the sacrificial layer 26 is formed, the sacrificial layer 26 is then covered one by one. 8. Cover the 参见 参见 参见 参见 参见 参见 参见 参见 参见 参见 参见 参见 参见 参见 参见 参见 参见 参见 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般 一般Layer 23 and tantalum oxide layer 21, (4) = see Figure 3C, after removing the photoresist layer 28, then the trench is used. The trench (4) is electrically gas-mixed with I gas: the second control is at the sacrificial layer. In the embodiment, the CO and/or CN signals can be measured to confirm the electric erosion of the water 0, sound. For example, #t, + a 疋 has reached the end point control : 2: The signal indicates that the nitride layer as the sacrificial layer 26 has been etched. Or, the detection of the oxide layer = the upper layer as the end point control layer 24 is judged as the etching end point. Xisheng sacrificial layer 2 6 and Shi Xiji page 11 0503-8385TWF3; daphne.ptc 1304632 rt month 倐 _ ;; 5, invention description (8) a "-- bottom 20 after the rate ' and the formation Ditch depth (D2), the tenth is calculated as the thickness of the tantalum nitride sacrificial layer 26 (D1), so when the thickness 〇1 of the tantalum nitride sacrificial layer 26 When the gas is removed, the trenches 30 of the depth D2 are simultaneously etched on behalf of the germanium substrate 2. Next, referring to Fig. 3D, when the trenches 3 on the germanium substrate 2 are formed, the germanium substrate 20 is introduced. A thermal oxidation process causes the inner wall of the trench 3 to form a liner oxide 32 to remove material damage that may result from the etching process of the germanium substrate. Finally, see Figure 3E, filling the trench 3〇 with insulating material. For example, an insulating oxide is filled into the trench 3 by high density plasma deposition (HDPCVD). The excess oxide or nitride layer outside the trench 30 is continuously removed by etch back or chemical mechanical polishing (CMp) to obtain a planar shallow trench isolation structure 34 to isolate the semiconductor substrate 2 The component on 0. According to the present invention, the sacrificial layer in the above method is not limited to the nitride material, and it is only necessary to select an appropriate material, and has an appropriate etching ratio between the semiconductor substrate and the semiconductor substrate. Further, the above-mentioned end point control layer is not limited to the oxide θ only, and a material different from the sacrificial layer is selected to achieve the effect of the end point control. In light of the above description, the present invention is advantageously limited to the etching time control, and the residual end point of the trench can be calculated by the etching rate ratio of the substrate. Therefore, the left-handed death is 1 touch; the ΪΚ:7 + η士,》

1304632 _案號91124259_年月曰 修正_ 五、發明說明(9) 成均一的淺溝渠隔離結構之溝渠深度的控制,有效掌控半 導體製程品質。 雖然本發明以較佳實施例揭露如上,然其並非用以限 定本發明,任何熟悉此項技藝者,在不脫離本發明之精神 和範圍内,當可做些許更動與潤飾,因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。1304632 _ Case No. 91124259_年月曰 修正 Amendment _ V. Description of invention (9) The control of the ditch depth of the shallow ditch isolation structure of the uniform one, effectively control the quality of the semi-guided process. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

0503-8385TWF3;daphne.p t c 第13頁 1304632 _案號91124259_年月曰 修正_ 圊式簡單說明 為了讓本發明之上述目的、特徵、及優點能更明顯易 懂,以下配合所附圖式,作詳細說明如下,其中,相同之 圖式符號代表相同或相似之元件: 圖式簡單說明 第1 A至1 E圖所示為習知的一種淺溝渠隔離結構製造流 程侧視圖。 第2 A至2 C圖所示為根據本發明之一實施例中,一種控 制淺溝渠隔離結構蝕刻深度方法流程。 第3 A至3 E圖所示為根據本發明之一實施例中,一種形 成淺溝渠隔離結構的方法流程。 符號說明 10 半 導 體 基 底 ( 矽 基底 半 導 體矽 基 底); 12 墊 氧 化 物 層 ( 塾 氧 化 物 ) , 14 氮 化 矽 層 16 溝 渠 ( 淺 溝 渠 ) , 18 内 襯 氧 化 物 層 19 墊層 ( 絕 緣 材 料 ) , 20 半 導 體 基 底 ( 矽 基 底 半 導 體矽 基 底)·’ 21 墊 氧 化 物 層 ( 墊 氧 化 層 ) 9 22 塾 層 ( 塾 層 結 構 ) j 23 墊 氮 化 物 層 j 24 終 點 控 制 層 , 26 犧 牲 層 ( 氮 化 矽 犧 牲 層 ) 90503-8385TWF3; daphne.ptc Page 13 1304632 _ Case No. 91124259_年月曰 _ _ 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 为了 为了 为了 为了 为了 为了 为了 为了 为了DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the same drawing symbols represent the same or similar elements: Brief Description of the Drawings Figures 1A to 1E show a side view of a conventional shallow trench isolation structure manufacturing process. 2A through 2C are diagrams showing a method of controlling the etching depth of a shallow trench isolation structure in accordance with an embodiment of the present invention. Figures 3A through 3E illustrate a process flow for forming a shallow trench isolation structure in accordance with one embodiment of the present invention. DESCRIPTION OF SYMBOLS 10 Semiconductor substrate (矽 base semiconductor 矽 substrate); 12 pad oxide layer (塾 oxide), 14 矽 nitride layer 16 trench (shallow trench), 18 lining oxide layer 19 underlayer (insulating material), 20 Semiconductor substrate (矽 base semiconductor 矽 substrate) · ' 21 pad oxide layer (pad oxide layer) 9 22 塾 layer (塾 layer structure) j 23 pad nitride layer j 24 endpoint control layer, 26 sacrificial layer (tantalum nitride Sacrificial layer) 9

0503 -8385TWF3;daphne.p t c 第14頁 13046320503 -8385TWF3;daphne.p t c Page 14 1304632

0503-8385TWF3;daphne.ptc 第15頁0503-8385TWF3;daphne.ptc第15页

Claims (1)

I3〇4632 ^lS_iU24259I3〇4632 ^lS_iU24259 六、申請專利範圍 '· 2控制溝渠蝕刻深度的方法,適用於 &上,包含下列步驟: 千^體基 層;在该半導體基底上依序形成一終點控制層與一犧牲 在該犧牲層上形成並定義具有一溝渠 層, M木之一光阻 # &以遠光阻層為幕罩,蝕刻該犧牲層與該終& > 化成一開口暴露該半導體基底; …占控制層以 移除該光阻層;以及 =一既定蝕刻氣體蝕刻該暴露之半導體基 m達到該終點控制層為止,以於該半導體启=b羲牲 溝渠; 守股基底中形成一 ^中,該溝渠之深度/該犧牲層之厚度二者 的/虫刻該半導體基底之速率/蝕刻該犧牲層之」ς 的比例。 心平_者 2·根據申請專利範圍第1項所述之控制 的方法,直Φ承A人 巾」/莓本餘刻深度 云/、中更包含一步驟:在形成該終點控制M A ^ 形成-墊層於該半導體基底上。 Μ層則,先 的Λ根irf專利範圍第2項所述之控制溝渠飯刻深度 的方法,其中該墊層更包含一墊氧化物層木度 依序形成於該半導體基底上。 t鼠化石夕層 4. 根據申請專利範圍第2項所述之控制 的方法’其中該終點控制層包括氧化物層。卞兹到-度 5. 根據申請專利範圍第1項所述之控制溝渠蝕刻深度Sixth, the scope of application for patents '· 2 method for controlling the etching depth of the trench, applicable to & includes the following steps: a base layer; sequentially forming an end point control layer on the semiconductor substrate and a sacrificial layer on the sacrificial layer Forming and defining a trench layer, M wood one photoresist # & with a far photoresist layer as a mask, etching the sacrificial layer and the final &> into an opening to expose the semiconductor substrate; ... occupy the control layer to shift In addition to the photoresist layer; and = a predetermined etching gas etches the exposed semiconductor substrate m to reach the endpoint control layer, so that the semiconductor is turned into a ditch; a solid is formed in the base of the holding, the depth of the trench / The thickness of the sacrificial layer is / the ratio of the rate at which the semiconductor substrate is etched/the etch of the sacrificial layer.心平_者2· According to the method of control described in the first paragraph of the patent application, the straight-through A-body towel/Raspberry depth depth cloud/, the middle includes a step: in the formation of the end point control MA ^ formation - A mat is layered on the semiconductor substrate. The method of controlling the depth of the trench as described in the second item of the irf irf patent range, wherein the underlayer further comprises a pad oxide layer of wood formed sequentially on the semiconductor substrate. The mouse fossil layer 4. The method of controlling according to the scope of claim 2 wherein the endpoint control layer comprises an oxide layer.到到到度 degrees 5. Control trench etch depth as described in item 1 of the scope of the patent application 0503-8385TWF3;daphne.ptc 第16頁 1304632 修正0503-8385TWF3;daphne.ptc Page 16 1304632 Fix 的方法,其中形成該犧牲層係以低壓化學氧相、士拉 (LPCVD)形成氮化石夕層。'“'低’山乳相沈積法 盖號 9Π242Μ 六、申請專利範圍 的方6法根ί if第5項所述之控制溝渠飯刻深度 气"n、Z、中以该既疋蝕刻氣體蝕刻,係以氯氣(C1 乳亂(02)之混合氣體反應進行一電漿餘刻。 2)與 的方v艮ί nd圍第6項所述之控制溝渠餘刻深度 與該犧牲層Π; : ::L氣㈣刻該暴露之半導體基底 带蔣: 點控制層為止之步驟更包合:产# ^ p 偵測一co及/或—⑶信號以確認該電f # : 否已達到該終點控制層。 水餘刻疋 8 ·根據申請專利if圚穿D 的方法,其中該氣氣:^6項所述之控制溝渠钱刻深度 15… ……混合氣體之混合比例約為 9. 根據申請專利範圍第8 的方法’該電㈣刻之壓力物二毫Γ耳Λ刻深度 率約為40 0瓦特,偏壓功率 成电槳源功 該犧牲層與該半導體基底’、、、 寸’而该電漿蝕刻對 10. 根據申請專利範圍第1比約為1 :3。 的方法,其中形成該犧牲層、二斤S控制溝渠蝕刻深度 度之1/3。 尽度約為該欲形成之溝渠深 11. 根據申請專利範圍第丨〇項 度的方法,其中該犧牲層之、 之彳工制溝渠蝕刻深 溝渠深度約為3 0 0 〇埃。 X ”、 ’、 〇 0 0埃,而所形成之 12. 根據申請專利範圍第 之 _一^‘制溝渠餞刻深度The method of forming the sacrificial layer forms a nitride layer by a low pressure chemical oxygen phase, LPCVD. '''Low' mountain milk phase deposition method cover number 9Π242Μ Six, the patent scope of the party 6 Fagan ί If the control of the ditch as described in item 5 depth gas "n, Z, in the 疋 疋 etching gas Etching, the chlorine gas (C1 milk chaos (02) mixed gas reaction to carry out a plasma residue. 2) and the square v艮ί nd surrounding the control of the trench depth depth and the sacrificial layer 第; ::L gas (four) engraved the exposed semiconductor substrate with Chiang: point to the control layer is more involved: production # ^ p detect a co and / or - (3) signal to confirm the electricity f # : No has reached this End point control layer. Water residual engraving ·8 · According to the method of applying for patent if 圚D, where the gas: ^6 item controls the ditch depth of the groove 15... The mixing ratio of the mixed gas is about 9. Patent application No. 8 method 'The electric (four) engraved pressure material has a depth of about 40 watts, and the bias power is the electric power source of the sacrificial layer and the semiconductor substrate ',,, inch' And the plasma etching pair 10. The method according to the first aspect of the patent application is about 1:3, wherein the sacrificial layer is formed Two kilograms of S control trench etch depth of 1/3. The full extent is about the depth of the trench to be formed. 11. According to the method of the patent application scope, the fabrication of the sacrificial layer is completed by trenching The depth of the deep trench is about 300 angstroms. X ”, ', 〇 0 0 angstroms, and the formed 12. 12. According to the scope of the patent application, the depth of the trench is etched. 0503~8385WF3;daphne.ptc 1304632 _案號91124259_年月曰 修正___ 六、申請專利範圍 的方法’其中於該半導體基底中形成一溝渠之後更包括· 以熱氧化法在該溝渠内側形成一内襯氧化物層; 沈積一絕緣材料以填滿該溝渠;以及 進行一平坦化製程以去除多餘之該終點控制層而形成 一淺溝渠隔離結構。 1 3 ·根據申請專利範圍第1 2項所述之控制溝渠蝕刻深 度的方法’其中沈積該絕緣材料係以高密度電漿氣相沈積 法(HDPCVD)沈積氧化物。 1 4 ·根據申請專利範圍第1 2項所述之控制溝渠蝕刻深 度的方法,其中進行該平坦化製择#進行一化學機械研磨 (CMP 卜0503~8385WF3;daphne.ptc 1304632 _Case No. 91124259_Yearly revision ___ Sixth, the method of applying for a patent range] wherein after forming a ditch in the semiconductor substrate, a further includes: forming a inside of the trench by thermal oxidation Lining an oxide layer; depositing an insulating material to fill the trench; and performing a planarization process to remove the excess endpoint control layer to form a shallow trench isolation structure. 1 3 . The method of controlling the etch depth of a trench according to item 12 of the patent application, wherein the insulating material is deposited by high density plasma vapor deposition (HDPCVD). 1 4 · A method for controlling the etching depth of a trench according to claim 12 of the patent application, wherein the flattening is performed to perform a chemical mechanical polishing (CMP) 1304632 案號 911242M 四、中文發明摘要(發明之名稱1304632 Case No. 911242M IV. Summary of Chinese Invention (Name of Invention 一種控制淺溝 下。在半導體基底 犧牲層。接著在犧 阻層,並以該光阻 與墊層以形 後’以一既 層至達到終 渠,而其中 約等於蝕刻 者的比例。 成一開 定蝕刻 點控制 ,該溝 該半導 渠隔離 上依序 牲層上 層為幕 口暴露 氣體钱 層為止 渠之深 體基底 本案指定代表圖·· 案指定代表圖 (發明之名稱:) (一)本 英文發明摘要 mi度的方法’其步驟如 一墊層、一終點控制層I 一 ^成亚定義具有一溝渠圖案之光 罩,蝕刻犧牲層、終點劁先 其下之半導體基底。移二曰、 刻該暴露之半導體二除先阻層 产以於半導體基底;=該:牲 度/該犧牲層之厚声形成一溝 之速㈣刻該犧; 為·第(One is to control the shallow ditch. On the semiconductor substrate sacrificial layer. Then, at the sacrificial layer, the photoresist and the underlayer are patterned to form a final channel, which is approximately equal to the ratio of the etcher. The etch point control is opened, and the upper layer of the semi-channel is isolated as the deep layer of the channel exposed to the gas layer, and the designated representative figure of the case is designated (the name of the invention:) A) The method of the invention of the present invention is as follows: a step, an end point control layer, a mask, a mask having a trench pattern, a sacrificial layer, and a semiconductor substrate underneath. Moving the second semiconductor, the exposed semiconductor is removed from the semiconductor substrate; = the: the thickness of the sacrificial layer forms a ditch (four) engraving; 13046321304632 0503-8385TWF3;daphne.pt c 第3頁0503-8385TWF3;daphne.pt c Page 3
TW91124259A 2002-10-21 2002-10-21 TWI304632B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW91124259A TWI304632B (en) 2002-10-21 2002-10-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW91124259A TWI304632B (en) 2002-10-21 2002-10-21

Publications (1)

Publication Number Publication Date
TWI304632B true TWI304632B (en) 2008-12-21

Family

ID=45070978

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91124259A TWI304632B (en) 2002-10-21 2002-10-21

Country Status (1)

Country Link
TW (1) TWI304632B (en)

Similar Documents

Publication Publication Date Title
TW490796B (en) Method for fabricating an air gap shallow trench isolation (STI) structure
TWI301644B (en) Self-aligned contact etch with high sensitivity to nitride shoulder
US6507081B2 (en) In-situ silicon nitride and silicon based oxide deposition with graded interface for damascene application
TW484185B (en) Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a demascene etch scheme
US20070290293A1 (en) Liner for shallow trench isolation
TW200300980A (en) Process for selectively etching dielectric layers
JP2001244337A (en) Method and apparatus for forming film on substrate
US6933206B2 (en) Trench isolation employing a high aspect ratio trench
TWI225685B (en) Method forming metal filled semiconductor features to improve structural stability
TW201010026A (en) Through substrate via including variable sidewall profile
TWI288430B (en) Structure with via hole and trench and the fabrication method thereof
TWI263252B (en) Method for forming STI structures with controlled step height
TW413866B (en) Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher
US20060003560A1 (en) Method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure
TW540135B (en) Method of forming shallow trench isolation region
TWI258204B (en) Method for fabricating deep trench capacitor
TW201204200A (en) Manufacturing method for a buried circuit structure
TWI253692B (en) STI liner for SOI structure
TWI304632B (en)
CN101197304A (en) Method for forming isolation structure of shallow plough groove
TW506105B (en) Method for forming interconnect
TW200837876A (en) Gap filling method and method for fabricating shallow trench isolation
TWI240360B (en) Forming method of trench isolation region
TW589703B (en) Method of reducing the trench aspect ratio
TW544807B (en) Method for forming shallow trench isolation

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees